US10950712B2 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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US10950712B2
US10950712B2 US16/425,960 US201916425960A US10950712B2 US 10950712 B2 US10950712 B2 US 10950712B2 US 201916425960 A US201916425960 A US 201916425960A US 10950712 B2 US10950712 B2 US 10950712B2
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insulating layer
substrate
gate structure
sidewall
region
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Chu-Ming Ma
Hung-Chi Huang
Hsien-Ta Chung
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United Microelectronics Corp
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H01L29/66689—
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H01L29/1095—
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane

Definitions

  • the present invention generally relates to a semiconductor device and method for forming the same. More particularly, the present invention relates to a semiconductor device having asymmetric gate structure and method for forming the same.
  • Double-diffused metal-oxide-semiconductor (DMOS) devices have drawn much attention recently.
  • Conventional DMOS devices are categorized into vertical double-diffused MOS (VDMOS) devices and lateral double-diffused MOS (LDMOS) devices.
  • VDMOS vertical double-diffused MOS
  • LDMOS lateral double-diffused MOS
  • a key parameter for power device is the breakdown voltage, which usually refers to the highest voltage the device may sustain during operation.
  • the drift region in a conventional LDMOS usually requires a certain area of the substrate and has cause hindrance for device minimization. Therefore, there is still a need in the field to provide a semiconductor device which may facilitate device minimization and also provide better voltage endurance.
  • One objective of the present invention is to provide a semiconductor device having higher break-down voltage by performing a selective oxidation process to form an insulating layer on a sidewall of the gate structure adjacent to the drain region and rounding a bottom corner of the gate structure.
  • the present invention provides a semiconductor device including a substrate, a gate structure disposed on the substrate and comprising a first sidewall and a second sidewall opposite to the first sidewall, a gate dielectric layer disposed between the gate structure and the substrate, a first insulating layer disposed on the gate dielectric layer and covering the first sidewall of the gate structure, and a pair of spacers respectively disposed on the first insulating layer and on the second sidewall of the gate structure.
  • the first insulating layer comprises a first bird's beak portion covering a rounded bottom corner of the gate structure.
  • the present invention provides a method for forming a semiconductor device including providing a substrate, forming a gate structure on the substrate, wherein the gate structure comprises a first sidewall and a second sidewall opposite to the first sidewall, forming a mask layer completely covering the substrate and the gate structure, patterning the mask layer to form an opening in the mask layer to expose the first sidewall of the gate structure, performing an oxidation process to form a first insulating layer on the first sidewall, removing the mask layer, and forming a pair of spacer respectively on the first insulating layer and on the second sidewall.
  • FIG. 1 to FIG. 6 are schematic cross-sectional diagrams illustrating a method for forming a semiconductor device according to a first embodiment of the present invention
  • FIG. 7 to FIG. 10 are schematic cross-sectional diagrams illustrating a method for forming a semiconductor device according to a second embodiment of the present invention.
  • FIG. 1 to FIG. 6 are cross-sectional diagrams illustrating the steps for forming a semiconductor device according to a first embodiment of the present invention.
  • the cross-sectional structures of the semiconductor device shown in FIG. 1 to FIG. 6 are along the XY-plane defined by the X direction and the Y direction. X direction and Y direction are perpendicular.
  • a substrate 10 is provided.
  • the substrate 10 may be a semiconductor substrate, such as a silicon substrate, an epitaxial substrate, a silicon-germanium substrate, a silicon carbide substrate or silicon-on-insulator (SOI) substrate, but not limited thereto.
  • the substrate 10 may have a main surface 10 a which is perpendicular to the Y direction.
  • a well region 12 is formed in the substrate 10 under the main surface 10 a .
  • the well region 12 may be a doped region formed by performing an ion implantation process to implant conductive dopants into the substrate 10 .
  • the well region 12 may be a doped epitaxial layer of the substrate 10 .
  • the well region 12 may have a first conductivity type, and the substrate 10 may have a second conductivity type complementary to the first conductivity type.
  • first conductivity type is N-type and the second conductivity is P-type. It should be understood that, in other embodiments, the first conductivity type may be P-type and the second conductivity may be N-type.
  • a gate structure 20 is formed on the main surface 10 a of the substrate 10 .
  • a gate dielectric layer 18 is disposed between the gate structure 20 and the substrate 10 .
  • the opposite two sides of the gate structure 20 may respectively have a first sidewall 22 and a second sidewall 24 .
  • the first sidewall 22 is between the first top corner 22 a and the first bottom corner 22 b of the gate structure 20 .
  • the second sidewall 24 is between the second top corner 24 a and the second bottom corner 24 b of the gate structure 20 .
  • the gate structure 20 may have a top surface 26 between the first top corner 22 a and the second top corner 24 a and between the first sidewall 22 and the second sidewall 24 .
  • the gate structure 20 may comprise conductive material, such as poly silicon, but not limited thereto.
  • the gate dielectric layer 18 may comprise insulating material, such as silicon oxide, silicon nitride, high-k dielectric material, but not limited thereto.
  • the method for forming the gate structure 20 and the dielectric layer 18 may comprise depositing a gate dielectric material layer (such as silicon oxide, for example) on the substrate 10 and then depositing a gate material layer (such as poly silicon, for example) on the gate dielectric layer.
  • a patterning process such as a photolithography-etching process may be performed to remove the unnecessary portions of the gate material layer and the gate dielectric material layer, thereby patterning the gate material layer and the gate dielectric material layer into the gate structure 20 and the gate dielectric layer 18 .
  • a drift region 14 and a body region 16 may be formed in the well region 12 in the substrate 10 at two sides of the gate structure 20 and respectively adjacent to the first sidewall 22 and the second sidewall 24 of the gate structure 20 .
  • the drift region 14 and the body region 16 are spaced apart from each other by the well region 12 and are not in direct contact with each other.
  • the drift region 14 may have the same conductivity type as the well region 12 , such as N-type.
  • the body region 16 may have the opposite conductivity type to the drift region, such as P-type.
  • the boundary 140 between the drift region 14 and the well region 12 may near the first sidewall 22 of the gate structure 20 . For example, as shown in FIG.
  • the first sidewall 22 may be aligned with the boundary 140 along the Y direction. In other examples, the first sidewall 22 may shift a distance from the boundary 140 along the X direction and therefore may be vertically disposed on the drift region 14 or the well region 12 near the boundary 140 .
  • the gate structure 20 may stride over the boundary 160 between the body region 16 and the well region 12 .
  • the gate structure 20 may vertically overlap a portion of the body region 16 .
  • a mask layer 30 may be formed on the substrate 10 in a blanket manner.
  • the mask layer 30 may conformally cover along the main surface 10 a of the substrate 10 and the first sidewall 22 , the second sidewall 24 and the top surface 26 of the gate structure 20 .
  • the mask layer 30 may be a silicon nitride layer.
  • the mask layer 30 may be formed by plasma enhanced chemical vapor deposition (PECVD) process or sub-atmospheric chemical vapor deposition (SACVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • SACVD sub-atmospheric chemical vapor deposition
  • the thickness T 2 of the mask layer 30 may be approximately 25% of the thickness T 1 of the gate structure 20 .
  • the thickness T 2 of the mask layer 30 may be approximately 200 ⁇ .
  • the thickness T 2 of the mask layer 30 should be well controlled because that over-thick mask layer 30 may cause problems to a subsequent patterning of the mask layer 30 .
  • the mask layer 30 having insufficiently thickness may not be able to protect the underlying regions from being oxidized during a subsequent oxidation process P 1 as shown in FIG. 4 .
  • a patterning process such as a photolithography-etching process may be performed to remove a portion of the mask layer 30 , thereby forming the patterned mask layer 30 having an opening 32 to expose the first sidewall 22 , the first top corner 22 a and a portion of the top surface 26 of the gate structure 20 .
  • the other regions of the gate structure 20 and the substrate 10 are still covered by the patterned mask layer 30 and are not exposed.
  • an oxidation process P 1 is performed to oxidize the exposed first top corner 22 a and first sidewall 22 of the gate structure 20 through the opening 32 , thereby forming a first insulating layer 40 on the gate dielectric layer 18 and covering the first sidewall 23 of the remaining gate structure 20 .
  • a portion of the gate structure 20 is oxidized into the first insulating layer during the oxidation process P 1 .
  • the oxidation process P 1 may be a dry oxidation process using oxygen gas and nitrogen gas.
  • the oxidation process P 1 may be a wet oxidation process such as ISSG using oxygen gas, hydrogen gas and nitrogen gas.
  • the gate structure 20 may comprise poly silicon, and the first insulating layer 40 may comprise silicon oxide.
  • the gases such as oxygen used during the oxidation process P 1 may diffuse faster along the interface between the gate structure 20 and the gate dielectric layer 18 . Accordingly, the gate structure 20 near the gate dielectric layer 18 may have a higher oxidation rate and the first insulating layer 40 may have a first bird's beak portion 40 b near the gate dielectric layer 18 and covering a rounded bottom corner 23 b of the remaining gate structure 20 .
  • the gases such as oxygen used during the oxidation process P 1 may also diffuse faster along the interface of the top surface 26 of the gate structure 20 and the patterned mask layer 30 , and therefore a second bird's beak portion 40 a may be formed near the top surface 26 and covering a rounded top corner 23 a of the remaining gate structure 20 .
  • the gases such as oxygen, hydrogen or nitrogen used in the oxidation process P 1 may diffuse into the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40 . Accordingly, the composition of the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40 and the composition of the second portion 18 b of the gate dielectric layer 18 under the remaining gate structure 20 may be different.
  • the first portion 18 a may have oxygen, hydrogen or nitrogen in a concentration higher than that of the second portion 18 b of the gate dielectric layer 18 .
  • a boundary between the first portion 18 a and the second portion 18 b of the gate dielectric layer 18 may be vertically aligned with the first bird's beak portion 40 b of the first insulating layer 40 in the Y direction.
  • the thickness (such as the thickness measures along the X direction) of the first insulating layer 40 may be controlled by controlling the width of the opening 32 and the processing time of the oxidation process P 1 .
  • the mask layer 30 is removed.
  • the top surface 26 and the second sidewall 24 of the remaining gate structure 20 and the top surface 10 a of the substrate are exposed.
  • a pair of spacers 50 a and 50 b are then formed respectively on the first insulating layer 40 and the second sidewall 24 of that remaining gate structure 20 .
  • the spacers 50 a and 50 b may be formed by self-aligned process. For example, after removing the mask layer 30 , a spacer material layer (not shown) may be formed on the substrate 10 , and an anisotropic etching process (such as dry etching process) may be performed to remove unnecessary portion of the spacer material layer not on the two sides of the gate structure 20 .
  • the remaining spacer material layer on the two sides of the gate structure 20 becomes the spacers 50 a and 50 b .
  • the second sidewall 24 is in direct contact with the spacer 50 b
  • the first sidewall 23 is spaced apart from the spacer 50 a by the first insulating layer 40 .
  • the spacers 50 a and 50 b may have a single-layered structure or a multi-layered structure.
  • the person skilled in the art should understand that the single-layered or multi-layered spacers 50 a and 50 b bay be formed by depositing a single layered or multi-layered spacer material layer and performing one or more anisotropic etching processes.
  • one or more implantation processes may be performed, using the gate structure 20 and the first insulating layer 40 as the implanting mask to implant dopants into the substrate 10 to form lightly doped regions (not shown) at two sides of the gate structure 20 .
  • a source/drain implantation process may be performed, using the gate structure 20 , the first insulating layer 40 and the spacers 50 a and 50 b as the implanting mask to implant dopants into the substrate 10 at two sides of the gate structure 20 , thereby forming a drain region 52 and a source region 54 self-aligned to the outer edges of the spacers 50 a and 50 b .
  • An interlayer dielectric layer 60 is then formed on the substrate 10 in a blanket manner and covers the gate structure 20 and the substrate 10 .
  • a plurality of contact plugs 62 are then formed in the interlayer dielectric layer 60 and respectively electrically connect to the gate structure 20 , the drain region 52 and the source region 54 , and the semiconductor device 100 according to the first embodiment of the present invention is therefore obtained.
  • both of the drain region 52 and the source region 54 have the first conductivity type, such as N-type.
  • the drain region 52 is completely within the drift region 14 and spaced apart from the rounded bottom corner 23 b of the gate structure 20 by the spacer 50 a , the first portion 18 a of the gate dielectric layer 18 and the first insulating layer 40 .
  • the source region 54 is completely within the body region 16 and spaced apart from the second bottom corner 24 b by the spacer 50 b and the second portion 18 b of the gate dielectric layer 18 .
  • the semiconductor device 100 has a channel region L in the body region 16 directly under the gate structure 20 and near the main surface 10 a of the substrate 10 .
  • the channel region L is between the source region 54 and the boundary 160 .
  • the length of the channel region L may be influenced by the overlapping width of the gate structure 20 and the body region 16 and the source region 52 (or the lightly doped region, not shown) to the second sidewall 24 of the gate structure 20 .
  • the drift region 14 and the well region 12 under the gate structure 20 may reduce the high voltage applied to the drain region 52 to a lower voltage level applied to the channel region L and the breakdown between the drain region 52 and the source region 54 may be eliminated.
  • the first insulating layer 40 is formed intervening between the remaining gate structure 20 and the drain region 52 .
  • the conductive portion (such as poly silicon) of the gate structure 20 may be farther distanced from the drain region 52 .
  • the electrically isolation between the gate structure 20 and the drain region 52 may be improved without causing unexpected influences to the source region 54 , the length of the channel region L and other semiconductor devices integrally formed with the semiconductor device 100 on the substrate 10 .
  • the remaining gate structure 20 between the spacers 50 a and 50 b may have an asymmetric cross-section, as shown in FIG. 6 .
  • the top corner 23 a and bottom corner 23 b adjacent to the drain region 52 may have a more rounded profile with respect to the first top corner 24 a and the second bottom corner 24 b adjacent to the source region 52 . More important, the bottom corner 23 b of the gate structure 20 adjacent to the drain region 52 is beneficial for reducing the strength of the electrical field. Additionally, the oxidation process P 1 may be able to repair the defects in the first portion 18 a of the gate dielectric layer 18 formed in previous process steps such as the etching process to pattern the gate dielectric layer 18 . The quality of the first portion 18 a of the gate dielectric layer 18 is therefore improved.
  • FIG. 7 to FIG. 10 are cross-sectional diagrams illustrating the steps for forming a semiconductor device according to a second embodiment of the present invention.
  • the difference between the first embodiment and the second embodiment is that, as shown in FIG. 7 , the opening 34 of the patterned mask layer 30 exposes the first sidewall 22 , the first top corner 22 a and a portion of the top surface 26 of the gate structure 20 and a portion of the main surface 10 a adjacent to the first sidewall 22 of the gate structure 20 .
  • the other regions of the gate structure 20 and the substrate 10 may be covered by the patterned mask layer 30 .
  • an oxidation process P 1 is performed to oxidize the exposed regions of the gate structure 20 and the substrate 10 from the opening 34 , thereby forming a first insulating layer 40 on the first sidewall 23 of the remaining gate structure 20 and a second insulating layer 42 in the substrate 10 adjacent to the first sidewall 23 .
  • the substrate 10 may comprise silicon and the second insulating layer 42 may comprise silicon oxide.
  • a bottom surface 42 b of the second insulating layer 42 is lower than the main surface 10 a of the substrate 10 .
  • the first insulating layer 40 and the second insulating layer 42 may have a same thickness.
  • the second insulating layer 42 may have a third bird's beak portion 42 a adjacent to the main surface 10 a of the substrate 10 .
  • the third bird's beak portion 42 a may extending along the main surface 10 a of the substrate 10 and covering a rounded top corner 10 b of the substrate 10 .
  • the gases used in the oxidation process P 1 may diffuse into a first portion 18 a of the gate dielectric layer 18 directly under the first insulating layer 40 . Accordingly, the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40 and the second portion 18 b of the gate dielectric layer 18 under the remaining gate structure 20 may have different compositions.
  • the first portion 18 a may have a higher oxygen concentration than the second portion 18 b .
  • the first insulating layer 40 , the first portion 18 a of the gate dielectric layer 18 and the second insulating layer 42 collectively form an L-shaped insulating layer.
  • the thickness of the first insulating layer 40 and the thickness of the second insulating layer 42 may be controlled by the width of the opening 32 and the processing time of the oxidation process P 1 .
  • the mask layer 30 is removed and the top surface 26 and second sidewall 24 of the gate structure 20 and the main surface 10 a of the substrate 10 are exposed.
  • a pair of spacers 50 a and 50 b are then formed respectively on the L-shaped insulating layer and the second sidewall 24 at two sides of the gate structure 20 .
  • the second insulating layer 42 may have a length (laterally extending along the X direction) larger than the width of the spacer 50 a .
  • the bottom of the spacer 50 a may be completely overlapped by the second insulating layer 42 and a portion of the top surface 42 c of the second insulating layer 42 may be exposed from the spacer 50 a.
  • an source/drain implantation process may be performed, using the gate structure 20 , the first insulating layer 40 and the spacers 50 a and 50 b as the implanting mask to implant dopants into the substrate 10 at two sides of the gate structure 20 , thereby forming a drain region 52 and a source region 54 near the outer edges of the spacers 50 a and 50 b .
  • An interlayer dielectric layer 60 is then deposited on the substrate 10 in a blanket manner and covers the gate structure 20 and the substrate 10 .
  • a plurality of contact plugs 62 are then formed in the interlayer dielectric layer 60 and respectively electrically connect to the gate structure 20 , the drain region 52 and the source region 54 , and the semiconductor device 100 according to the second embodiment of the present invention is therefore obtained.
  • the second insulating layer 42 formed in the substrate 10 may prevent some of the dopants in the source/drain implantation process from being implanted into the substrate 10 . Accordingly, the portion 53 of the drain region 52 under the second insulating layer 42 may have dopants in a lower concentration. In this way, the strength of the electric field in the portion 53 of the drain region 52 may be reduced.
  • the first sidewall of the gate structure adjacent to the drain region is selectively oxidized to form a first insulating layer.
  • the conductive portion of the remaining gate structure may be farther distanced from the drain region and the bottom corner of the remaining gate structure may be rounded. Accordingly, the breakdown voltage between the gate structure and the drain region may be improved.
  • a portion of the substrate adjacent to the first sidewall is also oxidized to form a second insulating layer.
  • the second insulating layer may reduce the amount of the dopants being implanted into the substrate during the source/drain implantation process. Accordingly, a portion of the drain region underneath the second insulating layer may have dopants in a lower concentration and the breakdown voltage between the gate structure and the drain region may be further improved.

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Abstract

A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention generally relates to a semiconductor device and method for forming the same. More particularly, the present invention relates to a semiconductor device having asymmetric gate structure and method for forming the same.
2. Description of the Prior Art
Power devices are semiconductor devices used in high voltage application. Double-diffused metal-oxide-semiconductor (DMOS) devices have drawn much attention recently. Conventional DMOS devices are categorized into vertical double-diffused MOS (VDMOS) devices and lateral double-diffused MOS (LDMOS) devices. Having advantages of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other semiconductor devices in integrated circuits due to the planar structures, LDMOS devices are prevalently used in high operation voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier.
A key parameter for power device is the breakdown voltage, which usually refers to the highest voltage the device may sustain during operation. To achieve the breakdown voltage requirement, the drift region in a conventional LDMOS usually requires a certain area of the substrate and has cause hindrance for device minimization. Therefore, there is still a need in the field to provide a semiconductor device which may facilitate device minimization and also provide better voltage endurance.
SUMMARY OF THE INVENTION
One objective of the present invention is to provide a semiconductor device having higher break-down voltage by performing a selective oxidation process to form an insulating layer on a sidewall of the gate structure adjacent to the drain region and rounding a bottom corner of the gate structure.
To achieve the objective described above, the present invention provides a semiconductor device including a substrate, a gate structure disposed on the substrate and comprising a first sidewall and a second sidewall opposite to the first sidewall, a gate dielectric layer disposed between the gate structure and the substrate, a first insulating layer disposed on the gate dielectric layer and covering the first sidewall of the gate structure, and a pair of spacers respectively disposed on the first insulating layer and on the second sidewall of the gate structure. The first insulating layer comprises a first bird's beak portion covering a rounded bottom corner of the gate structure.
To achieve the objective described above, the present invention provides a method for forming a semiconductor device including providing a substrate, forming a gate structure on the substrate, wherein the gate structure comprises a first sidewall and a second sidewall opposite to the first sidewall, forming a mask layer completely covering the substrate and the gate structure, patterning the mask layer to form an opening in the mask layer to expose the first sidewall of the gate structure, performing an oxidation process to form a first insulating layer on the first sidewall, removing the mask layer, and forming a pair of spacer respectively on the first insulating layer and on the second sidewall.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 to FIG. 6 are schematic cross-sectional diagrams illustrating a method for forming a semiconductor device according to a first embodiment of the present invention
FIG. 7 to FIG. 10 are schematic cross-sectional diagrams illustrating a method for forming a semiconductor device according to a second embodiment of the present invention.
 DETAILED DESCRIPTION
To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.
Please refer to FIG. 1 to FIG. 6, which are cross-sectional diagrams illustrating the steps for forming a semiconductor device according to a first embodiment of the present invention. The cross-sectional structures of the semiconductor device shown in FIG. 1 to FIG. 6 are along the XY-plane defined by the X direction and the Y direction. X direction and Y direction are perpendicular.
As shown in FIG. 1, a substrate 10 is provided. The substrate 10 may be a semiconductor substrate, such as a silicon substrate, an epitaxial substrate, a silicon-germanium substrate, a silicon carbide substrate or silicon-on-insulator (SOI) substrate, but not limited thereto. The substrate 10 may have a main surface 10 a which is perpendicular to the Y direction. A well region 12 is formed in the substrate 10 under the main surface 10 a. In some embodiments, the well region 12 may be a doped region formed by performing an ion implantation process to implant conductive dopants into the substrate 10. In other embodiment, the well region 12 may be a doped epitaxial layer of the substrate 10. The well region 12 may have a first conductivity type, and the substrate 10 may have a second conductivity type complementary to the first conductivity type. For example, first conductivity type is N-type and the second conductivity is P-type. It should be understood that, in other embodiments, the first conductivity type may be P-type and the second conductivity may be N-type.
Please still refer to FIG. 1. A gate structure 20 is formed on the main surface 10 a of the substrate 10. A gate dielectric layer 18 is disposed between the gate structure 20 and the substrate 10. Along the X direction, the opposite two sides of the gate structure 20 may respectively have a first sidewall 22 and a second sidewall 24. The first sidewall 22 is between the first top corner 22 a and the first bottom corner 22 b of the gate structure 20. The second sidewall 24 is between the second top corner 24 a and the second bottom corner 24 b of the gate structure 20. The gate structure 20 may have a top surface 26 between the first top corner 22 a and the second top corner 24 a and between the first sidewall 22 and the second sidewall 24. According to some embodiments, the gate structure 20 may comprise conductive material, such as poly silicon, but not limited thereto. The gate dielectric layer 18 may comprise insulating material, such as silicon oxide, silicon nitride, high-k dielectric material, but not limited thereto. The method for forming the gate structure 20 and the dielectric layer 18 may comprise depositing a gate dielectric material layer (such as silicon oxide, for example) on the substrate 10 and then depositing a gate material layer (such as poly silicon, for example) on the gate dielectric layer. After that, a patterning process such as a photolithography-etching process may be performed to remove the unnecessary portions of the gate material layer and the gate dielectric material layer, thereby patterning the gate material layer and the gate dielectric material layer into the gate structure 20 and the gate dielectric layer 18.
Please still refer to FIG. 1. A drift region 14 and a body region 16 may be formed in the well region 12 in the substrate 10 at two sides of the gate structure 20 and respectively adjacent to the first sidewall 22 and the second sidewall 24 of the gate structure 20. The drift region 14 and the body region 16 are spaced apart from each other by the well region 12 and are not in direct contact with each other. The drift region 14 may have the same conductivity type as the well region 12, such as N-type. The body region 16 may have the opposite conductivity type to the drift region, such as P-type. The boundary 140 between the drift region 14 and the well region 12 may near the first sidewall 22 of the gate structure 20. For example, as shown in FIG. 1, the first sidewall 22 may be aligned with the boundary 140 along the Y direction. In other examples, the first sidewall 22 may shift a distance from the boundary 140 along the X direction and therefore may be vertically disposed on the drift region 14 or the well region 12 near the boundary 140. The gate structure 20 may stride over the boundary 160 between the body region 16 and the well region 12. The gate structure 20 may vertically overlap a portion of the body region 16.
Please refer to FIG. 2. Subsequently, a mask layer 30 may be formed on the substrate 10 in a blanket manner. The mask layer 30 may conformally cover along the main surface 10 a of the substrate 10 and the first sidewall 22, the second sidewall 24 and the top surface 26 of the gate structure 20. In some embodiments, the mask layer 30 may be a silicon nitride layer. The mask layer 30 may be formed by plasma enhanced chemical vapor deposition (PECVD) process or sub-atmospheric chemical vapor deposition (SACVD) process. According to an embodiment, the thickness T2 of the mask layer 30 may be approximately 25% of the thickness T1 of the gate structure 20. For example, when the thickness T1 of the gate structure 20 is approximately 800 angstroms (Å), the thickness T2 of the mask layer 30 may be approximately 200 Å. The thickness T2 of the mask layer 30 should be well controlled because that over-thick mask layer 30 may cause problems to a subsequent patterning of the mask layer 30. On the contrary, the mask layer 30 having insufficiently thickness may not be able to protect the underlying regions from being oxidized during a subsequent oxidation process P1 as shown in FIG. 4.
Please refer to FIG. 3. Afterward, a patterning process such as a photolithography-etching process may be performed to remove a portion of the mask layer 30, thereby forming the patterned mask layer 30 having an opening 32 to expose the first sidewall 22, the first top corner 22 a and a portion of the top surface 26 of the gate structure 20. The other regions of the gate structure 20 and the substrate 10 are still covered by the patterned mask layer 30 and are not exposed.
Please refer to FIG. 4. Following, an oxidation process P1 is performed to oxidize the exposed first top corner 22 a and first sidewall 22 of the gate structure 20 through the opening 32, thereby forming a first insulating layer 40 on the gate dielectric layer 18 and covering the first sidewall 23 of the remaining gate structure 20. In other words, a portion of the gate structure 20 is oxidized into the first insulating layer during the oxidation process P1. In some embodiments, the oxidation process P1 may be a dry oxidation process using oxygen gas and nitrogen gas. In other embodiments, the oxidation process P1 may be a wet oxidation process such as ISSG using oxygen gas, hydrogen gas and nitrogen gas. In some embodiments, the gate structure 20 may comprise poly silicon, and the first insulating layer 40 may comprise silicon oxide. In some embodiments, the gases such as oxygen used during the oxidation process P1 may diffuse faster along the interface between the gate structure 20 and the gate dielectric layer 18. Accordingly, the gate structure 20 near the gate dielectric layer 18 may have a higher oxidation rate and the first insulating layer 40 may have a first bird's beak portion 40 b near the gate dielectric layer 18 and covering a rounded bottom corner 23 b of the remaining gate structure 20. Similarly, in some embodiments, the gases such as oxygen used during the oxidation process P1 may also diffuse faster along the interface of the top surface 26 of the gate structure 20 and the patterned mask layer 30, and therefore a second bird's beak portion 40 a may be formed near the top surface 26 and covering a rounded top corner 23 a of the remaining gate structure 20. In some embodiments, the gases such as oxygen, hydrogen or nitrogen used in the oxidation process P1 may diffuse into the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40. Accordingly, the composition of the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40 and the composition of the second portion 18 b of the gate dielectric layer 18 under the remaining gate structure 20 may be different. For example, the first portion 18 a may have oxygen, hydrogen or nitrogen in a concentration higher than that of the second portion 18 b of the gate dielectric layer 18. As shown in FIG. 4, a boundary between the first portion 18 a and the second portion 18 b of the gate dielectric layer 18 may be vertically aligned with the first bird's beak portion 40 b of the first insulating layer 40 in the Y direction. The thickness (such as the thickness measures along the X direction) of the first insulating layer 40 may be controlled by controlling the width of the opening 32 and the processing time of the oxidation process P1.
Please refer to FIG. 5. After the oxidation process P1, the mask layer 30 is removed. The top surface 26 and the second sidewall 24 of the remaining gate structure 20 and the top surface 10 a of the substrate are exposed. A pair of spacers 50 a and 50 b are then formed respectively on the first insulating layer 40 and the second sidewall 24 of that remaining gate structure 20. The spacers 50 a and 50 b may be formed by self-aligned process. For example, after removing the mask layer 30, a spacer material layer (not shown) may be formed on the substrate 10, and an anisotropic etching process (such as dry etching process) may be performed to remove unnecessary portion of the spacer material layer not on the two sides of the gate structure 20. The remaining spacer material layer on the two sides of the gate structure 20 becomes the spacers 50 a and 50 b. The second sidewall 24 is in direct contact with the spacer 50 b, the first sidewall 23 is spaced apart from the spacer 50 a by the first insulating layer 40. The spacers 50 a and 50 b may have a single-layered structure or a multi-layered structure. The person skilled in the art should understand that the single-layered or multi-layered spacers 50 a and 50 b bay be formed by depositing a single layered or multi-layered spacer material layer and performing one or more anisotropic etching processes. In some embodiments, after removing the mask layer 30 and before forming the spacers 50 a and 50 b, one or more implantation processes may be performed, using the gate structure 20 and the first insulating layer 40 as the implanting mask to implant dopants into the substrate 10 to form lightly doped regions (not shown) at two sides of the gate structure 20.
Please refer to FIG. 6. Subsequently, a source/drain implantation process may be performed, using the gate structure 20, the first insulating layer 40 and the spacers 50 a and 50 b as the implanting mask to implant dopants into the substrate 10 at two sides of the gate structure 20, thereby forming a drain region 52 and a source region 54 self-aligned to the outer edges of the spacers 50 a and 50 b. An interlayer dielectric layer 60 is then formed on the substrate 10 in a blanket manner and covers the gate structure 20 and the substrate 10. A plurality of contact plugs 62 are then formed in the interlayer dielectric layer 60 and respectively electrically connect to the gate structure 20, the drain region 52 and the source region 54, and the semiconductor device 100 according to the first embodiment of the present invention is therefore obtained. In the illustrated embodiment, both of the drain region 52 and the source region 54 have the first conductivity type, such as N-type. The drain region 52 is completely within the drift region 14 and spaced apart from the rounded bottom corner 23 b of the gate structure 20 by the spacer 50 a, the first portion 18 a of the gate dielectric layer 18 and the first insulating layer 40. The source region 54 is completely within the body region 16 and spaced apart from the second bottom corner 24 b by the spacer 50 b and the second portion 18 b of the gate dielectric layer 18. The semiconductor device 100 has a channel region L in the body region 16 directly under the gate structure 20 and near the main surface 10 a of the substrate 10. The channel region L is between the source region 54 and the boundary 160. The length of the channel region L may be influenced by the overlapping width of the gate structure 20 and the body region 16 and the source region 52 (or the lightly doped region, not shown) to the second sidewall 24 of the gate structure 20. The drift region 14 and the well region 12 under the gate structure 20 may reduce the high voltage applied to the drain region 52 to a lower voltage level applied to the channel region L and the breakdown between the drain region 52 and the source region 54 may be eliminated.
As shown in FIG. 6, by using the mask layer 30 and performing the oxidation process P1 to selectively oxidize the portion of the gate structure 20 near the drain region 52, the first insulating layer 40 is formed intervening between the remaining gate structure 20 and the drain region 52. The conductive portion (such as poly silicon) of the gate structure 20 may be farther distanced from the drain region 52. In this way, the electrically isolation between the gate structure 20 and the drain region 52 may be improved without causing unexpected influences to the source region 54, the length of the channel region L and other semiconductor devices integrally formed with the semiconductor device 100 on the substrate 10. Furthermore, the remaining gate structure 20 between the spacers 50 a and 50 b may have an asymmetric cross-section, as shown in FIG. 6. The top corner 23 a and bottom corner 23 b adjacent to the drain region 52 may have a more rounded profile with respect to the first top corner 24 a and the second bottom corner 24 b adjacent to the source region 52. More important, the bottom corner 23 b of the gate structure 20 adjacent to the drain region 52 is beneficial for reducing the strength of the electrical field. Additionally, the oxidation process P1 may be able to repair the defects in the first portion 18 a of the gate dielectric layer 18 formed in previous process steps such as the etching process to pattern the gate dielectric layer 18. The quality of the first portion 18 a of the gate dielectric layer 18 is therefore improved.
Other embodiments or variations directed to the semiconductor devices and the manufacturing methods will be described in the following paragraphs. To simplify the disclosure, the following description will be focus on and be directed to the different features between the embodiments rather than redundantly repeating similar components. In addition, like reference numerals will refer to like elements throughout the disclosure to facilitate the comparison between embodiments.
Please refer to FIG. 7 to FIG. 10, which are cross-sectional diagrams illustrating the steps for forming a semiconductor device according to a second embodiment of the present invention. The difference between the first embodiment and the second embodiment is that, as shown in FIG. 7, the opening 34 of the patterned mask layer 30 exposes the first sidewall 22, the first top corner 22 a and a portion of the top surface 26 of the gate structure 20 and a portion of the main surface 10 a adjacent to the first sidewall 22 of the gate structure 20. Similarly, the other regions of the gate structure 20 and the substrate 10 may be covered by the patterned mask layer 30.
Subsequently, as shown in FIG. 8, an oxidation process P1 is performed to oxidize the exposed regions of the gate structure 20 and the substrate 10 from the opening 34, thereby forming a first insulating layer 40 on the first sidewall 23 of the remaining gate structure 20 and a second insulating layer 42 in the substrate 10 adjacent to the first sidewall 23. In some embodiments, the substrate 10 may comprise silicon and the second insulating layer 42 may comprise silicon oxide. A bottom surface 42 b of the second insulating layer 42 is lower than the main surface 10 a of the substrate 10. In some embodiments, the first insulating layer 40 and the second insulating layer 42 may have a same thickness. In some embodiments, the second insulating layer 42 may have a third bird's beak portion 42 a adjacent to the main surface 10 a of the substrate 10. The third bird's beak portion 42 a may extending along the main surface 10 a of the substrate 10 and covering a rounded top corner 10 b of the substrate 10. As previously illustrated, the gases used in the oxidation process P1 may diffuse into a first portion 18 a of the gate dielectric layer 18 directly under the first insulating layer 40. Accordingly, the first portion 18 a of the gate dielectric layer 18 under the first insulating layer 40 and the second portion 18 b of the gate dielectric layer 18 under the remaining gate structure 20 may have different compositions. In some embodiments, the first portion 18 a may have a higher oxygen concentration than the second portion 18 b. As shown in FIG. 8, the first insulating layer 40, the first portion 18 a of the gate dielectric layer 18 and the second insulating layer 42 collectively form an L-shaped insulating layer. Similarly, the thickness of the first insulating layer 40 and the thickness of the second insulating layer 42 may be controlled by the width of the opening 32 and the processing time of the oxidation process P1.
Subsequently, as shown in FIG. 9, the mask layer 30 is removed and the top surface 26 and second sidewall 24 of the gate structure 20 and the main surface 10 a of the substrate 10 are exposed. A pair of spacers 50 a and 50 b are then formed respectively on the L-shaped insulating layer and the second sidewall 24 at two sides of the gate structure 20. In some embodiments, by controlling the width of the opening 34 shown in FIG. 8, the second insulating layer 42 may have a length (laterally extending along the X direction) larger than the width of the spacer 50 a. In this case, the bottom of the spacer 50 a may be completely overlapped by the second insulating layer 42 and a portion of the top surface 42 c of the second insulating layer 42 may be exposed from the spacer 50 a.
Subsequently, as shown in FIG. 10, an source/drain implantation process may be performed, using the gate structure 20, the first insulating layer 40 and the spacers 50 a and 50 b as the implanting mask to implant dopants into the substrate 10 at two sides of the gate structure 20, thereby forming a drain region 52 and a source region 54 near the outer edges of the spacers 50 a and 50 b. An interlayer dielectric layer 60 is then deposited on the substrate 10 in a blanket manner and covers the gate structure 20 and the substrate 10. A plurality of contact plugs 62 are then formed in the interlayer dielectric layer 60 and respectively electrically connect to the gate structure 20, the drain region 52 and the source region 54, and the semiconductor device 100 according to the second embodiment of the present invention is therefore obtained. It is noteworthy that, in the second embodiment, the second insulating layer 42 formed in the substrate 10 may prevent some of the dopants in the source/drain implantation process from being implanted into the substrate 10. Accordingly, the portion 53 of the drain region 52 under the second insulating layer 42 may have dopants in a lower concentration. In this way, the strength of the electric field in the portion 53 of the drain region 52 may be reduced.
In one embodiment of the present invention, the first sidewall of the gate structure adjacent to the drain region is selectively oxidized to form a first insulating layer. The conductive portion of the remaining gate structure may be farther distanced from the drain region and the bottom corner of the remaining gate structure may be rounded. Accordingly, the breakdown voltage between the gate structure and the drain region may be improved. In another embodiment of the present invention, a portion of the substrate adjacent to the first sidewall is also oxidized to form a second insulating layer. The second insulating layer may reduce the amount of the dopants being implanted into the substrate during the source/drain implantation process. Accordingly, a portion of the drain region underneath the second insulating layer may have dopants in a lower concentration and the breakdown voltage between the gate structure and the drain region may be further improved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (17)

What is claimed is:
1. A semiconductor device, comprising:
a substrate;
a gate structure disposed on the substrate and comprising a first sidewall and a second sidewall opposite to the first sidewall;
a gate dielectric layer disposed between the gate structure and the substrate;
a first insulating layer disposed on the gate dielectric layer and covering the first sidewall, wherein the first insulating layer comprises a first bird's beak portion covering a rounded bottom corner of the gate structure;
a pair of spacers respectively disposed on the first insulating layer and on the second sidewall, wherein the second sidewall is in direct contact with one of the spacer, and the first sidewall is spaced apart from the other one of the spacer by the first insulating layer;
a second insulating layer formed in the substrate and under the spacer on the first insulating layer; and
a drain region formed in the substrate and adjacent to the spacer on the first insulating layer, wherein a portion of the drain region is under the second insulating layer.
2. The semiconductor device according to claim 1, wherein the first insulating layer further comprises a second bird's beak portion disposed on a rounded top corner of the gate structure.
3. The semiconductor device according to claim 1, wherein the gate dielectric layer comprises a first portion vertically under the first insulating layer and a second portion vertically under the gate structure, wherein a boundary between the first portion and the second portion is vertically aligned with the first bird's beak portion.
4. The semiconductor device according to claim 3, wherein the first portion and the second portion of the gate dielectric layer comprise different compositions.
5. The semiconductor device according to claim 1, wherein a bottom surface of the second insulating layer is lower than a top surface of the substrate.
6. The semiconductor device according to claim 5, wherein the second insulating layer comprises a third bird's beak portion adjacent to the top surface of the substrate.
7. The semiconductor device according to claim 5, wherein a top surface of the second insulating layer is exposed from a bottom of the spacer.
8. The semiconductor device according to claim 1, further comprising:
a well region comprising a first conductivity type formed in the substrate;
a drift region comprising the first conductivity type formed in the well region and adjacent to the first sidewall of the gate structure, wherein the drain region is formed in the drift region;
a body region comprising a second conductivity type formed in the well region and adjacent to the second sidewall of the gate structure, wherein the gate structure stride over a boundary between the body region and the well region, wherein the first conductivity type and the second conductivity type are complementary; and
a source region formed in the body region and adjacent to the spacer on the second sidewall.
9. A method for forming a semiconductor device, comprising:
providing a substrate;
forming a gate structure on the substrate, wherein the gate structure comprises a first sidewall and a second sidewall opposite to the first sidewall;
forming a mask layer completely covering the substrate and the gate structure;
patterning the mask layer to form an opening in the mask layer to expose the first sidewall of the gate structure and a portion of the substrate adjacent to the first sidewall;
performing an oxidation process to form a first insulating layer on the first sidewall and a second insulating layer in the exposed portion of the substrate;
removing the mask layer;
forming a pair of spacer respectively on the first insulating layer and on the second sidewall; and
forming a drain region in the substrate and adjacent to the spacer on the first insulating layer, wherein a portion of the drain region is under the second insulating layer.
10. The method according to claim 9, wherein the oxidation process comprises oxidizing the first sidewall of the gate structure through the opening to form the first insulating layer.
11. The method according to claim 9, wherein the gate structure comprises poly silicon and the first insulating layer comprises silicon oxide.
12. The method according to claim 9, wherein the mask layer comprise silicon nitride.
13. The method according to claim 9, wherein the oxidation process comprises:
oxidizing the first sidewall of the gate structure through the opening to form the first insulating layer; and
oxidizing the exposed portion of the substrate through the opening to form the second insulating layer in the substrate.
14. The method according to claim 9, wherein the second insulating layer comprises a bottom surface lower than a top surface of the substrate.
15. The method according to claim 9, wherein a top surface of the second insulating layer is exposed form a bottom of the spacer on the first insulating layer.
16. The method according to claim 9, wherein the step for forming the gate structure comprises:
forming a well region comprising a first conductivity type in the substrate;
forming a drift region and a body region in the well region and spaced apart from each other by the well region, wherein the drift region comprises the first conductivity type, the body region comprises a second conductivity type complementary to the first conductivity type; and
forming the gate structure on the substrate and disposed on a boundary between the body region and the well region.
17. The method according to claim 16, further comprising the following step after forming the pair of spacers:
performing an implantation process, using the spacers as a mask to form the drain region and a source region in the substrate and self-aligned to the spacers, wherein the drain region is formed in the drift region and the source region is formed in the body region, wherein the drain region and the source region comprise the first conductivity type.
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