US10950536B2 - Packed interconnect structure with reduced cross coupled noise - Google Patents
Packed interconnect structure with reduced cross coupled noise Download PDFInfo
- Publication number
- US10950536B2 US10950536B2 US16/017,710 US201816017710A US10950536B2 US 10950536 B2 US10950536 B2 US 10950536B2 US 201816017710 A US201816017710 A US 201816017710A US 10950536 B2 US10950536 B2 US 10950536B2
- Authority
- US
- United States
- Prior art keywords
- interconnects
- angled
- signal interconnects
- electro
- computer system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/51—Fixed connections for rigid printed circuits or like structures
- H01R12/52—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/51—Fixed connections for rigid printed circuits or like structures
- H01R12/55—Fixed connections for rigid printed circuits or like structures characterised by the terminals
- H01R12/57—Fixed connections for rigid printed circuits or like structures characterised by the terminals surface mounting terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
- H01R12/714—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit with contacts abutting directly the printed circuit; Button contacts therefore provided on the printed circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
- H01R13/6467—Means for preventing cross-talk by cross-over of signal conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/16—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for manufacturing contact members, e.g. by punching and by bending
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/20—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for assembling or disassembling contact members with insulating base, case or sleeve
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/7005—Guiding, mounting, polarizing or locking means; Extractors
- H01R12/7011—Locking or fixing a connector to a PCB
- H01R12/707—Soldering or welding
Definitions
- the field of invention pertains generally to electrical engineering. More specifically, the field of invention pertains to a packed interconnect structure with reduced cross coupled nose.
- FIG. 1 shows a interconnect
- FIG. 2 shows a prior art packed interconnect structure
- FIG. 3 shows an improved interconnect pair
- FIG. 4 shows an improved three dimensional multiple interconnect structure
- FIG. 5 shows an improved packed interconnect structure
- FIG. 6 shows a packaged packed interconnect structure
- FIGS. 7 a , 7 b and 7 c shows a method of making an improved packed interconnect structure
- FIG. 8 shows another improved interconnect pair
- FIGS. 9 a and 9 b show other improved packed interconnect structures
- FIG. 10 shows a computing system
- the electrical current carried by one interconnect may flow through the magnetic field created by another interconnect (such as an adjacent interconnect).
- another interconnect such as an adjacent interconnect.
- noise the presence of a time varying magnetic field in the pathway of the electrical signal is reproduced as noise in the electrical signal.
- the total energy of such noise limits the performance of the electrical signal. That is, with increasing noise energy, the amplitude of the signal must be increased and/or the highest frequencies of the signal must be reduced.
- FIG. 3 depicts a wiring solution that puts distance between neighboring interconnects 301 , 302 so as to dramatically reduce the induced noise between them.
- the depiction of FIG. 3 can be viewed as a cross section in which the interconnects 301 , 302 run vertically upward along a z axis, e.g., from a substrate 300 located at the bottoms of the interconnects that lies in the xy plane.
- the interconnects 301 , 302 are purposely formed so that they are separated by a distance over much of their run length, where, as described immediately below, is wide enough to significantly reduce magnetic field coupling (and therefore noise) between them.
- both of the interconnects 301 , 302 can be viewed as having respective input ends 307 , 308 and respective output ends 309 , 310 , where, e.g., the input and output ends of a same interconnect are aligned with one another along a respective vertical axis 311 , 312 .
- the interconnects may be separated by a minimal distance such as, e.g., the minimal pitch of the wiring's manufacturing technology.
- the interconnects Traversing the interconnects from their respective input ends 307 / 308 , the interconnects deviate away from one another along first respective legs 303 , 304 so as to put distance between them. Notably, in the case where the legs deviate at 90° with respect to one another, neither leg 303 , 304 induces noise in the other leg.
- the radial magnetic field from both legs 303 , 304 will emanate perpendicular to their respective current flows (which follow the path of the respective legs 303 , 304 ).
- the perpendicular orientation of the magnetic field from one leg does not cross into the current path of the other leg. As such, the other leg observes minimal noise from the leg.
- the respective legs 303 , 304 then terminate at respective elbows 313 , 314 .
- second respective legs 305 , 306 converge toward one another until they reach their respective output ends 309 , 310 .
- the perpendicular orientation of the magnetic fields induced from one of the second legs theoretically crosses the current flow of its oppositely located first leg (the magnetic field from second leg 305 theoretically crosses through the current flow of first leg 304 and the magnetic field from second leg 306 theoretically crosses through the current flow first leg 303 ).
- the magnetic field induced from a first leg theoretically cross the current flow of its oppositely located second leg (the magnetic field from first leg 304 theoretically crosses through the current flow of second leg 305 and the magnetic field from first leg 303 theoretically crosses through the current flow second leg 306 ).
- oppositely located leg pairs 304 / 305 and 303 / 306 are cross-coupled and can induce noise into one another.
- both opposite leg pairs 304 / 305 , 303 / 306 have enough distance between them such that the aforementioned 1/r 2 roll-off in magnetic flux intensity from one leg of a pair results in negligible coupled magnetic flux intensity and corresponding induced noise into the other leg of the pair.
- the overall structure results in minimal/negligible induced noise between the interconnects 301 , 301 over their entire respective run lengths.
- FIG. 4 shows a three dimensional embodiment 400 where the interconnects 401 , 402 , 403 are located on different y axis locations unlike FIG. 3 which suggests the interconnects 301 , 302 are located on a same y axis location. Nevertheless, the principles of reduced noise coupling between neighboring interconnects in the three dimensional structure 400 of FIG. 4 are essentially the same as those described above with respect to FIG. 3 . Additionally, the distance between non-neighboring interconnects (e.g., interconnect 401 and 403 ) in the three dimensional interconnect structure 400 of FIG. 4 is sufficient to keep induced noise negligible between non-neighboring interconnects (although additional shielding may help as described in more detail below).
- non-neighboring interconnects e.g., interconnect 401 and 403
- FIG. 4 also depicts for comparison purposes a three dimensional depiction of three interconnects in a traditional straight line arrangement 410 .
- the improved structure 400 has a spatial cost of 2 ⁇ X along the x axis which is comparable to the aforementioned distance 315 between elbows 313 , 314 in the wiring structure of FIG. 3 . That is, the improved structure 400 is approximately 2 ⁇ X wider than the traditional structure 410 .
- the outward expansion of the overall improved structure 400 results in a 2 ⁇ X space consumption “cost” as compared to the traditional structure 410 , the cost does not replicate/compound itself as more and more interconnects are added packed into the wiring structure.
- the structure 400 of FIG. 4 remains approximately only 2 ⁇ X wider than a structure that packs a same number of additional straight line interconnects into the traditional structure 410 .
- the improved structure 400 also includes reduced coupling path length as compared to the traditional structure 410 because of its alternately angled pins and therefore exhibits less cross talk noise.
- FIG. 5 depicts this property.
- the overall structure remains approximately only 2 ⁇ X wider than if the 5 ⁇ 6 array were packed with straight interconnects.
- the spatial cost approximately varies as 2 ⁇ X/N where N is the number of interconnects packed into the structure 500 .
- N is the number of interconnects packed into the structure 500 .
- interconnects that carry signals correspond to interconnects 501 while the remaining interconnects correspond to ground or power plane interconnects.
- ground and power plane interconnects act to terminate magnetic flux lines which has the effect of shielding a interconnect from a noise inducing interconnect where the shielding interconnect resides between the two.
- FIG. 6 shows a package structure 600 that keeps the packed interconnect structure 500 in place.
- the package structure 600 in made of electrically insulating material (e.g., plastic, ceramic, dielectric, etc.) and includes angled slots 601 in its base to keep the interconnects in the correct location given their angled lower legs (e.g., the angle of an angled slot equals the angle of deviation of its interconnect's lower leg). With a deep enough slot (e.g., equal to the length of the interconnects' lower leg), the package structure is able to keep a interconnect in its correct location.
- electrically insulating material e.g., plastic, ceramic, dielectric, etc.
- the interconnect may be epoxied to the sidewalls of the slot or simply press fit (push through hole) where, e.g., the interconnect diameter is approximately equal to the diameter of the slot opening (more generally, the size and shape of the interconnect cross section is approximately the same size and shape as the slot opening).
- each interconnect is “dimpled” so that, e.g., a solder ball or micro-ball or other spherical connection 602 can easily make an electrical connection to the interconnect.
- the packaged wiring structure can easily mate to a ball grid array.
- the bottoms of each of the interconnects may also be dimpled so that the packaged wiring structure can easily form an electrical and mechanical interface between two ball-grid arrays.
- the bottoms of the interconnects (and/or the tops of the interconnects) may be non-dimpled (flat) for easing mating with a pad grid array or land grid array.
- the interconnects may be further bent or otherwise formed into a J lead or other lead shape that adds some mechanical/spring-like resistance to being pressed so as to form a secure electron-mechanical connection.
- the packaged structure of FIG. 6 lends itself to various types of connections such as: a chip to chip connection, a packaged chip to packaged chip connection, a chip to packaged chip connection, a chip to PC board connection, a packaged chip to PC board connection, etc.
- an angled wiring approach is used to implement a high speed memory interface such as a double data rate (DDR) memory interface as specified by an industry standard such as a Joint Electron Device Engineering Council (JEDEC) industry standard.
- the signal interconnects may correspond to high speed signal interconnects such as DQ interconnects or control/address (CA) interconnects.
- the angled interconnects may form a connection between, e.g., stacked memory chips in a stacked memory chip structure, a logic chip and a stack of memory chips in a stacked memory chip solution, a memory chip and a dual in-line memory module (DIMM), a stacked memory chip solution package and a PC board (motherboard), a DIMM and a PC board, etc.
- DIMM dual in-line memory module
- the embodiments of FIGS. 4, 5 and 6 do not depict a 90° divergence angle between bottom leg pairs of neighboring interconnects and top leg pairs of neighboring interconnects. Rather, the divergence angle is closer to 60°. As such, there exists some magnetic flux coupling between bottom leg pairs of neighboring interconnects and top leg pairs of neighboring interconnects. Nevertheless, with maximum coupling existing when neighboring interconnects have 0° divergence angle (parallel), a 60° divergence angle is close enough to 90° such that any magnetic coupling between bottom leg pairs and top leg pairs is negligible. Likewise, any resulting induced noise between bottom leg pairs and top leg pairs is negligible. Moreover, such coupling is additionally shielded in the embodiments of FIGS. 5 and 6 by the presence of shielding interconnects between signal interconnects.
- FIGS. 7 a through 7 c depict one embodiment of manufacturing process for forming the packaged wiring structure of FIG. 6 .
- a bottom fixture 701 having angled slots is first presented.
- the bottom fixture 701 may be the base of the final packaged structure.
- straight interconnects (e.g., pins) 702 are then inserted in corresponding slots of the bottom fixture 701 which results in straight pins 702 that emerge from a top face of the bottom structure 701 at the angle of the bottom fixture's slots.
- the pins 703 are then bent, as observed in FIG. 7 c , by applying a force 703 to the pins 702 in unison in the direction the pins are to be bent.
- an upper structure (not shown) that is similar in structure to the bottom fixture 701 is placed only over the upper regions of the exposed pins so that the tops of the pins extend only a shallow distance into the upper structure's slots.
- the upper structure is then pushed or pulled in the direction that the pins are to be bent.
- the shallow insertion of the tops of the pins into the upper structure is not only enough to grab the tops of the pins but also applies maximum torque to the elbow/bending region of the pins. As such, the pins should easily bend in unison in the desired direction a same amount.
- FIGS. 7 a -7 c The process of FIGS. 7 a -7 c is suitable for forming a single row of angled interconnects in the packed interconnect structure of FIGS. 4, 5 and 6 .
- a next row (e.g., positioned deeper along the y axis of the packed structure) is formed by the same process of FIGS. 7 a through 7 c except that the interconnects are initially angled in the opposite direction of FIG. 7 b and then bent in the opposite direction of FIG. 7 c .
- the identical process of FIGS. 7 a through 7 c is performed except that the right and left ends of the finished structure of FIG. 7 c are swapped before placement into the final packaged structure.
- FIG. 8 shows another embodiment 800 that only includes bottom diverging legs.
- little or no magnetic flux coupling should exist between the diverging interconnect legs.
- one leg should induce little or no noise in the other leg.
- FIG. 9 a shows a three dimensional embodiment 900 of the approach of FIG. 8 .
- shielding pins (P) are dispersed to promote shielding and minimize cross-coupling between signal pins (S) where possible.
- some neighboring pins will exhibit cross-coupling approximately at their mid-sections.
- cross-coupling is largely limited to their mid-sections rather than their entire run lengths which, in turn, effectively minimizes the cross-coupling and resulting induced noise between them.
- singularly divergent interconnect approach may be more feasible in monolithic implementations in the metallurgical layers of a semiconductor chip, where, e.g., the angled slots are formed in the inter metal layer dielectric between metal layers with an anisotropic etch that etches one or more dielectric layers at the angle of divergence. Metal is then deposited in the angled opening to form the angled interconnects.
- FIG. 9 b shows another bottom angled approach in which the interconnects have bent leads to form a compressive/spring-like resistance with upper pads to form a secure electro-mechanical connection.
- This approach can be applied to the packaging via design.
- FIG. 10 provides an exemplary depiction of a computing system 1000 (e.g., a smartphone, a tablet computer, a laptop computer, a desktop computer, a server computer, etc.).
- the basic computing system 1000 may include a central processing unit 1001 (which may include, e.g., a plurality of general purpose processing cores 1015 _ 1 through 1015 _X) and a main memory controller 1017 disposed on a multi-core processor or applications processor, system memory 1002 , a display 1003 (e.g., touchscreen, flat-panel), a local interconnectd point-to-point link (e.g., USB) interface 1004 , various network I/O functions 1005 (such as an Ethernet interface and/or cellular modem subsystem), a interconnectless local area network (e.g., WiFi) interface 1006 , a interconnectless point-to-point link (e.g., Bluetooth) interface 1007 and a Global Positioning System interface 1008 , various sensors 100
- An applications processor or multi-core processor 1050 may include one or more general purpose processing cores 1015 within its CPU 1001 , one or more graphical processing units 1016 , a memory management function 1017 (e.g., a memory controller) and an I/O control function 1018 .
- the general purpose processing cores 1015 typically execute the operating system and application software of the computing system.
- the graphics processing unit 1016 typically executes graphics intensive functions to, e.g., generate graphics information that is presented on the display 1003 .
- the memory control function 1017 interfaces with the system memory 1002 to write/read data to/from system memory 1002 .
- the power management control unit 1012 generally controls the power consumption of the system 1000 .
- Each of the touchscreen display 1003 , the communication interfaces 1004 - 507 , the GPS interface 1008 , the sensors 1009 , the camera(s) 1010 , and the speaker/microphone codec 1013 , 1014 all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the one or more cameras 1010 ).
- I/O input and/or output
- various ones of these I/O components may be integrated on the applications processor/multi-core processor 1050 or may be located off the die or outside the package of the applications processor/multi-core processor 1050 .
- the computing system also includes non-volatile storage 1020 which may be the mass storage component of the system.
- Computing system may contain various embodiments of angled interconnect connections as described at length above.
- Embodiments of the invention may include various processes as set forth above.
- the processes may be embodied in machine-executable instructions.
- the instructions can be used to cause a general-purpose or special-purpose processor to perform certain processes.
- these processes may be performed by specific/custom hardware components that contain hard interconnectd logic circuitry or programmable logic circuitry (e.g., field programmable gate array (FPGA), programmable logic device (PLD)) for performing the processes, or by any combination of programmed computer components and custom hardware components.
- FPGA field programmable gate array
- PLD programmable logic device
- Elements of the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions.
- the machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASH memory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media or other type of media/machine-readable medium suitable for storing electronic instructions.
- the present invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).
- a remote computer e.g., a server
- a requesting computer e.g., a client
- a communication link e.g., a modem or network connection
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/017,710 US10950536B2 (en) | 2018-06-25 | 2018-06-25 | Packed interconnect structure with reduced cross coupled noise |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/017,710 US10950536B2 (en) | 2018-06-25 | 2018-06-25 | Packed interconnect structure with reduced cross coupled noise |
Publications (2)
Publication Number | Publication Date |
---|---|
US20190043796A1 US20190043796A1 (en) | 2019-02-07 |
US10950536B2 true US10950536B2 (en) | 2021-03-16 |
Family
ID=65229857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/017,710 Active US10950536B2 (en) | 2018-06-25 | 2018-06-25 | Packed interconnect structure with reduced cross coupled noise |
Country Status (1)
Country | Link |
---|---|
US (1) | US10950536B2 (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6594152B2 (en) * | 1999-09-30 | 2003-07-15 | Intel Corporation | Board-to-board electrical coupling with conductive band |
US7255573B2 (en) * | 2005-12-30 | 2007-08-14 | Intel Corporation | Data signal interconnection with reduced crosstalk |
US20090279274A1 (en) * | 2004-12-31 | 2009-11-12 | Martin Joseph Agnew | Circuit boards |
US8587357B2 (en) * | 2011-08-25 | 2013-11-19 | International Business Machines Corporation | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting |
US20140374875A1 (en) * | 2010-06-01 | 2014-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Inductor and Transformer |
US9531130B1 (en) * | 2016-01-12 | 2016-12-27 | Tyco Electronics Corporation | Electrical connector having resonance control |
-
2018
- 2018-06-25 US US16/017,710 patent/US10950536B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6594152B2 (en) * | 1999-09-30 | 2003-07-15 | Intel Corporation | Board-to-board electrical coupling with conductive band |
US20090279274A1 (en) * | 2004-12-31 | 2009-11-12 | Martin Joseph Agnew | Circuit boards |
US7255573B2 (en) * | 2005-12-30 | 2007-08-14 | Intel Corporation | Data signal interconnection with reduced crosstalk |
US20140374875A1 (en) * | 2010-06-01 | 2014-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Inductor and Transformer |
US8587357B2 (en) * | 2011-08-25 | 2013-11-19 | International Business Machines Corporation | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting |
US9531130B1 (en) * | 2016-01-12 | 2016-12-27 | Tyco Electronics Corporation | Electrical connector having resonance control |
Non-Patent Citations (1)
Title |
---|
Tech Web, published in Apr. 19, 2018. * |
Also Published As
Publication number | Publication date |
---|---|
US20190043796A1 (en) | 2019-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11929339B2 (en) | Innovative interconnect design for package architecture to improve latency | |
TWI518912B (en) | Systems and methods for high-speed, low-profile memory packages and pinout designs | |
JP5164273B2 (en) | Multi-die integrated circuit device | |
TWI785544B (en) | Apparatus included in a die, method of forming an integrated circuit die including backside or underside metallization and system comprising a package substrate | |
US20140264915A1 (en) | Stacked Integrated Circuit System | |
US9691437B2 (en) | Compact microelectronic assembly having reduced spacing between controller and memory packages | |
JP2018511165A (en) | A substrate comprising a stack of interconnects, an interconnect on a solder resist layer, and an interconnect on a side portion of the substrate | |
TW201618238A (en) | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design | |
TWI520279B (en) | Unified pcb design for ssd applications, various density configurations, and direct nand access | |
CN110024121A (en) | Super chip | |
US9542978B2 (en) | Semiconductor package with terminals adjacent sides and corners | |
US10109570B2 (en) | Radial solder ball pattern for attaching semiconductor and micromechanical chips | |
US11068640B2 (en) | Power shared cell architecture | |
US10950536B2 (en) | Packed interconnect structure with reduced cross coupled noise | |
KR20180011433A (en) | Memory device including interposer and system in package including the same | |
TW201810581A (en) | Bridge die design for high bandwidth memory interface | |
CN103871980A (en) | Semiconductor package and method for routing the package | |
US11646271B2 (en) | Apparatuses including conductive structure layouts | |
US9337146B1 (en) | Three-dimensional integrated circuit stack | |
CN114121873A (en) | Apparatus and system having ball grid array and related microelectronic device and device package | |
US11682664B2 (en) | Standard cell architecture with power tracks completely inside a cell | |
US8399965B2 (en) | Layer structure with EMI shielding effect | |
US20240203736A1 (en) | Reusable templates for semiconductor design and fabrication | |
Hu et al. | Methods to Reduce the Hierarchy of Interconnections in Electronic System | |
JP2024041688A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHOU, ZHEN;LIAO, JUN;LI, XIANG;AND OTHERS;SIGNING DATES FROM 20180919 TO 20190715;REEL/FRAME:049791/0310 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |