US10269750B2 - Methods and apparatus of packaging semiconductor devices - Google Patents

Methods and apparatus of packaging semiconductor devices Download PDF

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Publication number
US10269750B2
US10269750B2 US15/601,801 US201715601801A US10269750B2 US 10269750 B2 US10269750 B2 US 10269750B2 US 201715601801 A US201715601801 A US 201715601801A US 10269750 B2 US10269750 B2 US 10269750B2
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layer
passivation layer
underbump metallization
opening
substrate
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US20170256512A1 (en
Inventor
Chia-Wei Tu
Yian-Liang Kuo
Tsung-Fu Tsai
Ru-Ying Huang
Ming-Song Sheu
Hsien-Wei Chen
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Definitions

  • Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples.
  • the semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
  • WLP wafer level packaging
  • RDL redistribution layer
  • WLP packages have been applied more and more in integrated circuit packaging due to the advantages of cost and simple structure.
  • stress has been found to be directly applied on passivation (PSV) and extreme low-k (ELK) layers, causing ELK/PSV crack/delamination by severe fatigue loading during reliability testing.
  • PSV passivation
  • ELK extreme low-k
  • FIGS. 1( a )-1( f ) illustrate an embodiment of a WLP process, shown in cross-sectional view or in top view;
  • FIGS. 2( a )-2( c ) illustrate embodiments of detailed cross-sectional views of WLP semiconductor devices
  • FIGS. 3( a )-3( c ) illustrate top views of the connections between a conducting solder ball/bump to a contact pad within a WLP package.
  • a semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon.
  • the active side surface contains a plurality of semiconductor die.
  • the active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment.
  • semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering.
  • Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures.
  • the doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
  • FIGS. 1( a )-1( f ) illustrate an embodiment of a WLP process, shown in cross-sectional view or in top view. Illustrated in FIG. 1( a ) , a semiconductor die 30 is formed on a substrate which is made of silicon or other bulk semiconductor material. Semiconductor die 30 is part of a base semiconductor wafer, which contains additional semiconductor die not shown. The illustrative process shown in FIGS. 1( a )-1( e ) applies to the packaging of other die as well. The length of the die 30 is only for illustrative purposes and may not be drawn to scale.
  • the process is only illustrated for connection of one contact pad with one solder ball/bump through redistribution layer (RDL) as shown in FIG. 1( e ) .
  • the die 30 may comprise a plurality of contact pads connected to a plurality of solder ball/bumps through a network of RDLs according to its functional design.
  • the electrical signals from semiconductor die 30 are routed through the network of RDLs to one or more of the solder bumps according to the function of the semiconductor device.
  • Semiconductor die 30 includes a surface 31 , which may be an active surface, further containing active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die.
  • a conductive layer 32 is formed as a contact pad on surface 31 using a patterning and deposition process.
  • Semiconductor die 30 may have a plurality of contact pads 32 .
  • Conductive pad 32 may be made with aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other electrically conductive material.
  • the deposition of conductive pad 32 uses an electrolytic plating or electroless plating process.
  • the size, shape, and location of the contact pad 32 are only for illustration purposes and are not limiting.
  • the plurality of contact pads of the die 30 which are not shown, may be of the same size or of different sizes.
  • a passivation layer 34 is formed over semiconductor die 30 on top of the surface 31 and on top of the conductive pad 32 for structural support and physical isolation.
  • Passivation layer 34 can be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material.
  • An opening of the passivation layer 34 is made by removing a portion of passivation layer 34 using a mask-defined photoresist etching process to expose conductive pad 32 .
  • the size, shape, and location of the opening made are only for illustration purposes and are not limiting. It is advantageous to expose a portion of the top surface of the conductive pad 32 , as shown in FIG. 1( a ) .
  • RDL portion 46 is deposited over the passivation layer 34 and conductive pad 32 .
  • the RDL portion 46 may be deposited following the contour of passivation layer 34 .
  • RDL 46 can be made with, e.g., Al, Ni, nickel vanadium (NiV), Cu, or a Cu alloy.
  • RDL 46 can be made by an electrolytic plating or electroless plating process.
  • RDL 46 can be made with a single layer, or multiple layers using an adhesion layer of Ti, TiW, or Cr, for example.
  • the die 30 is connected to a number of RDL portions 46 to form a network of inter-level interconnects which may electrically connect to the contact pads of semiconductor die 30 according to the function of the semiconductor device.
  • RDL 46 may be used to refer a portion of RDL.
  • the height and length of the RDL 46 are only shown for illustrative purposes and not limiting.
  • One end 46 a of the RDL 46 is deposited on top of the passivation layer 34 and in contact with the conductive pad 32 through the passivation layer opening.
  • the shape of the 46 a end is shown for illustration purposes and are not limiting. There may be other kinds of shapes for the 46 a end of the RDL 46 layer. For example, the end of 46 a may extend further to cover more surfaces of passivation layer 34 , beyond the shape of the conductive pad 32 .
  • the other end 46 b of the RDL 46 is stopped somewhere beyond the conductive pad 32 , but before a solder ball projection region where, as described below, a solder ball/bump may be mounted.
  • the solder ball projection region may be determined by projecting other connectors instead of solder ball as well.
  • the location of 46 b may not be unique, but rather in a range, so that when a solder ball/bump 82 , shown in FIG. 1( a ) as shadowed, is mounted to the device, the pressure of the ball is not directly on top of the RDL 46 . As shown in FIG.
  • solder ball 82 when the solder ball 82 is mounted to the device 30 to connect it to the carrier substrate or printed circuit board (PCB), which will be done in step shown in FIG. 1( e ) , the outer periphery of the ball 82 projected to the surface of silicon 30 , passivation 34 is at a point 101 . It may be advantageous that the end 46 b terminates at a point before reaching the point 101 so that there is a gap between the end of 46 b and the point 101 .
  • the solder ball 82 is shown in FIG. 1( a ) as shadowed because it is not mounted in FIG. 1( a ) . It will be mounted in a step shown in FIG. 1( e ) .
  • the projected point 101 divide the surface of the passivation layer 34 into two regions, one region is for the RDL 46 , and another region contains no RDL portion and is used to receive a solder ball, which may be called as a solder ball projection region.
  • a passivation layer 54 is formed over passivation layers 34 and RDL 46 for structural support and physical isolation.
  • Passivation layer 54 can be made with SiN, SiO2, SiON, PI, BCB, PBO, or other insulating material.
  • the passivation layer 54 may be formed, e.g., conformed with the shape of RDL 46 , on top of RDL 46 or on top of the passivation layer 34 .
  • the passivation layer 54 is on top of the surface of the RDL 46 and extends further to cover the top of the conductive pad 32 and beyond.
  • the passivation layer 54 is formed so that the RDL 46 is completely covered by passivation layer 54 .
  • the size of passivation layer 54 is only for illustration purposes and is not limiting.
  • FIG. 1( c ) illustrates that a portion of passivation layer 54 is removed using a mask-defined etching process to expose a portion of RDL 46 , forming an opening 65 .
  • the size, shape, and location of the opening 65 are only for illustration purposes and are not limiting. There may be other size, shape, and location for the opening 65 .
  • FIG. 1( d ) illustrates that a metal layer 73 is deposited over passivation layer 54 , and the exposed RDL 46 through the opening 65 by an evaporation, electrolytic plating, electroless plating, or screen printing process.
  • Metal layer 73 is an under bump metallization (UBM) layer which follows the contour of passivation layer 54 and RDL 46 .
  • UBM 73 can be made with Ti, Ni, NiV, Cu, Cu alloy, any metal or electrically conductive material.
  • the size, shape, and location of the UBM 73 are only for illustration purposes and are not limiting. There may be other size, shape for the UBM 73 . There may be a multiple sub-layers of UBM 73 built on top of each other (not shown).
  • FIG. 1( e ) illustrates that an electrically conductive solder material 91 is deposited over UBM 73 and extending over the opening 65 and its walls, using an electrolytic plating or electroless plating process, or screen printing process.
  • the solder material can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other electrically conductive material.
  • This conductive solder material 91 is optional. In some embodiments, there may not be any conductive solder material 91 deposited.
  • FIG. 1( e ) further illustrates that a solder ball 82 is mounted on top of the solder material 91 and on top of the UBM 73 .
  • the solder ball 82 is positioned so that the projected outer periphery of the ball 82 to the surface of silicon 30 and passivation 34 is at a point 101 , and there is a gap between the point 101 and the end point of the RDL 46 .
  • the projected point 101 on the passivation layer 34 divides the surface of passivation layer 34 into two regions, one region is to hold the solder ball 82 while the RDL 46 is formed on the surface of another region. In this way, the pressure from the solder ball 82 is on the passivation layer 54 rather than on the RDL layer 46 , therefore reducing the cracks since passivation layer 54 has stronger mechanical support.
  • FIG. 1( f ) illustrates a top view of the solder ball 82 mounted on top of semiconductor device 10 .
  • the contact pad 32 is connected to the RDL 46 , which is further connected to the UBM 73 .
  • the circle 101 is the projected outer periphery of the solder ball 82 .
  • the circle 101 determines the solder ball projection region, and the RDL 46 is formed in another region with a gap between the end point of RDL 46 and the circle 101 .
  • the projected outer periphery of the solder ball 82 is of circular shape. If other connector is used instead of the solder ball 82 , the projected shape may not be a circle like 101 . As long as there is a gap between the end point of RDL 46 and the projected outer periphery of the connector, then the pressure of the connector would not be directly on the RDL 46 and it can help to reduce the pressure on RDL 46 .
  • FIGS. 1( a )-1( e ) The process shown in FIGS. 1( a )-1( e ) is only for illustration purposes, and are not limiting. There may be many variations of processing steps and processing materials that can be readily seen by those skilled in the art.
  • FIGS. 2( a )-2( c ) illustrate various WLP devices resulting from the WLP process demonstrated in FIGS. 1( a )-1( e ) .
  • a semiconductor die 30 includes an active surface 31 .
  • a conductive layer 32 is formed as a contact pad on the active surface 31 .
  • a passivation layer 34 is formed over semiconductor die 30 on top of the surface 31 and on top of the conductive pad 32 .
  • An opening of the passivation layer 34 is made to expose the top surface of the conductive pad 32 .
  • the surface of the passivation layer 34 is divided into two regions, and in a first region, an RDL 46 is deposited over and it may follow the contour of passivation layer 34 and conductive pad 32 .
  • One end of the RDL 46 is on top of the passivation layer 34 and in contact with the conductive pad 32 through the passivation layer opening.
  • the other end of the RDL 46 is stopped somewhere beyond the conductive pad 32 but within the first region.
  • a second region will be used to receive a solder ball 82 so that there is a gap between the end point of RDL 46 and the projected outer periphery of the solder ball 82 to the surface of passivation layer 34 .
  • a passivation layer 54 is formed over passivation layers 34 and RDL 46 , which may be conformed with the shape of layer 34 and RDL 46 to cover the RDL 46 completely.
  • a portion of passivation layer 54 is removed to expose a portion of the top surface of the RDL 46 , forming an opening 65 .
  • An UBM layer 73 is deposited over passivation layer 54 and the exposed RDL 46 through the opening 65 , to make connection between the UBM layer 73 and the RDL layer 46 which is further connected to the contact pad 32 .
  • a solder ball 82 is mounted on top of the UBM 73 .
  • an optional electrically conductive solder material 91 is deposited over UBM 73 first, and a solder ball 82 is mounted on top of the solder material 91 and on top of the UBM 73 .
  • the height of the passivation layer 54 in some embodiments may be in the range of 5 um to 30 um.
  • the size of the 65 opening may be wider than 20 um.
  • the size of the width the solder ball intersection with the UBM layer is around 180 um to 300 um.
  • FIG. 2( c ) further illustrates an additional and optional opening 67 in the layer UBM 73 .
  • the opening 67 is also formed in the passivation layer 54 , and the UBM 73 is deposited following the contour of the opening 67 .
  • the opening may only be formed only in UBM 73 , and the passivation 54 is as formed previously without an opening.
  • the opening 67 may be help to keep the mounted solder ball 82 in a fixed position since it would be easier for the solder ball 82 to maintain its position over the opening 67 as compared to maintain its position over a flat surface.
  • FIGS. 3( a )-3( c ) are top views of a WLP formed by the process shown in FIGS. 1( a )-1( e ) .
  • the UBM 73 may be of different shapes such as shown in FIGS. 3( a ), 3( b ), and 3( c ) . In FIG.
  • the UBM 73 has a plurality of connection branches which are all connected to the solder ball 82 on one end and to the RDL 46 at the other end, where the RDL 46 is further connected to the contact pad 32 .
  • FIG. 3( c ) there is only one branch 73 connecting the solder ball 82 to the RDL layer 46 .
  • FIG. 3( b ) shows a larger surface of the UBM 73 connected to the solder ball 82 and the smaller end of the UBM 72 is connected to the RDL 46 .
  • There may be other forms, shapes, and sizes of UBM 73 connecting the solder ball 82 to the RDL 46 which are not shown.
  • the embodiments of the present disclosure have several advantageous features. By reducing the length of the RDL layer so that the solder ball is directly on top of the second passivation layer, the stress on the RDL layer is reduced. The reliability of the WLP, on the other hand, is improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Description

This application is a continuation of U.S. patent application Ser. No. 14/853,006, filed on Sep. 14, 2015, entitled “Methods and Apparatus of Packaging Semiconductor Devices,” which is a continuation of U.S. patent application Ser. No. 14/065,134, filed on Oct. 28, 2013, now U.S. Pat. No. 9,136,235 issued on Sep. 15, 2015 entitled “Methods and Apparatus of Packaging Semiconductor Devices,” which is a divisional of U.S. patent application Ser. No. 13/302,551, filed on Nov. 22, 2011, now U.S. Pat. No. 8,569,886 issued on Oct. 29, 2013, entitled “Methods and Apparatus of Packaging Semiconductor Devices,” which applications are incorporated herein by reference.
BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
One type of smaller packaging for semiconductor devices that has been developed is wafer level packaging (WLP), in which integrated circuit die are packaged in packages that typically include a redistribution layer (RDL) that is used to fan out wiring for contact pads of the integrated circuit die so that electrical contact can be made on a larger pitch than contact pads of the die. Throughout this description, the term die is used to refer to both the singular and the plural.
WLP packages have been applied more and more in integrated circuit packaging due to the advantages of cost and simple structure. However, for some WLP packages, stress has been found to be directly applied on passivation (PSV) and extreme low-k (ELK) layers, causing ELK/PSV crack/delamination by severe fatigue loading during reliability testing.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1(a)-1(f) illustrate an embodiment of a WLP process, shown in cross-sectional view or in top view;
FIGS. 2(a)-2(c) illustrate embodiments of detailed cross-sectional views of WLP semiconductor devices; and
FIGS. 3(a)-3(c) illustrate top views of the connections between a conducting solder ball/bump to a contact pad within a WLP package.
 DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments of the present disclosure provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure.
A semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
Wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. FIGS. 1(a)-1(f) illustrate an embodiment of a WLP process, shown in cross-sectional view or in top view. Illustrated in FIG. 1(a), a semiconductor die 30 is formed on a substrate which is made of silicon or other bulk semiconductor material. Semiconductor die 30 is part of a base semiconductor wafer, which contains additional semiconductor die not shown. The illustrative process shown in FIGS. 1(a)-1(e) applies to the packaging of other die as well. The length of the die 30 is only for illustrative purposes and may not be drawn to scale. The process is only illustrated for connection of one contact pad with one solder ball/bump through redistribution layer (RDL) as shown in FIG. 1(e). The die 30 may comprise a plurality of contact pads connected to a plurality of solder ball/bumps through a network of RDLs according to its functional design. The electrical signals from semiconductor die 30 are routed through the network of RDLs to one or more of the solder bumps according to the function of the semiconductor device.
Semiconductor die 30 includes a surface 31, which may be an active surface, further containing active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. A conductive layer 32 is formed as a contact pad on surface 31 using a patterning and deposition process. Semiconductor die 30 may have a plurality of contact pads 32. Conductive pad 32 may be made with aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other electrically conductive material. The deposition of conductive pad 32 uses an electrolytic plating or electroless plating process. The size, shape, and location of the contact pad 32 are only for illustration purposes and are not limiting. The plurality of contact pads of the die 30, which are not shown, may be of the same size or of different sizes.
A passivation layer 34 is formed over semiconductor die 30 on top of the surface 31 and on top of the conductive pad 32 for structural support and physical isolation. Passivation layer 34 can be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material. An opening of the passivation layer 34 is made by removing a portion of passivation layer 34 using a mask-defined photoresist etching process to expose conductive pad 32. The size, shape, and location of the opening made are only for illustration purposes and are not limiting. It is advantageous to expose a portion of the top surface of the conductive pad 32, as shown in FIG. 1(a).
An RDL portion 46 is deposited over the passivation layer 34 and conductive pad 32. The RDL portion 46 may be deposited following the contour of passivation layer 34. RDL 46 can be made with, e.g., Al, Ni, nickel vanadium (NiV), Cu, or a Cu alloy. RDL 46 can be made by an electrolytic plating or electroless plating process. RDL 46 can be made with a single layer, or multiple layers using an adhesion layer of Ti, TiW, or Cr, for example. The die 30 is connected to a number of RDL portions 46 to form a network of inter-level interconnects which may electrically connect to the contact pads of semiconductor die 30 according to the function of the semiconductor device. RDL 46 may be used to refer a portion of RDL.
As illustrated in FIG. 1(a), the height and length of the RDL 46 are only shown for illustrative purposes and not limiting. One end 46 a of the RDL 46 is deposited on top of the passivation layer 34 and in contact with the conductive pad 32 through the passivation layer opening. The shape of the 46 a end is shown for illustration purposes and are not limiting. There may be other kinds of shapes for the 46 a end of the RDL 46 layer. For example, the end of 46 a may extend further to cover more surfaces of passivation layer 34, beyond the shape of the conductive pad 32.
On the other hand, the other end 46 b of the RDL 46 is stopped somewhere beyond the conductive pad 32, but before a solder ball projection region where, as described below, a solder ball/bump may be mounted. The solder ball projection region may be determined by projecting other connectors instead of solder ball as well. The location of 46 b may not be unique, but rather in a range, so that when a solder ball/bump 82, shown in FIG. 1(a) as shadowed, is mounted to the device, the pressure of the ball is not directly on top of the RDL 46. As shown in FIG. 1(a), when the solder ball 82 is mounted to the device 30 to connect it to the carrier substrate or printed circuit board (PCB), which will be done in step shown in FIG. 1(e), the outer periphery of the ball 82 projected to the surface of silicon 30, passivation 34 is at a point 101. It may be advantageous that the end 46 b terminates at a point before reaching the point 101 so that there is a gap between the end of 46 b and the point 101. The solder ball 82 is shown in FIG. 1(a) as shadowed because it is not mounted in FIG. 1(a). It will be mounted in a step shown in FIG. 1(e). The projected point 101 divide the surface of the passivation layer 34 into two regions, one region is for the RDL 46, and another region contains no RDL portion and is used to receive a solder ball, which may be called as a solder ball projection region.
Furthermore, as illustrated in FIG. 1(b), a passivation layer 54 is formed over passivation layers 34 and RDL 46 for structural support and physical isolation. Passivation layer 54 can be made with SiN, SiO2, SiON, PI, BCB, PBO, or other insulating material. The passivation layer 54 may be formed, e.g., conformed with the shape of RDL 46, on top of RDL 46 or on top of the passivation layer 34. At one end, the passivation layer 54 is on top of the surface of the RDL 46 and extends further to cover the top of the conductive pad 32 and beyond. At another end, the passivation layer 54 is formed so that the RDL 46 is completely covered by passivation layer 54. The size of passivation layer 54 is only for illustration purposes and is not limiting.
FIG. 1(c) illustrates that a portion of passivation layer 54 is removed using a mask-defined etching process to expose a portion of RDL 46, forming an opening 65. The size, shape, and location of the opening 65 are only for illustration purposes and are not limiting. There may be other size, shape, and location for the opening 65.
FIG. 1(d) illustrates that a metal layer 73 is deposited over passivation layer 54, and the exposed RDL 46 through the opening 65 by an evaporation, electrolytic plating, electroless plating, or screen printing process. Metal layer 73 is an under bump metallization (UBM) layer which follows the contour of passivation layer 54 and RDL 46. UBM 73 can be made with Ti, Ni, NiV, Cu, Cu alloy, any metal or electrically conductive material. The size, shape, and location of the UBM 73 are only for illustration purposes and are not limiting. There may be other size, shape for the UBM 73. There may be a multiple sub-layers of UBM 73 built on top of each other (not shown).
FIG. 1(e) illustrates that an electrically conductive solder material 91 is deposited over UBM 73 and extending over the opening 65 and its walls, using an electrolytic plating or electroless plating process, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other electrically conductive material. This conductive solder material 91 is optional. In some embodiments, there may not be any conductive solder material 91 deposited.
FIG. 1(e) further illustrates that a solder ball 82 is mounted on top of the solder material 91 and on top of the UBM 73. The solder ball 82 is positioned so that the projected outer periphery of the ball 82 to the surface of silicon 30 and passivation 34 is at a point 101, and there is a gap between the point 101 and the end point of the RDL 46. The projected point 101 on the passivation layer 34 divides the surface of passivation layer 34 into two regions, one region is to hold the solder ball 82 while the RDL 46 is formed on the surface of another region. In this way, the pressure from the solder ball 82 is on the passivation layer 54 rather than on the RDL layer 46, therefore reducing the cracks since passivation layer 54 has stronger mechanical support.
FIG. 1(f) illustrates a top view of the solder ball 82 mounted on top of semiconductor device 10. The contact pad 32 is connected to the RDL 46, which is further connected to the UBM 73. The circle 101 is the projected outer periphery of the solder ball 82. The circle 101 determines the solder ball projection region, and the RDL 46 is formed in another region with a gap between the end point of RDL 46 and the circle 101. The projected outer periphery of the solder ball 82 is of circular shape. If other connector is used instead of the solder ball 82, the projected shape may not be a circle like 101. As long as there is a gap between the end point of RDL 46 and the projected outer periphery of the connector, then the pressure of the connector would not be directly on the RDL 46 and it can help to reduce the pressure on RDL 46.
The process shown in FIGS. 1(a)-1(e) is only for illustration purposes, and are not limiting. There may be many variations of processing steps and processing materials that can be readily seen by those skilled in the art. FIGS. 2(a)-2(c) illustrate various WLP devices resulting from the WLP process demonstrated in FIGS. 1(a)-1(e).
As illustrated in FIG. 2(a)-2(c), a semiconductor die 30 includes an active surface 31. A conductive layer 32 is formed as a contact pad on the active surface 31. A passivation layer 34 is formed over semiconductor die 30 on top of the surface 31 and on top of the conductive pad 32. An opening of the passivation layer 34 is made to expose the top surface of the conductive pad 32. The surface of the passivation layer 34 is divided into two regions, and in a first region, an RDL 46 is deposited over and it may follow the contour of passivation layer 34 and conductive pad 32. One end of the RDL 46 is on top of the passivation layer 34 and in contact with the conductive pad 32 through the passivation layer opening. The other end of the RDL 46 is stopped somewhere beyond the conductive pad 32 but within the first region. A second region will be used to receive a solder ball 82 so that there is a gap between the end point of RDL 46 and the projected outer periphery of the solder ball 82 to the surface of passivation layer 34. A passivation layer 54 is formed over passivation layers 34 and RDL 46, which may be conformed with the shape of layer 34 and RDL 46 to cover the RDL 46 completely. A portion of passivation layer 54 is removed to expose a portion of the top surface of the RDL 46, forming an opening 65. An UBM layer 73 is deposited over passivation layer 54 and the exposed RDL 46 through the opening 65, to make connection between the UBM layer 73 and the RDL layer 46 which is further connected to the contact pad 32.
In FIG. 2(a), a solder ball 82 is mounted on top of the UBM 73. In FIG. 2(b), an optional electrically conductive solder material 91 is deposited over UBM 73 first, and a solder ball 82 is mounted on top of the solder material 91 and on top of the UBM 73.
Furthermore, as shown in FIG. 2(a), the height of the passivation layer 54 in some embodiments may be in the range of 5 um to 30 um. The size of the 65 opening may be wider than 20 um. The size of the width the solder ball intersection with the UBM layer is around 180 um to 300 um.
FIG. 2(c) further illustrates an additional and optional opening 67 in the layer UBM 73. The opening 67 is also formed in the passivation layer 54, and the UBM 73 is deposited following the contour of the opening 67. In another embodiment, the opening may only be formed only in UBM 73, and the passivation 54 is as formed previously without an opening. The opening 67 may be help to keep the mounted solder ball 82 in a fixed position since it would be easier for the solder ball 82 to maintain its position over the opening 67 as compared to maintain its position over a flat surface.
The interconnect structure resulting from the process shown in FIGS. 1(a)-1(e), electrically connects electrical signals from semiconductor die 30 through conductive pad 32 and RDL 46 and further to solder bump 82 by way of UBM 73. RDLs 46 provide a complete inter-level interconnect structure for the WLP without using through hole vias. More details of such connection sequences are shown in FIGS. 3(a)-3(c), which are top views of a WLP formed by the process shown in FIGS. 1(a)-1(e). The UBM 73 may be of different shapes such as shown in FIGS. 3(a), 3(b), and 3(c). In FIG. 3(a), the UBM 73 has a plurality of connection branches which are all connected to the solder ball 82 on one end and to the RDL 46 at the other end, where the RDL 46 is further connected to the contact pad 32. In FIG. 3(c), there is only one branch 73 connecting the solder ball 82 to the RDL layer 46. FIG. 3(b) shows a larger surface of the UBM 73 connected to the solder ball 82 and the smaller end of the UBM 72 is connected to the RDL 46. There may be other forms, shapes, and sizes of UBM 73 connecting the solder ball 82 to the RDL 46, which are not shown.
The embodiments of the present disclosure have several advantageous features. By reducing the length of the RDL layer so that the solder ball is directly on top of the second passivation layer, the stress on the RDL layer is reduced. The reliability of the WLP, on the other hand, is improved.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Claims (20)

What is claimed is:
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a polymer layer at least partially over a redistribution layer over a substrate, the depositing of the polymer layer comprises forming a first surface facing away from the substrate in a first direction at a first distance from the substrate and forming a second surface completely facing away from the substrate in the first direction, the second surface being at a second distance from the substrate less than the first distance;
depositing an underbump metallization over both the first surface and the second surface, the underbump metallization extending through the first surface to make electrical contact with the redistribution layer; and
placing a bump in electrical connection with the underbump metallization, the underbump metallization being between the bump and the second surface.
2. The method of claim 1, wherein after the depositing the underbump metallization the underbump metallization has a third surface facing the substrate that is located a third distance from the substrate less than the second distance.
3. The method of claim 2, wherein the third surface has a width of between about 80 μm and about 270 μm.
4. The method of claim 1, wherein the polymer layer has a third surface opposite the second surface and wherein a distance between the third surface and the second surface is between about 5 μm and about 30 μm.
5. The method of claim 1, wherein the bump has a third surface facing the substrate at a third distance from the substrate, the third distance being less than the first distance.
6. The method of claim 5, wherein the underbump metallization extends through the second surface to make contact with a dielectric layer different from the polymer layer.
7. The method of claim 1, wherein the redistribution layer has a first straight portion and a second curved portion.
8. A method of manufacturing a semiconductor device, the method comprising:
forming a redistribution layer over a substrate;
placing a passivation layer over the redistribution layer, wherein a first portion of the passivation layer is in physical contact with a top surface of the redistribution layer and a second portion of the passivation layer is in physical contact with a sidewall of the redistribution layer adjacent to the top surface of the redistribution layer;
forming a first opening through the first portion of the passivation layer;
depositing an underbump metallization through the first opening and over the second portion of the passivation layer; and
placing a conductive bump onto the underbump metallization, wherein after the placing the conductive bump the conductive bump is located over the second portion of the passivation layer and does not directly overlie the redistribution layer in a direction normal to a major surface of the substrate.
9. The method of claim 8, further comprising forming a second opening through the first portion of the passivation layer different from the first opening, wherein the depositing the underbump metallization deposits the underbump metallization through the second opening.
10. The method of claim 9, further comprising forming a third opening through the first portion of the passivation layer different from the first opening and the second opening, wherein the depositing the underbump metallization deposits the underbump metallization through the third opening.
11. The method of claim 8, wherein the underbump metallization has a first longitudinal axis in a top down view, the first longitudinal axis being aligned with a second longitudinal axis of the redistribution layer.
12. The method of claim 11, wherein the underbump metallization has a third longitudinal axis in a top down view, the third longitudinal axis being mis-aligned with the second longitudinal axis of the redistribution layer.
13. The method of claim 12, wherein the underbump metallization has a fourth longitudinal axis in a top down view, the fourth longitudinal axis being mis-aligned with the second longitudinal axis of the redistribution layer.
14. The method of claim 8, wherein the underbump metallization has a first longitudinal axis in a top down view, the first longitudinal axis being mis-aligned with a second longitudinal axis of the redistribution layer.
15. A method of manufacturing a semiconductor device, the method comprising:
placing a passivation layer over a redistribution layer and a substrate, the passivation layer comprising a first portion directly over the redistribution layer and a second portion laterally removed from being directly over the redistribution layer;
forming at least one opening through the passivation layer; and
placing an underbump metallization through the at least one opening to form a first interface between the underbump metallization and the redistribution layer, a second interface between the underbump metallization and the first portion of the passivation layer, and a third interface between the underbump metallization and the second portion of the passivation layer, wherein the third interface is closer to the substrate than the second interface.
16. The method of claim 15, wherein the third interface is closer to the substrate than the first interface.
17. The method of claim 16, wherein the forming the at least one opening through the passivation layer comprises forming an opening through the second portion of the passivation layer.
18. The method of claim 15, further comprising placing a conductive bump directly over the third interface.
19. The method of claim 15, wherein the second interface is continuous.
20. The method of claim 15, wherein the second interface is discontinuous.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11502049B2 (en) 2020-05-06 2022-11-15 Qualcomm Incorporated Package comprising multi-level vertically stacked redistribution portions

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204876B2 (en) * 2013-03-07 2019-02-12 Maxim Integrated Products, Inc. Pad defined contact for wafer level package
TWI493675B (en) 2013-05-01 2015-07-21 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US20150069585A1 (en) * 2013-09-12 2015-03-12 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with an angled passivation layer
US9373594B2 (en) * 2014-02-13 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Under bump metallization
US10348565B2 (en) * 2014-09-25 2019-07-09 Oracle International Corporation System and method for rule-based elasticity in a multitenant application server environment
US9666550B2 (en) * 2014-12-16 2017-05-30 Tongfu Microelectronics Co., Ltd. Method and structure for wafer-level packaging
JP6436531B2 (en) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 Manufacturing method of semiconductor device
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
KR102357937B1 (en) * 2015-08-26 2022-02-04 삼성전자주식회사 Semiconductor chip, method for fabricating the same, and semiconductor package comprising the same
KR102456667B1 (en) 2015-09-17 2022-10-20 삼성전자주식회사 Semiconductor devices having redistribution pads
US10020239B2 (en) * 2016-01-12 2018-07-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR102487532B1 (en) * 2016-04-28 2023-01-12 에스케이하이닉스 주식회사 Semiconductor chip and stacked semiconductor chip using the same
KR102658923B1 (en) 2016-09-12 2024-04-18 삼성전자주식회사 Semiconductor device and semiconductor package
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
DE102018124497B4 (en) 2018-10-04 2022-06-30 Infineon Technologies Ag Semiconductor device and method of forming a semiconductor device
KR102527569B1 (en) * 2018-10-16 2023-05-03 에스케이하이닉스 주식회사 Semiconductor device including re-distribution layer structure and method of forming the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
TWI717155B (en) * 2019-12-17 2021-01-21 財團法人工業技術研究院 Chip package structure
KR20220056309A (en) * 2020-10-27 2022-05-06 삼성전자주식회사 Semiconductor package

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244002A (en) 1977-10-19 1981-01-06 Nippon Electric Co., Ltd. Semiconductor device having bump terminal electrodes
US20050017355A1 (en) 2003-05-27 2005-01-27 Chien-Kang Chou Water level processing method and structure to manufacture two kinds of bumps, gold and solder, on one wafer
US20070238283A1 (en) 2006-04-05 2007-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Novel under-bump metallization for bond pad soldering
US20080150161A1 (en) * 2006-12-21 2008-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
US20080197475A1 (en) 2007-02-16 2008-08-21 Chipmos Technologies Inc. Packaging conductive structure and method for forming the same
US20090014869A1 (en) 2004-10-29 2009-01-15 Vrtis Joan K Semiconductor device package with bump overlying a polymer layer
US20090250813A1 (en) 2005-09-23 2009-10-08 Yaojian Lin Integrated circuit solder bumping system
US20090278263A1 (en) 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US20090283905A1 (en) 2008-03-19 2009-11-19 Hsiang-Ming Huang Conductive structure of a chip
US20100193950A1 (en) 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
US20100213608A1 (en) 2009-02-24 2010-08-26 Unisem Advanced Technologies Sdn. Bhd., a company incorporated in Malaysia Solder bump UBM structure
US20100264516A1 (en) 2007-11-07 2010-10-21 Stats Chippac, Ltd. Method of Forming an Inductor on a Semiconductor Wafer
US20110024901A1 (en) 2009-07-30 2011-02-03 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device and semiconductor device
US7977783B1 (en) 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US20110186995A1 (en) 2007-04-23 2011-08-04 Flipchip International, Llc Solder bump interconnect
US7994045B1 (en) 2009-09-08 2011-08-09 Amkor Technology, Inc. Bumped chip package fabrication method and structure
US20110204515A1 (en) 2010-02-22 2011-08-25 Texas Instruments Incorporated Ic die including rdl capture pads with notch having bonding connectors or its ubm pad over the notch
US8035226B1 (en) 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US20110298137A1 (en) 2007-12-14 2011-12-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
US20120038047A1 (en) 2010-08-10 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in FO-WLCSP
US20120061823A1 (en) 2010-09-10 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US20120098123A1 (en) 2010-10-26 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Molded Chip Interposer Structure and Methods
US20120104604A1 (en) 2010-11-01 2012-05-03 Texas Instruments Incorporated Crack arrest vias for ic devices
US20120199967A1 (en) 2010-08-18 2012-08-09 Cambridge Silicon Radio Limited Interconnection Structure
US20130026618A1 (en) 2011-07-27 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US20130037948A1 (en) 2011-08-09 2013-02-14 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via

Patent Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244002A (en) 1977-10-19 1981-01-06 Nippon Electric Co., Ltd. Semiconductor device having bump terminal electrodes
US20050017355A1 (en) 2003-05-27 2005-01-27 Chien-Kang Chou Water level processing method and structure to manufacture two kinds of bumps, gold and solder, on one wafer
US20090014869A1 (en) 2004-10-29 2009-01-15 Vrtis Joan K Semiconductor device package with bump overlying a polymer layer
US20090250813A1 (en) 2005-09-23 2009-10-08 Yaojian Lin Integrated circuit solder bumping system
US8487438B2 (en) 2005-09-23 2013-07-16 Stats Chippac Ltd. Integrated circuit system having different-size solder bumps and different-size bonding pads
US20070238283A1 (en) 2006-04-05 2007-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Novel under-bump metallization for bond pad soldering
US20080150161A1 (en) * 2006-12-21 2008-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
US20080197475A1 (en) 2007-02-16 2008-08-21 Chipmos Technologies Inc. Packaging conductive structure and method for forming the same
US7656020B2 (en) 2007-02-16 2010-02-02 Chipmos Technologies, Inc. Packaging conductive structure for a semiconductor substrate having a metallic layer
US20120228765A1 (en) 2007-04-23 2012-09-13 Flipchip International, Llc Solder bump interconnect
US8188606B2 (en) 2007-04-23 2012-05-29 Flipchip International, Llc Solder bump interconnect
US20110186995A1 (en) 2007-04-23 2011-08-04 Flipchip International, Llc Solder bump interconnect
US20100264516A1 (en) 2007-11-07 2010-10-21 Stats Chippac, Ltd. Method of Forming an Inductor on a Semiconductor Wafer
US20130015555A1 (en) 2007-11-07 2013-01-17 Stats Chippac, Ltd. Method of Forming an Inductor on a Semiconductor Wafer
US8309452B2 (en) 2007-11-07 2012-11-13 Stats Chippac, Ltd. Method of forming an inductor on a semiconductor wafer
US20110298137A1 (en) 2007-12-14 2011-12-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
US20090283905A1 (en) 2008-03-19 2009-11-19 Hsiang-Ming Huang Conductive structure of a chip
US20090278263A1 (en) 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US8035226B1 (en) 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US20100193950A1 (en) 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
US20100213608A1 (en) 2009-02-24 2010-08-26 Unisem Advanced Technologies Sdn. Bhd., a company incorporated in Malaysia Solder bump UBM structure
US7915741B2 (en) 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
US20110024901A1 (en) 2009-07-30 2011-02-03 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device and semiconductor device
US8314491B2 (en) 2009-07-30 2012-11-20 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device and semiconductor device
US7977783B1 (en) 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US8263486B1 (en) 2009-09-08 2012-09-11 Amkor Technology, Inc. Bumped chip package fabrication method and structure
US7994045B1 (en) 2009-09-08 2011-08-09 Amkor Technology, Inc. Bumped chip package fabrication method and structure
US8269348B2 (en) 2010-02-22 2012-09-18 Texas Instruments Incorporated IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch
US20110204515A1 (en) 2010-02-22 2011-08-25 Texas Instruments Incorporated Ic die including rdl capture pads with notch having bonding connectors or its ubm pad over the notch
US8193610B2 (en) 2010-08-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP
US20120038047A1 (en) 2010-08-10 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in FO-WLCSP
US20120199967A1 (en) 2010-08-18 2012-08-09 Cambridge Silicon Radio Limited Interconnection Structure
US8283781B2 (en) 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US20120061823A1 (en) 2010-09-10 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US20120098123A1 (en) 2010-10-26 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Molded Chip Interposer Structure and Methods
US8338945B2 (en) 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8304867B2 (en) 2010-11-01 2012-11-06 Texas Instruments Incorporated Crack arrest vias for IC devices
US20120104604A1 (en) 2010-11-01 2012-05-03 Texas Instruments Incorporated Crack arrest vias for ic devices
US20130026618A1 (en) 2011-07-27 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US20130037948A1 (en) 2011-08-09 2013-02-14 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11502049B2 (en) 2020-05-06 2022-11-15 Qualcomm Incorporated Package comprising multi-level vertically stacked redistribution portions

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US20160005704A1 (en) 2016-01-07
US9136235B2 (en) 2015-09-15
US20170256512A1 (en) 2017-09-07
US8569886B2 (en) 2013-10-29
US20140057431A1 (en) 2014-02-27
US9659890B2 (en) 2017-05-23
US20130127052A1 (en) 2013-05-23

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