US10198394B2 - Reduced pin count interface - Google Patents

Reduced pin count interface Download PDF

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US10198394B2
US10198394B2 US15/283,310 US201615283310A US10198394B2 US 10198394 B2 US10198394 B2 US 10198394B2 US 201615283310 A US201615283310 A US 201615283310A US 10198394 B2 US10198394 B2 US 10198394B2
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interface
signals
pins
registers
control
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US20170344512A1 (en
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Michelle Jen
Dan Froelich
Debendra Das Sharma
Bruce Tennant
Quinn Devine
Su Wei Lim
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Intel Corp
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Intel Corp
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Priority to EP17803213.2A priority patent/EP3465453B1/de
Priority to PCT/US2017/027720 priority patent/WO2017204922A1/en
Priority to CN202011576801.4A priority patent/CN112579496A/zh
Priority to EP20216390.3A priority patent/EP3822800B1/de
Priority to CN201780025415.6A priority patent/CN109074341B/zh
Priority to PL20216390.3T priority patent/PL3822800T3/pl
Publication of US20170344512A1 publication Critical patent/US20170344512A1/en
Priority to US16/266,992 priority patent/US10706003B2/en
Publication of US10198394B2 publication Critical patent/US10198394B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • FIG. 5 illustrates a representation of a PHY/MAC interface.
  • FIG. 7 illustrates a representation of a second, register-based version of a PIPE PHY/MAC interface.
  • FIG. 9 illustrates a signaling diagram illustrating an example transaction involving a register of an example PHY/MAC interface.
  • FIG. 10 is a flowchart illustrating example techniques within an example PHY/MAC interface.
  • FIG. 12 illustrates another embodiment of a block diagram for a computing system.
  • embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation.
  • the disclosed embodiments are not limited to desktop computer systems or UltrabooksTM. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications.
  • handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs.
  • Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below.
  • DSP digital signal processor
  • NetPC network computers
  • Set-top boxes network hubs
  • the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency.
  • interconnect architectures to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation.
  • different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the invention described herein.
  • PCI Express Peripheral Component Interconnect Express
  • PCIe Peripheral Component Interconnect Express
  • a primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices.
  • PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms.
  • Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface.
  • PCI Express takes advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features.
  • Power Management Quality Of Service (QoS)
  • Hot-Plug/Hot-Swap support Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.
  • System 100 includes processor 105 and system memory 110 coupled to controller hub 115 .
  • Processor 105 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor.
  • Processor 105 is coupled to controller hub 115 through front-side bus (FSB) 106 .
  • FSB 106 is a serial point-to-point interconnect as described below.
  • link 106 includes a serial, differential interconnect architecture that is compliant with different interconnect standard.
  • System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100 .
  • System memory 110 is coupled to controller hub 115 through memory interface 116 .
  • Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.
  • DDR double-data rate
  • DRAM dynamic RAM
  • controller hub 115 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy.
  • PCIe Peripheral Component Interconnect Express
  • Examples of controller hub 115 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub.
  • chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH).
  • MCH memory controller hub
  • ICH interconnect controller hub
  • current systems often include the MCH integrated with processor 105 , while controller 115 is to communicate with I/O devices, in a similar manner as described below.
  • peer-to-peer routing is optionally supported through root complex 115 .
  • controller hub 115 is coupled to switch/bridge 120 through serial link 119 .
  • Input/output modules 117 and 121 which may also be referred to as interfaces/ports 117 and 121 , include/implement a layered protocol stack to provide communication between controller hub 115 and switch 120 .
  • multiple devices are capable of being coupled to switch 120 .
  • Layered protocol stack 200 includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack.
  • QPI Quick Path Interconnect
  • PCIe stack a next generation high performance computing interconnect stack
  • protocol stack 200 is a PCIe protocol stack including transaction layer 205 , link layer 210 , and physical layer 220 .
  • An interface such as interfaces 117 , 118 , 121 , 122 , 126 , and 131 in FIG. 1 , may be represented as communication protocol stack 200 .
  • Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.
  • transaction descriptor 300 is a mechanism for carrying transaction information.
  • transaction descriptor 300 supports identification of transactions in a system.
  • Other potential uses include tracking modifications of default transaction ordering and association of transaction with channels.
  • Transaction descriptor 300 includes global identifier field 302 , attributes field 304 and channel identifier field 306 .
  • global identifier field 302 is depicted comprising local transaction identifier field 308 and source identifier field 310 .
  • global transaction identifier 302 is unique for all outstanding requests.
  • local transaction identifier field 308 is a field generated by a requesting agent, and it is unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier 310 uniquely identifies the requestor agent within a PCIe hierarchy. Accordingly, together with source ID 310 , local transaction identifier 308 field provides global identification of a transaction within a hierarchy domain.
  • physical layer 220 includes logical sub block 221 and electrical sub-block 222 to physically transmit a packet to an external device.
  • logical sub-block 221 is responsible for the “digital” functions of Physical Layer 221 .
  • the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block 222 , and a receiver section to identify and prepare received information before passing it to the Link Layer 210 .
  • Physical block 222 includes a transmitter and a receiver.
  • the transmitter is supplied by logical sub-block 221 with symbols, which the transmitter serializes and transmits onto to an external device.
  • the receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream.
  • the bit-stream is de-serialized and supplied to logical sub-block 221 .
  • an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received.
  • special symbols are used to frame a packet with frames 223 .
  • the receiver also provides a symbol clock recovered from the incoming serial stream.
  • a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented.
  • an port/interface that is represented as a layered protocol includes: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer.
  • CSI common standard interface
  • a transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path.
  • a connection between two devices, such as device 405 and device 410 is referred to as a link, such as link 415 .
  • a link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception).
  • a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.
  • each symmetric lane contains one transmit differential pair and one receive differential pair.
  • Asymmetric lanes can contain unequal ratios of transmit and receive pairs.
  • Some technologies can utilize symmetric lanes (e.g., PCIe), while others (e.g., Displayport) may not and may even including only transmit or only receive pairs, among other examples.
  • a differential pair refers to two transmission paths, such as lines 416 and 417 , to transmit differential signals.
  • lines 416 and 417 to transmit differential signals.
  • line 416 toggles from a low voltage level to a high voltage level, i.e. a rising edge
  • line 417 drives from a high logic level to a low logic level, i.e. a falling edge.
  • Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.
  • a data link layer or logical physical layer can include a controller or embody a media access control (MAC) layer.
  • the physical (PHY) layer e.g., its logic and/or physical fabric
  • IP intellectual property
  • computing, block can be provided as a separate intellectual property (IP), or computing, block, which can be coupled with other computing block providing other portions of the hardware logic to implement an interconnect stack.
  • IP intellectual property
  • an interface can be provided to connect the computing blocks while still supporting a particular interconnect protocol (or potentially multiple different interconnect protocols) over the resulting interconnect (e.g., provided by the interconnected computing blocks).
  • the PHY Interface for the PCI Express architecture has been developed to define such interfaces.
  • PIPE has been extended to enable interfaces between controllers and PHYs in now multiple different interconnect technologies, including not only PCIe, but also SATA and USB architectures.
  • PIPE is intended to enable the development of functionally equivalent PCI Express, SATA and USB PHY's.
  • PHYs can be delivered as discrete integrated chip packages (ICs) or as macrocells for inclusion in ASIC designs or other systems.
  • ICs integrated chip packages
  • the specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY.
  • PIPE is defined to provide a standard interface between such a PHY and a Media Access Layer (MAC) and/or Link Layer ASIC.
  • MAC Media Access Layer
  • a standardized PHY interface, such as PIPE can provide an interface to which ASIC and endpoint device vendors can develop.
  • the MAC layer (or other controller layer) may be a part of the logical PHY layer and a register-based interface (adopting at least some of the features described herein) can connect the logical PHY to the analog or physical PHY, among other examples.
  • USB Type-C which includes support for Displayport, Thunderbolt, and configurable Rx/Tx lane pairs, among other examples.
  • Such improvements would result in a significant increase of the signal wire (and pin) count of the PIPE interface using the current scheme of dedicated signals for each operation.
  • the traditional PIPE interface is reaching a point where the escalating pin count threatens its future scalability and usability.
  • escalating signal and pin count of a defined MAC-PHY can be addressed by providing a low pin count version of the defined interface (e.g., a PIPE interface) through the utilization of a register-based status and control interface.
  • a set of datapath signals and control and status signals can be defined.
  • the current PIPE interface defines datapath signals and control and status signals per Rx/Tx lane pair (and other interfaces may additionally support configurable pairs where pairs are configured either as ⁇ Rx, Tx ⁇ , ⁇ Rx, Rx ⁇ , ⁇ Tx, Tx ⁇ or ⁇ Tx, Rx ⁇ , etc.).
  • a low pin count version of a traditional PIPE interface can be implemented, for instance, by providing an interface that maintains dedicated wires for datapath signals, asynchronous control and status signals, and latency-sensitive control and status signals, but that maps remaining control and status signals defined for the interface to registers (e.g. 8-bit, 16-bit, or 32-bit registers), which can be accessed over a small number of additional pins/wires, such as wires facilitating data transmission of 4-bits, 8-bits, etc. per direction.
  • registers e.g. 8-bit, 16-bit, or 32-bit registers
  • an address space can be provided (e.g., 12 address bits), into which the defined registers are mapped.
  • this address space can be designed to be deliberately large to accommodate expansion of the set of operations, control and status signals, that are to use these defined registers. This allows plenty of headroom for future expansion as well as room to house vendor-specific registers that PHY designs can use to expose useful status information to the controller or to provide additional configurability.
  • a framing scheme can also be defined in connection with the interface, by which a corresponding computing block may identify boundaries (e.g., start and end) of potentially multiple sequential (or contemporaneous) register transactions, each transaction serving to communicate one or more control or status signals in lieu of these same signals being driven over dedicated wires, as is done, for instance, in traditional PIPE interfaces, among other example features.
  • an improved MAC-PHY interface can enable a defined interface to be extended to support complicated and large signal sets (e.g., such as when extending PIPE specification support for USB Type-C), while at the same time reducing the interface's signal and pin count.
  • the current PIPE interface signal count would roughly need to double to support Type-C configurable pairs, which would make PIPE compliant Type-C designs very challenging to implement from a physical design point of view.
  • An improved interface design which offloads some signals, previously using dedicated wires, to specialized registers, may also provide the ability to enable more interface operations in the future, as the protocols supported by the interface (e.g., PIPE) evolve to add new features, all while saving the interface from further increases in interface signal count.
  • PIPE protocols supported by the interface
  • FIG. 6 a simplified block diagram 600 is shown of a conventional PIPE interface coupling a MAC computing block 605 with a PHY computing block 610 .
  • the interface can include a control and status interface (for control and status signaling) with roughly 67 control and status inputs and 80 control and status outputs per lane (i.e., Rx/Tx pair).
  • Rx/Tx pair control and status outputs per lane
  • FIG. 7 a simplified block diagram 700 is shown of an improved PIPE interface utilizing a register-based, low pin count PIPE control and status interface.
  • the interface is adapted for coupling a MAC computing block 705 with a PHY computing block 710 .
  • subsets of the control and status signals defined for the interface can be categorized as either asynchronous signals, timing critical signals, and regular control and status signals.
  • the asynchronous and timing critical control and status signals may be assigned dedicated wires on the improved interface, such as shown in FIG. 7 .
  • the regular control and status signals may be mapped into and replaced by the bits of registers (e.g., 715 , 720 ), which are accessed over a small set of wires (e.g.
  • Register commands e.g. reads and writes, register address, and register data may be transmitted in a time-multiplexed manner across this small serial interface.
  • the datapath related signals of the interface may be separate from the control and status signals and may, in effect, be the same or very similar to those provided in conventional interface implementations (e.g., traditional PIPE interfaces).
  • FIG. 8 a table 800 is illustrated showing an example of how some of the PIPE control and status signals can be mapped into 8-bit PIPE registers. While the example of FIG. 8 illustrated a small subset of the numerous control and status signals that may be mapped to register bits in a computing block, it should be appreciated that, in practice, potentially all of the control and status signals of a defined link layer-physical layer interface (e.g., PIPE) may be mapped to register bits (e.g., with exceptions for the asynchronous and timing critical control signals, which may remain implemented through dedicated wires). Further, while the example of FIG. 8 shows an 8-bit register, other potential register widths can just as easily be used, including 16- or 32-bit registers, etc.
  • PIPE link layer-physical layer interface
  • MAC ⁇ PHY control and status signals can be mapped into an address space starting at address zero, while the PHY ⁇ MAC control and status signals can be mapped into another address space starting at address zero.
  • a 12-bit address space is shown, which may be considered large enough to accommodate the currently defined PIPE signals with plenty of headroom for future signal growth, however, other address space sizes can be chosen in other examples.
  • a large address space may be utilized in connection with the registers to enable room for a dedicated address range for vendor specific registers that can be used to expose useful PHY status information and/or to provide additional configurability.
  • different sized address spaces can be provided that can be accessed via different commands, depending on latency requirements of transmitting the full command plus address bits across the serial interface, among other example implementations.
  • Bits within a set of status/control registers of an example PHY/MAC interface can be mapped to defined signals in a set of signals defined or extended in the PHY/MAC interface (e.g., the signals defined in the PIPE specification).
  • a “1” is written to a bit mapped to a particular signal, this value is interpreted the same as if the particular signal were received in an implementation of the interface that provides dedicated wires to each of the signals.
  • Table 1 provides examples of some register commands for use in accessing registers maintained in connection with control and status signals defined for a MAC-PHY interface, such as PIPE.
  • a no operation (or “NOP”) command can be utilized to indicate that there is no operation being requested (e.g., for use during idle states).
  • Write operations can be used to replace transmission of one or more of a set of control and status signals defined for the interface. For instance, a write can write a value to a particular bit of a particular register mapped to a particular one of the set of control and status signals. The value of the particular bit can be interpreted as the receipt of the particular signal (even though the particular signal was not actually sent (e.g., as the dedicated wire has been omitted in the improved interface design)).
  • an interface can provide for a combination of signals in the set of control and status signals to be sent at the same time. For instance, certain PIPE signals may need to be aligned so that their values take effect during the same cycle. In a conventional version of the interface, this combination of signals can be transmitted concurrently each on their respective wires. In an improved implementation based on registers, it may not be feasible to concurrently write to each of the register bits corresponding to the combination of signals (e.g., the bits may be scattered across multiple registers with multiple different addresses).
  • write commands can include committed and uncommitted writes. For example, an uncommitted command can be used to provisionally write, or queue a write, to an identified register address corresponding to the command.
  • Uncommitted writes can be held until the next committed write is received, at which point the values requested in the intervening uncommitted writes (e.g., since the last committed write) are written to their respective register bits together with the writing to the register requested in the committed write. For instance, an uncommitted write can be written to a buffer (that is flushed on a committed write) or to a shadow register to store the write until the next committed write is received and the status and control register is updated, while committed writes are written directly to the status and control register. In this manner, one or more uncommitted writes can be requested followed by a committed write to simultaneously write values to multiple different registers and bits so as to achieve alignment of the signals mapped to these bits.
  • 24 different signals can be mapped across three or more registers, such as registers A, B, and C.
  • three signals mapped to three respective bits in register A may need to be aligned with another signal mapped to a respective bit in register B, and two signals mapped to two respective bits in register C.
  • values can be written to the three bits in register A in a first write_uncommitted command, followed by a second write_uncommitted command to write the value to the bit in register B.
  • a write_committed command can be utilized to not only write to the values of the two bits in register C, but also to “commit” and cause the uncommitted writes to registers A and B to be performed simultaneously with the writes to register C and thereby cause all the values associated with the writes to registers A, B, and C to take effect in the same cycle.
  • read and read completion commands can be provided for accessing values written to particular status registers.
  • Acknowledgement (ACK) commands can also be defined, for instance, to indicate acknowledgement (i.e., to requesting computing block) that a committed or uncommitted write has been successful performed at a particular register.
  • Some implementations may omit support of a write_uncommitted command.
  • the registers of a particular computing block can be defined in such a way, with width and signal assignments, that signals understood to need alignment are mapped to bits in the same register or adjacent registers, thereby making it possible to write to each of the corresponding bits in the register in a single committed write.
  • Other potentially useful commands may include (but are not limited to) writes that span multiple adjacent registers, among other examples.
  • a signal diagram 900 is shown illustrating example signaling on an 8-bit status and control interface 930 of a MAC-PHY interface.
  • 8-bits of data can be sent during each clock (PCLK) 935 cycle, or unit interval (UI).
  • PCLK clock
  • UI unit interval
  • the data can be interpreted as the beginning of a status/control transaction on the interface.
  • a first one of the computing blocks can determine that a particular one of the defined status and control signals is to be sent to the other computing block as defined by the interface.
  • all status and control register transactions may contain a command.
  • the transaction can further include the associated register address.
  • the transaction can also contain data (identifying contents of the register).
  • the number of cycles it takes to transfer a transaction across the interface can be deduced from the command type.
  • the example transaction shown in FIG. 9 involves a write command 905 transferred across an 8-bit serial interface, assuming a 4-bit command, 32-bit registers, and 12-bit address space, that is completed in 6 cycles (or UIs). Other transactions in this configuration will be expected to take a respective number of UIs to complete.
  • some existing status and control signals are defined based not only on the designated wire on which they are transmitted but also the duration at which the signal is held on the corresponding wire. Accordingly, in an implementation that replaces at least some of these dedicated signaling wires with a register mapping (such as described above), it can be desirable to enable the distinguishing of signals that require 1-cycle assertions from signals that need to be held over multiple UIs (e.g., at a static value).
  • particular register bits or registers can be configured such that a value written to the bit is held at that value but then automatically returned to a default or un-asserted value (i.e., without requiring an explicit write transaction to return the value to the default (e.g., from “1” back to “0”).
  • a particular bit may be mapped to a particular signal that has a 1-cycle assertion, such that when a “1” is written to the particular bit, the “1” is interpreted as an instance of the particular signal.
  • the value can be automatically returned to “0”.
  • signals that are to be held at a value for more than one UI can be mapped to register bits that are configured to be held at that value until the expiration of a defined number of cycles or until the bit is overwritten, among other examples.
  • bits with similar configurations can be grouped within the same register or consecutively addressed registers. For instance, the bits within a given register can all be mapped to respective single cycle signal assertions, such that the register is processed to always return values back to a default for any bit in the register.
  • Other registers can be used to group other bits mapped to other signals with similarly equal signal assertion lengths, among other examples.
  • 1-cycle assertion type signals and static value type signals can be distinguished simply by grouping the two different signal types into different registers that are located in different address spaces or different address ranges of the same address space, and interpreting their values based on their respective address.
  • different signal types can be mapped to different registers and accessed using different write command types (e.g., a static-type write and a single-cycle write, etc.), among other examples.
  • a receiving computing block can perform 1020 actions such as changing the frequency of operation, changing the power state, changing transmitter coefficient settings, among other examples. Additional tasks can also be performed in connection with a status and control transaction over a reduced-pin, register-based interface. For instance, the computing block can detect that a particular register bit or associated signal is a 1-cycle or static value signal type and determine whether to automatically return the written-to bit to a default value or to use a particular type of write command to facilitate the accurate representation of the signal in the register.
  • a computing block can additionally identify boundaries between a first transaction and second transaction by identified an expected length of the first transaction based on the command utilized in the first transaction, among other example tasks.
  • a processing element refers to hardware or logic to support a software thread.
  • hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state.
  • a processing element in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code.
  • a physical processor or processor socket typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
  • a core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources.
  • a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources.
  • the line between the nomenclature of a hardware thread and core overlaps.
  • a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
  • some form of translation such as a binary translation
  • some form of translation such as a binary translation
  • the functional units illustrated in core 1101 are described in further detail below, as the units in core 1102 operate in a similar manner in the depicted embodiment.
  • core 1101 includes two hardware threads 1101 a and 1101 b , which may also be referred to as hardware thread slots 1101 a and 1101 b . Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1101 a , a second thread is associated with architecture state registers 1101 b , a third thread may be associated with architecture state registers 1102 a , and a fourth thread may be associated with architecture state registers 1102 b .
  • Some resources such as re-order buffers in reorder/retirement unit 1135 , ILTB 1120 , load/store buffers, and queues may be shared through partitioning.
  • Other resources such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1115 , execution unit(s) 1140 , and portions of out-of-order unit 1135 are potentially fully shared.
  • decoders 1125 include logic designed or adapted to recognize specific instructions, such as transactional instruction.
  • the architecture or core 1101 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
  • decoders 1126 in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1126 recognize a second ISA (either a subset of the first ISA or a distinct ISA).
  • allocator and renamer block 1130 includes an allocator to reserve resources, such as register files to store instruction processing results.
  • threads 1101 a and 1101 b are potentially capable of out-of-order execution, where allocator and renamer block 1430 also reserves other resources, such as reorder buffers to track instruction results.
  • Unit 1130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1100 .
  • Reorder/retirement unit 1135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
  • Scheduler and execution unit(s) block 1140 includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
  • cores 1101 and 1102 share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface 1110 .
  • higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s).
  • higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor 1100 —such as a second or third level data cache.
  • higher level cache is not so limited, as it may be associated with or include an instruction cache.
  • a trace cache a type of instruction cache—instead may be coupled after decoder 1125 to store recently decoded traces.
  • an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).
  • processor 1100 also includes on-chip interface module 1110 .
  • on-chip interface 1110 is to communicate with devices external to processor 1100 , such as system memory 1175 , a chipset (often including a memory controller hub to connect to memory 1175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit.
  • bus 1105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
  • Memory 1175 may be dedicated to processor 1100 or shared with other devices in a system. Common examples of types of memory 1175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1180 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
  • processor 1100 For example in one embodiment, a memory controller hub is on the same package and/or die with processor 1100 .
  • a portion of the core (an on-core portion) 1110 includes one or more controller(s) for interfacing with other devices such as memory 1175 or a graphics device 1180 .
  • the configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration).
  • on-chip interface 1110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1105 for off-chip communication.
  • processor 1100 is capable of executing a compiler, optimization, and/or translator code 1177 to compile, translate, and/or optimize application code 1176 to support the apparatus and methods described herein or to interface therewith.
  • a compiler often includes a program or set of programs to translate source text/code into target text/code.
  • compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation.
  • a compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.
  • a front-end i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place
  • a back-end i.e. generally where analysis, transformations, optimizations, and code generation takes place.
  • Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler.
  • reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler.
  • a compiler potentially inserts operations, calls, functions, etc.
  • compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime.
  • binary code (already compiled code) may be dynamically optimized during runtime.
  • the program code may include the dynamic optimization code, the binary code, or a combination thereof.
  • a translator such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.
  • multiprocessor system 1200 is a point-to-point interconnect system, and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250 .
  • processors 1270 and 1280 may be some version of a processor.
  • 1252 and 1254 are part of a serial, point-to-point coherent interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture.
  • QPI Quick Path Interconnect
  • processors 1270 , 1280 While shown with only two processors 1270 , 1280 , it is to be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.
  • Processors 1270 , 1280 each exchange information with a chipset 1290 via individual P-P interfaces 1252 , 1254 using point to point interface circuits 1276 , 1294 , 1286 , 1298 .
  • Chipset 1290 also exchanges information with a high-performance graphics circuit 1238 via an interface circuit 1292 along a high-performance graphics interconnect 1239 .
  • a shared cache (not shown) may be included in either processor or outside of both processors; yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
  • first bus 1216 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.
  • PCI Peripheral Component Interconnect
  • various I/O devices 1214 are coupled to first bus 1216 , along with a bus bridge 1218 which couples first bus 1216 to a second bus 1220 .
  • second bus 1220 includes a low pin count (LPC) bus.
  • LPC low pin count
  • Various devices are coupled to second bus 1220 including, for example, a keyboard and/or mouse 1222 , communication devices 1227 and a storage unit 1228 such as a disk drive or other mass storage device which often includes instructions/code and data 1230 , in one embodiment.
  • an audio I/O 1224 is shown coupled to second bus 1220 .
  • Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture of FIG. 12 , a system may implement a multi-drop bus or other such architecture.
  • an ARM-based design licensed from ARM Holdings, Ltd. or customer thereof, or their licensees or adopters may instead be present in other embodiments such as an Apple A5/A6 processor, a Qualcomm Snapdragon processor, or TI OMAP processor.
  • processors are modified and varied; however, they may support or recognize a specific instructions set that performs defined algorithms as set forth by the processor licensor.
  • the microarchitectural implementation may vary, but the architectural function of the processor is usually consistent. Certain details regarding the architecture and operation of processor in one implementation will be discussed further below to provide an illustrative example.
  • a mass storage may also couple to processor.
  • this mass storage may be implemented via a SSD.
  • the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities.
  • a flash device may be coupled to processor, e.g., via a serial peripheral interface (SPI). This flash device may provide for non-volatile storage of system software, including a basic input/output software (BIOS) as well as other firmware of the system.
  • BIOS basic input/output software
  • the display can be of different sizes, e.g., an 11.6′′ or a 13.3′′ screen, and may have a 16:9 aspect ratio, and at least 300 nits brightness.
  • the display may be of full high definition (HD) resolution (at least 1920 ⁇ 1080p), be compatible with an embedded display port (eDP), and be a low power panel with panel self refresh.
  • HD high definition
  • eDP embedded display port
  • the system may provide for a display multi-touch panel that is multi-touch capacitive and being at least 5 finger capable. And in some embodiments, the display may be 10 finger capable.
  • the touch screen is accommodated within a damage and scratch-resistant glass and coating (e.g., Gorilla Glass' or Gorilla Glass 2TM) for low friction to reduce “finger burn” and avoid “finger skipping”.
  • the touch panel in some implementations, has multi-touch functionality, such as less than 2 frames (30 Hz) per static view during pinch zoom, and single-touch functionality of less than 1 cm per frame (30 Hz) with 200 ms (lag on finger to pointer).
  • the display in some implementations, supports edge-to-edge glass with a minimal screen bezel that is also flush with the panel surface, and limited IO interference when using multi-touch.
  • the ambient light conditions in a location of the platform are determined and intensity of the display controlled accordingly.
  • power consumed in operating the display is reduced in certain light conditions.
  • security operations based on context information obtained from the sensors such as location information, it may be determined whether a user is allowed to access certain secure documents. For example, a user may be permitted to access such documents at a work place or a home location. However, the user is prevented from accessing such documents when the platform is present at a public location. This determination, in one embodiment, is based on location information, e.g., determined via a GPS sensor or camera recognition of landmarks.
  • Other security operations may include providing for pairing of devices within a close range of each other, e.g., a portable platform as described herein and a user's desktop computer, mobile telephone or so forth. Certain sharing, in some implementations, are realized via near field communication when these devices are so paired.
  • Responsiveness may also be enhanced using the sensor information. For example, even when a platform is in a low power state, the sensors may still be enabled to run at a relatively low frequency. Accordingly, any changes in a location of the platform, e.g., as determined by inertial sensors, GPS sensor, or so forth is determined. If no such changes have been registered, a faster connection to a previous wireless hub such as a Wi-FiTM access point or similar wireless enabler occurs, as there is no need to scan for available wireless network resources in this case. Thus, a greater level of responsiveness when waking from a low power state is achieved.
  • one or more infrared or other heat sensing elements may be present.
  • Such sensing elements may include multiple different elements working together, working in sequence, or both.
  • sensing elements include elements that provide initial sensing, such as light or sound projection, followed by sensing for gesture detection by, for example, an ultrasonic time of flight camera or a patterned light camera.
  • the system includes a light generator to produce an illuminated line.
  • this line provides a visual cue regarding a virtual boundary, namely an imaginary or virtual location in space, where action of the user to pass or break through the virtual boundary or plane is interpreted as an intent to engage with the computing system.
  • the illuminated line may change colors as the computing system transitions into different states with regard to the user. The illuminated line may be used to provide a visual cue for the user of a virtual boundary in space, and may be used by the system to determine transitions in state of the computer with regard to the user, including determining when the user wishes to engage with the computer.
  • the computer senses user position and operates to interpret the movement of a hand of the user through the virtual boundary as a gesture indicating an intention of the user to engage with the computer.
  • the light generated by the light generator may change, thereby providing visual feedback to the user that the user has entered an area for providing gestures to provide input to the computer.
  • Display screens may provide visual indications of transitions of state of the computing system with regard to a user.
  • a first screen is provided in a first state in which the presence of a user is sensed by the system, such as through use of one or more of the sensing elements.
  • the system acts to sense user identity, such as by facial recognition.
  • transition to a second screen may be provided in a second state, in which the computing system has recognized the user identity, where this second the screen provides visual feedback to the user that the user has transitioned into a new state.
  • Transition to a third screen may occur in a third state in which the user has confirmed recognition of the user.
  • the computing system may use a transition mechanism to determine a location of a virtual boundary for a user, where the location of the virtual boundary may vary with user and context.
  • the computing system may generate a light, such as an illuminated line, to indicate the virtual boundary for engaging with the system.
  • the computing system may be in a waiting state, and the light may be produced in a first color.
  • the computing system may detect whether the user has reached past the virtual boundary, such as by sensing the presence and movement of the user using sensing elements.
  • the computing system may then determine whether gesture movement is detected. If gesture movement is detected, the computing system may proceed with a gesture recognition process, which may include the use of data from a gesture data library, which may reside in memory in the computing device or may be otherwise accessed by the computing device.
  • a gesture recognition process may include the use of data from a gesture data library, which may reside in memory in the computing device or may be otherwise accessed by the computing device.
  • an internal lid/display open switch or sensor to indicate when the lid is closed/open, and can be used to place the system into Connected Standby or automatically wake from Connected Standby state.
  • Other system sensors can include ACPI sensors for internal processor, memory, and skin temperature monitoring to enable changes to processor and system operating states based on sensed parameters.
  • Various peripheral devices may couple to processor via a low pin count (LPC) interconnect.
  • various components can be coupled through an embedded controller.
  • Such components can include a keyboard (e.g., coupled via a PS2 interface), a fan, and a thermal sensor.
  • touch pad may also couple to EC via a PS2 interface.
  • a security processor such as a trusted platform module (TPM) in accordance with the Trusted Computing Group (TCG) TPM Specification Version 1.2, dated Oct. 2, 2003, may also couple to processor via this LPC interconnect.
  • TPM trusted platform module
  • TCG Trusted Computing Group
  • NFC unit Using the NFC unit described herein, users can bump devices side-to-side and place devices side-by-side for near field coupling functions (such as near field communication and wireless power transfer (WPT)) by leveraging the coupling between coils of one or more of such devices. More specifically, embodiments provide devices with strategically shaped, and placed, ferrite materials, to provide for better coupling of the coils. Each coil has an inductance associated with it, which can be chosen in conjunction with the resistive, capacitive, and other features of the system to enable a common resonant frequency for the system.
  • WPT wireless power transfer
  • additional wireless units can include other short range wireless engines including a WLAN unit and a Bluetooth unit.
  • WLAN unit Wi-FiTM communications in accordance with a given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard can be realized, while via Bluetooth unit, short range communications via a Bluetooth protocol can occur.
  • These units may communicate with processor via, e.g., a USB link or a universal asynchronous receiver transmitter (UART) link.
  • these units may couple to processor via an interconnect according to a Peripheral Component Interconnect ExpressTM (PCIeTM) protocol, e.g., in accordance with the PCI ExpressTM Specification Base Specification version 3.0 (published Jan. 17, 2007), or another such protocol such as a serial data input/output (SDIO) standard.
  • PCIeTM Peripheral Component Interconnect ExpressTM
  • SDIO serial data input/output
  • wireless wide area communications can occur via a WWAN unit which in turn may couple to a subscriber identity module (SIM).
  • SIM subscriber identity module
  • a GPS module may also be present.
  • WWAN unit and an integrated capture device such as a camera module may communicate via a given USB protocol such as a USB 2.0 or 3.0 link, or a UART or I 2 C protocol. Again the actual physical connection of these units can be via adaptation of a NGFF add-in card to an NGFF connector configured on the motherboard.
  • wireless functionality can be provided modularly, e.g., with a WiFiTM 802.11ac solution (e.g., add-in card that is backward compatible with IEEE 802.11abgn) with support for Windows 8 CS.
  • This card can be configured in an internal slot (e.g., via an NGFF adapter).
  • An additional module may provide for Bluetooth capability (e.g., Bluetooth 4.0 with backwards compatibility) as well as Intel® Wireless Display functionality.
  • NFC support may be provided via a separate device or multi-function device, and can be positioned as an example, in a front right portion of the chassis for easy access.
  • a still additional module may be a WWAN device that can provide support for 3G/4G/LTE and GPS.
  • This module can be implemented in an internal (e.g., NGFF) slot.
  • Integrated antenna support can be provided for WiFiTM, Bluetooth, WWAN, NFC and GPS, enabling seamless transition from WiFiTM to WWAN radios, wireless gigabit (WiGig) in accordance with the Wireless Gigabit Specification (July 2010), and vice versa.
  • WiGig wireless gigabit
  • an integrated camera can be incorporated in the lid.
  • this camera can be a high resolution camera, e.g., having a resolution of at least 2.0 megapixels (MP) and extending to 6.0 MP and beyond.
  • MP megapixels
  • an audio processor can be implemented via a digital signal processor (DSP), which may couple to processor via a high definition audio (HDA) link.
  • DSP may communicate with an integrated coder/decoder (CODEC) and amplifier that in turn may couple to output speakers which may be implemented within the chassis.
  • CODEC integrated coder/decoder
  • amplifier and CODEC can be coupled to receive audio inputs from a microphone which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system.
  • audio outputs can be provided from amplifier/CODEC to a headphone jack.
  • embodiments may provide a connected standby sleep state to maintain processor context using a dedicated power plane.
  • the connected standby sleep state facilitates processor wakeup using resources of a PCH which itself may be present in a package with the processor.
  • the connected standby sleep state facilitates sustaining processor architectural functions in the PCH until processor wakeup, this enabling turning off all of the unnecessary processor components that were previously left powered on during deep sleep states, including turning off all of the clocks.
  • the PCH contains a time stamp counter (TSC) and connected standby logic for controlling the system during the connected standby state.
  • TSC time stamp counter
  • the integrated voltage regulator for the sustain power plane may reside on the PCH as well.
  • Some implementations may provide a specific power management IC (PMIC) to control platform power.
  • PMIC power management IC
  • a system may see very low (e.g., less than 5%) battery degradation over an extended duration (e.g., 16 hours) when in a given standby state, such as when in a Win8 Connected Standby state.
  • a battery life exceeding, e.g., 9 hours may be realized (e.g., at 150 nits).
  • video playback a long battery life can be realized, e.g., full HD video playback can occur for a minimum of 6 hours.
  • a platform in one implementation may have an energy capacity of, e.g., 35 watt hours (Whr) for a Win8 CS using an SSD and (e.g.,) 40-44 Whr for Win8 CS using an HDD with a RST cache configuration.
  • Whr watt hours
  • a particular implementation may provide support for 15 W nominal CPU thermal design power (TDP), with a configurable CPU TDP of up to approximately 25 W TDP design point.
  • the platform may include minimal vents owing to the thermal features described above.
  • the platform is pillow-friendly (in that no hot air is blowing at the user).
  • Different maximum temperature points can be realized depending on the chassis material. In one implementation of a plastic chassis (at least having to lid or base portion of plastic), the maximum operating temperature can be 52 degrees Celsius (C). And for an implementation of a metal chassis, the maximum operating temperature can be 46° C.
  • a security module such as a TPM can be integrated into a processor or can be a discrete device such as a TPM 2.0 device.
  • an integrated security module also referred to as Platform Trust Technology (PTT)
  • BIOS/firmware can be enabled to expose certain hardware features for certain security features, including secure instructions, secure boot, Intel® Anti-Theft Technology, Intel® Identity Protection Technology, Intel® Trusted Execution Technology (TXT), and Intel® Manageability Engine Technology along with secure user interfaces such as a secure keyboard and display.
  • PTT Platform Trust Technology
  • BIOS/firmware can be enabled to expose certain hardware features for certain security features, including secure instructions, secure boot, Intel® Anti-Theft Technology, Intel® Identity Protection Technology, Intel® Trusted Execution Technology (TXT), and Intel® Manageability Engine Technology along with secure user interfaces such as a secure keyboard and display.
  • a design may go through various stages, from creation to simulation to fabrication.
  • Data representing a design may represent the design in a number of manners.
  • the hardware may be represented using a hardware description language or another functional description language.
  • a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
  • most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
  • the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
  • the data may be stored in any form of a machine readable medium.
  • a memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information.
  • an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made.
  • a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention.
  • phrase ‘to’ or ‘configured to,’ refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task.
  • an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task.
  • a logic gate may provide a 0 or a 1 during operation.
  • a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock.
  • use of the phrases ‘capable of/to,’ and or ‘operable to,’ in one embodiment refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner.
  • use of to, capable to, or operable to, in one embodiment refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
  • a value includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level.
  • a storage cell such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values.
  • the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.
  • states may be represented by values or portions of values.
  • a first value such as a logical one
  • a second value such as a logical zero
  • reset and set in one embodiment, refer to a default and an updated value or state, respectively.
  • a default value potentially includes a high logical value, i.e. reset
  • an updated value potentially includes a low logical value, i.e. set.
  • any combination of values may be utilized to represent any number of states.
  • Example 1 is an apparatus including a set of registers, and an interface of a computing block.
  • the computing block includes one of a physical layer block or a media access control layer block and the interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
  • Example 2 may include the subject matter of example 1, where the interface further includes one or more pins to transmit timing critical signals and one or more pins to receive timing critical signals.
  • Example 3 may include the subject matter of any one of examples 1-2, where the interface further includes a set of pins for communicating data signals.
  • Example 4 may include the subject matter of any one of examples 1-3, where values of the bits of the set of registers are to be used in lieu of the control and status signals.
  • Example 5 may include the subject matter of example 4, where the defined interface includes a PHY Interface for the Peripheral Component Interconnect Express (PCIe) architecture (PIPE) interface.
  • PCIe Peripheral Component Interconnect Express
  • Example 6 may include the subject matter of example 5, where the interface includes fewer pins than utilized in a particular PIPE specification.
  • Example 7 may include the subject matter of example 6, where the interface includes less than half the number of pins of the particular PIPE specification.
  • Example 8 may include the subject matter of any one of examples 4-7, where the particular signal includes a command and identifies an address of a particular one of the set of registers.
  • Example 14 may include the subject matter of example 13, where the command includes an uncommitted write and the values of the one or more bits are not to be modified until a subsequent instance of a committed write included in a subsequent transaction.
  • Example 15 may include the subject matter of any one of examples 12-13, where the code is further, when executed, to generate data to be sent over the particular portion of the interface to indicate an acknowledgement that the values of the one or more bits of the particular register have been modified.
  • Example 16 may include the subject matter of any one of examples 12-15, where the command is one of a plurality of supported commands including committed write commands, uncommitted write commands, read commands, read completions, and acknowledgement commands.
  • Example 17 may include the subject matter of any one of examples 12-15, where the code is further, when executed, to determine, from the command, a length of a transaction associated with the data.
  • Example 18 may include the subject matter of example 17, where the signal includes a first signal, the transaction includes a first transaction, and the code, when executed, is further to receive a second signal subsequent to the first signal, and determine that the second signal corresponds to a start of another transaction immediately subsequent to the first transaction based on the determined length of the transaction.
  • Example 21 is a system including means to perform the method of example 20.
  • Example 23 is a system including a physical layer computing block including a first set of registers, and a controller computing block, where the controller computing block includes a second set of registers and an interface to couple with the physical layer computing block.
  • the interface includes one or more pins to transmit asynchronous signals to the physical layer computing block, one or more pins to receive asynchronous signals from the physical layer computing block, and a set of pins including pins to communicate particular signals to the physical layer computing block to access the first set of registers and pins to receive signals from the physical layer computing block to permit access to the second set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the first and second sets of registers.
  • Example 24 may include the subject matter of example 23, where controller computing block includes a media access control layer computing block.
  • Example 25 may include the subject matter of example 24, where the physical layer computing block includes a Peripheral Component Interconnect Express (PCIe) physical layer.
  • PCIe Peripheral Component Interconnect Express
  • Example 26 may include the subject matter of example 24, where the physical layer computing block includes a Universal Serial Bus (USB) physical layer.
  • USB Universal Serial Bus
  • Example 27 may include the subject matter of example 24, where the physical layer computing block includes a Serial Advance Technology Attachment (SATA) physical layer.
  • SATA Serial Advance Technology Attachment
  • a non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system.
  • a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.
  • RAM random-access memory
  • SRAM static RAM
  • DRAM dynamic RAM
  • ROM magnetic or optical storage medium
  • flash memory devices electrical storage devices
  • optical storage devices e.g., optical storage devices
  • acoustical storage devices other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.
  • a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-

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US15/283,310 US10198394B2 (en) 2016-05-24 2016-10-01 Reduced pin count interface
PL20216390.3T PL3822800T3 (pl) 2016-05-24 2017-04-14 Interfejs o zmniejszonej liczbie pinów
PCT/US2017/027720 WO2017204922A1 (en) 2016-05-24 2017-04-14 Reduced pin count interface
CN202011576801.4A CN112579496A (zh) 2016-05-24 2017-04-14 减少引脚计数接口
EP20216390.3A EP3822800B1 (de) 2016-05-24 2017-04-14 Schnittstelle mit reduzierter pinanzahl
CN201780025415.6A CN109074341B (zh) 2016-05-24 2017-04-14 减少引脚计数接口
EP17803213.2A EP3465453B1 (de) 2016-05-24 2017-04-14 Schnittstelle mit reduzierter pinanzahl
US16/266,992 US10706003B2 (en) 2016-05-24 2019-02-04 Reduced pin count interface
US16/921,498 US11163717B2 (en) 2016-05-24 2020-07-06 Reduced pin count interface

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EP3465453A4 (de) 2019-12-25
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US20190303338A1 (en) 2019-10-03
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EP3465453B1 (de) 2023-07-19
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US10706003B2 (en) 2020-07-07
US11163717B2 (en) 2021-11-02
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