PL3822800T3 - Interfejs o zmniejszonej liczbie pinów - Google Patents
Interfejs o zmniejszonej liczbie pinówInfo
- Publication number
- PL3822800T3 PL3822800T3 PL20216390.3T PL20216390T PL3822800T3 PL 3822800 T3 PL3822800 T3 PL 3822800T3 PL 20216390 T PL20216390 T PL 20216390T PL 3822800 T3 PL3822800 T3 PL 3822800T3
- Authority
- PL
- Poland
- Prior art keywords
- interface
- pin number
- reduced pin
- reduced
- pin
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662340750P | 2016-05-24 | 2016-05-24 | |
| US15/283,310 US10198394B2 (en) | 2016-05-24 | 2016-10-01 | Reduced pin count interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| PL3822800T3 true PL3822800T3 (pl) | 2024-03-18 |
Family
ID=60411890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL20216390.3T PL3822800T3 (pl) | 2016-05-24 | 2017-04-14 | Interfejs o zmniejszonej liczbie pinów |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US10198394B2 (pl) |
| EP (2) | EP3822800B1 (pl) |
| CN (2) | CN112579496B (pl) |
| PL (1) | PL3822800T3 (pl) |
| WO (1) | WO2017204922A1 (pl) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391410B (zh) * | 2016-08-05 | 2020-02-07 | 威盛电子股份有限公司 | 桥接器 |
| TWI684869B (zh) * | 2016-11-23 | 2020-02-11 | 宸定科技股份有限公司 | 集線器 |
| US10963035B2 (en) * | 2017-10-11 | 2021-03-30 | Qualcomm Incorporated | Low power PCIe |
| US11134534B2 (en) * | 2017-10-23 | 2021-09-28 | Avago Technologies International Sales Pte. Limited | System on a chip with multiple cores |
| GB2571352B (en) * | 2018-02-27 | 2020-10-21 | Advanced Risc Mach Ltd | An apparatus and method for accessing metadata when debugging a device |
| US10817443B2 (en) * | 2018-03-28 | 2020-10-27 | SK Hynix Inc. | Configurable interface card |
| US10713209B2 (en) * | 2019-02-08 | 2020-07-14 | Intel Corporation | Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface |
| US11309013B2 (en) * | 2020-04-29 | 2022-04-19 | Samsung Electronics Co., Ltd. | Memory device for reducing resources used for training |
| US12271249B2 (en) | 2020-12-18 | 2025-04-08 | Intel Corporation | Advanced link power management for displayport |
| US12147288B2 (en) * | 2020-12-18 | 2024-11-19 | Intel Corporation | Display link power management using in-band low-frequency periodic signaling |
| US11755525B2 (en) * | 2021-04-14 | 2023-09-12 | SK Hynix Inc. | System including PIPE5 to PIPE4 converter and method thereof |
| CN114047954B (zh) * | 2021-11-08 | 2025-04-04 | 珠海全志科技股份有限公司 | 一种基于寄存器的数据处理方法及装置 |
| CN117539818B (zh) * | 2024-01-10 | 2024-04-02 | 富瀚微电子(成都)有限公司 | 基于phy模型的接口、集成接口的芯片及芯片仿真系统 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6795881B1 (en) * | 1999-12-23 | 2004-09-21 | Intel Corporation | Physical layer and data link interface with ethernet pre-negotiation |
| US6718417B1 (en) * | 1999-12-23 | 2004-04-06 | Intel Corporation | Physical layer and data link interface with flexible bus width |
| US6947956B2 (en) * | 2002-06-06 | 2005-09-20 | International Business Machines Corporation | Method and apparatus for selective caching of transactions in a computer system |
| US7219167B2 (en) * | 2003-09-25 | 2007-05-15 | Intel Corporation | Accessing configuration registers by automatically changing an index |
| US20050259685A1 (en) * | 2004-05-21 | 2005-11-24 | Luke Chang | Dual speed interface between media access control unit and physical unit |
| US7257655B1 (en) | 2004-10-13 | 2007-08-14 | Altera Corporation | Embedded PCI-Express implementation |
| EP2054810A2 (en) | 2006-08-18 | 2009-05-06 | Nxp, B.V. | Mac and phy interface arrangement |
| US7945741B2 (en) * | 2007-07-09 | 2011-05-17 | International Business Machines Corporation | Reservation required transactions |
| US7904623B2 (en) * | 2007-11-21 | 2011-03-08 | Microchip Technology Incorporated | Ethernet controller |
| KR20100083395A (ko) * | 2009-01-13 | 2010-07-22 | 삼성전자주식회사 | 병렬 인터페이싱 방법, 상기 방법을 수행하기 위한 장치들 |
| US20100177783A1 (en) * | 2009-01-13 | 2010-07-15 | Samsung Electronics Co., Ltd. | Interface systems between media access control (MAC) and physical layer (PHY) including parallel exchange of PHY register data and address information, and methods of operating the parallel exchange |
| US8438571B2 (en) * | 2010-02-24 | 2013-05-07 | International Business Machines Corporation | Thread speculative execution and asynchronous conflict |
| CN102291423B (zh) * | 2011-05-12 | 2013-08-14 | 福建星网锐捷网络有限公司 | 控制物理层芯片的方法及控制电路 |
| US8972640B2 (en) | 2012-06-27 | 2015-03-03 | Intel Corporation | Controlling a physical link of a first protocol using an extended capability structure of a second protocol |
| CN103164314B (zh) | 2013-02-22 | 2014-02-19 | 中国人民解放军国防科学技术大学 | 基于异步物理层接口的PCIe接口芯片硬件验证方法 |
| US9575552B2 (en) | 2013-04-17 | 2017-02-21 | Intel Corporation | Device, method and system for operation of a low power PHY with a PCIe protocol stack |
| KR101855603B1 (ko) * | 2013-10-30 | 2018-06-08 | 인텔 코포레이션 | 회로의 물리 유닛에서 지연을 측정하는 방법, 장치 및 시스템 |
| US9880965B2 (en) * | 2014-09-11 | 2018-01-30 | Qualcomm Incorporated | Variable frame length virtual GPIO with a modified UART interface |
| US9836420B2 (en) * | 2014-12-09 | 2017-12-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity |
| US10296356B2 (en) * | 2015-11-18 | 2019-05-21 | Oracle International Corporations | Implementation of reset functions in an SoC virtualized device |
-
2016
- 2016-10-01 US US15/283,310 patent/US10198394B2/en active Active
-
2017
- 2017-04-14 EP EP20216390.3A patent/EP3822800B1/en active Active
- 2017-04-14 PL PL20216390.3T patent/PL3822800T3/pl unknown
- 2017-04-14 CN CN202011576801.4A patent/CN112579496B/zh active Active
- 2017-04-14 EP EP17803213.2A patent/EP3465453B1/en active Active
- 2017-04-14 WO PCT/US2017/027720 patent/WO2017204922A1/en not_active Ceased
- 2017-04-14 CN CN201780025415.6A patent/CN109074341B/zh active Active
-
2019
- 2019-02-04 US US16/266,992 patent/US10706003B2/en active Active
-
2020
- 2020-07-06 US US16/921,498 patent/US11163717B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP3822800A2 (en) | 2021-05-19 |
| US20210056067A1 (en) | 2021-02-25 |
| US20170344512A1 (en) | 2017-11-30 |
| US10198394B2 (en) | 2019-02-05 |
| CN109074341A (zh) | 2018-12-21 |
| US10706003B2 (en) | 2020-07-07 |
| EP3822800A3 (en) | 2021-06-02 |
| US11163717B2 (en) | 2021-11-02 |
| CN112579496B (zh) | 2024-09-24 |
| EP3465453B1 (en) | 2023-07-19 |
| CN109074341B (zh) | 2023-04-18 |
| US20190303338A1 (en) | 2019-10-03 |
| EP3465453A1 (en) | 2019-04-10 |
| WO2017204922A1 (en) | 2017-11-30 |
| CN112579496A (zh) | 2021-03-30 |
| EP3465453A4 (en) | 2019-12-25 |
| EP3822800B1 (en) | 2023-10-25 |
| EP3822800C0 (en) | 2023-10-25 |
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