US10147814B2 - Lateral MOSFET - Google Patents

Lateral MOSFET Download PDF

Info

Publication number
US10147814B2
US10147814B2 US15/624,280 US201715624280A US10147814B2 US 10147814 B2 US10147814 B2 US 10147814B2 US 201715624280 A US201715624280 A US 201715624280A US 10147814 B2 US10147814 B2 US 10147814B2
Authority
US
United States
Prior art keywords
region
gate electrode
dielectric layer
isolation region
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/624,280
Other versions
US20170288054A1 (en
Inventor
Huei-Ru Liu
Chien-Chih Chou
Kong-Beng Thei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US15/624,280 priority Critical patent/US10147814B2/en
Publication of US20170288054A1 publication Critical patent/US20170288054A1/en
Priority to US16/177,808 priority patent/US10347757B2/en
Application granted granted Critical
Publication of US10147814B2 publication Critical patent/US10147814B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H01L29/7823—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H01L21/26513—
    • H01L21/28185—
    • H01L21/31111—
    • H01L21/32133—
    • H01L21/76224—
    • H01L21/823418—
    • H01L21/823437—
    • H01L21/823462—
    • H01L21/823481—
    • H01L27/088—
    • H01L29/0611—
    • H01L29/0653—
    • H01L29/0852—
    • H01L29/1083—
    • H01L29/402—
    • H01L29/4236—
    • H01L29/42368—
    • H01L29/66659—
    • H01L29/66681—
    • H01L29/7835—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, low on-resistance and high breakdown voltage of transistors are desirable for various high power applications.
  • MOSFET metal oxide semiconductor field effect transistors
  • MOSFETs are voltage controlled devices. When a control voltage is applied to the gate of a MOSFET and the control voltage is greater than the threshold of the MOSFET, a conductive channel is established between the drain and the source of the MOSFET. As a result, a current flows between the drain and the source of the MOSFET. On the other hand, when the control voltage is less than the threshold of the MOSFET, the MOSFET is turned off accordingly.
  • MOSFETs may include two major categories. One is n-channel MOSFETs; the other is p-channel MOSFETs. On the other hand, according to the structure difference, MOSFETs can be further divided into three sub-categories, planar MOSFETs, lateral diffused MOS (LDMOS) FETs and vertical diffused MOSFETs.
  • LDMOS lateral diffused MOS
  • the LDMOS transistor has more advantages.
  • the LDMOS transistor is capable of delivering more current per unit area because its asymmetric structure provides a short channel between the drain and the source of the LDMOS transistor.
  • FIG. 1 illustrates a cross sectional view of a semiconductor device including a lateral diffusion metal oxide semiconductor (LDMOS) transistor in accordance with an embodiment
  • LDMOS lateral diffusion metal oxide semiconductor
  • FIG. 2 illustrates a cross sectional view of a semiconductor device after a dielectric layer is deposited over the substrate in accordance with an embodiment
  • FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after a patterning process is applied to the semiconductor device in accordance with an embodiment
  • FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after an etching process is applied to the semiconductor device in accordance with an embodiment
  • FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to an isolation region of the semiconductor device in accordance with an embodiment
  • FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a high voltage gate dielectric layer is deposited over the substrate in accordance with an embodiment
  • FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a photoresist layer is deposited over the high voltage dielectric layer in accordance with an embodiment
  • FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after an etching process is applied to the high voltage gate dielectric layer in accordance with an embodiment
  • FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after an etching process is applied to the dielectric layer in accordance with an embodiment
  • FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after low voltage wells are formed in the low voltage region over the substrate in accordance with an embodiment
  • FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after a thin dielectric layer is formed over the low voltage region in accordance with an embodiment
  • FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a gate electrode layer is deposited over the substrate in accordance with an embodiment
  • FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment
  • FIG. 14 illustrates a cross sectional view of the semiconductor device shown in FIG. 13 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment
  • FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment
  • FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after high voltage drain/source regions and low voltage drain/source regions are formed in accordance with an embodiment.
  • MOSFET metal oxide semiconductor field effect transistor
  • FIG. 1 illustrates a cross sectional view of a semiconductor device including a lateral diffused metal oxide semiconductor (LDMOS) transistor in accordance with an embodiment.
  • the LDMOS transistor 100 is formed in a substrate 101 .
  • the substrate 101 may be formed of silicon, silicon germanium, silicon carbide or the like.
  • the wells are a first p-type well 112 , a first n-type well 114 and a second p-type well 116 .
  • the first n-type well 114 is disposed between the first p-type well 112 and the second p-type well 116 .
  • the first p-type well 112 and the second p-type well 116 are formed by implanting p-type doping materials such as boron, gallium, aluminum, indium, combinations thereof, or the like.
  • p-type doping materials such as boron, gallium, aluminum, indium, combinations thereof, or the like.
  • a p-type material such as boron may be implanted to a doping density of about 10 15 /cm 3 to 10 18 /cm 3 .
  • the first p-type well 112 and the second p-type well 116 can be formed by a diffusion process.
  • the first n-type well 114 are formed by implanting n-type doping materials such as phosphorus, arsenic, or the like.
  • n-type doping materials such as phosphorus, arsenic, or the like.
  • an n-type material such as phosphorus may be implanted to a doping density of about 10 15 /cm 3 to 10 18 /cm 3 .
  • the first n-type well 114 can be formed by a diffusion process.
  • the active regions include a first P+ region 152 , a first drain/source region 154 , a second drain/source region 156 and a second P+ region 158 .
  • the drain/source regions as well as the P+ regions may form a LDMOS transistor.
  • the wells e.g., p-type wells 112 , 116 and n-type well 116 ) shown in FIG. 1 are high voltage wells.
  • the LDMOS transistor 100 is a high voltage transistor.
  • Such a high voltage transistor can be used in medium voltage applications having a voltage rating range from about 2V to about 8V.
  • such a high voltage transistor can be sued in high voltage applications in a range from about 8V to about 400V.
  • such a high voltage transistor may be used in ultra-high voltage applications having a voltage rating greater than 400V.
  • the isolation regions shown in FIG. 1 provide isolation between active regions.
  • the isolation region 132 is formed at an interface in the substrate 101 between the first n-type well 112 and an exterior well or component.
  • the isolation region 134 is employed to isolate active regions (e.g., the first P+ region 152 and the first drain/source region 154 ) so as to prevent leakage current from flowing between adjacent active regions.
  • the isolation region 136 functions as a reduced surface field (RESURF) structure. More particularly, the isolation region 136 is an extension of the second drain/source region 156 . Such a dielectric extension of the second drain/source region 156 helps to achieve a uniform electric field distribution. As a result, the LDMOS transistor 100 may achieve both higher breakdown voltage and lower on resistance.
  • RESURF reduced surface field
  • a top surface of the isolation region 138 is lower than the top surfaces of other isolation regions (e.g., isolation regions 132 and 134 ).
  • the gap between the top surface of the isolation region 136 and the top surface of the substrate 101 is filled with a gate dielectric material.
  • the height of the gap is defined as H 2 as shown in FIG. 1 .
  • the detailed formation process of the gap between the top surface of the isolation region 136 and the top surface of the substrate 101 will be described below with respect to FIG. 5 .
  • the isolation region 138 is formed between the second drain/source region 156 and the second P+ region 158 .
  • the isolation region 140 is formed adjacent to the second P+ region 158 .
  • the function and structure of the isolation regions 138 and 140 are similar to the function and structure of isolation regions 134 and 132 respectively, and hence are not discussed in detail herein to avoid unnecessary repetition.
  • the isolation regions can be formed by various suitable fabrication techniques (e.g., thermally grown, deposited) and a variety of materials (e.g., silicon oxide, silicon nitride, any combinations thereof and/or the like).
  • the isolation region 104 may be fabricated by using a shallow trench isolation (STI) technique.
  • STI shallow trench isolation
  • a gate dielectric layer is deposited over the substrate 101 .
  • the detailed process of forming openings in the gate dielectric layer will be described below with respect to FIGS. 14-16 .
  • a gate electrode layer is formed over the substrate 101 .
  • the gate electrode layer may be divided into two portions, namely a first gate electrode layer 180 and a second gate electrode layer 182 .
  • the first gate electrode layer 180 is formed over a first gate dielectric region 176 , which is formed on the top surface of the substrate 101 .
  • the second gate electrode layer 182 is vertically aligned with the isolation region 136 . More particularly, due to the gap between the isolation region 136 and the top surface of the substrate 101 , there is a height difference between the top surface of the first gate electrode layer 180 and the top surface of the second gate electrode layer 182 .
  • the height difference shown in FIG. 1 is defined as H 1 .
  • H 1 is in a range from about 300 Angstroms to about 500 Angstroms.
  • FIG. 1 illustrates an ideal profile. H 1 and H 2 may vary after subsequent fabrication processes.
  • the height difference e.g., H 1 and H 2 ) shown in FIG. 1 is used to illustrate the inventive aspects of the various embodiments. The disclosure is not limited to any particular height difference.
  • the height of the first gate electrode layer 180 is similar to the height of conventional LDMOS transistors' gate electrode layer. Without having a recess at the isolation region 136 , the top surface of the second gate electrode layer 182 may be higher than the top surface of conventional LDMOS transistors' gate electrode layer. The protruded second electrode layer 182 may lead to a short between the second electrode layer 182 and subsequently formed metal layers (e.g., a first metal layer M 1 ).
  • the lower top surface of the second gate electrode 182 helps to prevent the second gate electrode layer 182 from shorting with subsequently formed metal layers (e.g., a first metal layer M 1 ).
  • subsequently formed metal layers e.g., a first metal layer M 1 .
  • the process margin of the LDMOS transistor 100 can be improved.
  • the improved process margin may further simplify the fabrication process and reduce the manufacturing cost of the LDMOS transistor 100 .
  • FIGS. 2-16 illustrates cross sectional views of intermediate steps of fabricating a semiconductor device including the LDMOS transistor shown in FIG. 1 in accordance with an embodiment.
  • FIG. 2 illustrates a cross sectional view of a semiconductor device after a dielectric layer is deposited over the substrate 101 in accordance with an embodiment.
  • the substrate 101 can be a semiconductor substrate, such as a bulk silicon substrate, a semiconductor on insulator (SOI), or the like.
  • the substrate 101 may include two regions, namely a high voltage region 110 and a low voltage region 150 .
  • the high voltage region 110 and the low voltage region 150 are demarcated in this example by two dashed rectangles.
  • the substrate 101 can be doped with various wells, such as according to appropriate high voltage and low voltage applications.
  • a first p-type well 112 , a first n-type well 114 and a second p-type well 116 are formed in the substrate 101 .
  • the high voltage region 110 is used to form a high voltage LDMOS transistor.
  • the low voltage region 150 is used to form a low voltage planar transistor. The detailed formation process of the high voltage LDMOS transistor and low voltage planar transistor will be described below with respect to FIGS. 3-16 .
  • a dielectric layer 190 is formed over the substrate 101 .
  • the dielectric layer 190 may be formed of various dielectric materials commonly used in integrated circuit fabrication.
  • the dielectric layer 190 may be formed of silicon dioxide, silicon nitride or a doped glass layer such as boron silicate glass and the like.
  • dielectric layer may be a silicon oxynitride layer, a polyamide layer, a low dielectric constant insulator and/or the like.
  • a combination of the foregoing dielectric materials may also be used to form the dielectric layer 190 .
  • the dielectric layer 190 may be formed of silicon nitride.
  • the silicon nitride layer 190 may be formed using suitable deposition techniques such as chemical vapor deposition (CVD) and/or the like.
  • FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after a patterning process is applied to the semiconductor device in accordance with an embodiment.
  • a photoresist mask layer 302 is deposited over the dielectric layer 190 through suitable deposition techniques. Furthermore, in consideration with the location of the opening in the dielectric layer 190 , suitable photolithography techniques are employed to form an opening 304 in the photoresist layer 302 .
  • FIG. 4 and FIG. 5 illustrate a high voltage gate oxide pre-clean process in accordance with an embodiment.
  • FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after an etching process is applied to the semiconductor device in accordance with an embodiment.
  • An etching process such as a reactive ion etch (RIE) or other dry etch, an anisotropic wet etch, or any other suitable anisotropic etch or patterning process, is performed to remove a portion of the dielectric layer 190 .
  • the remaining photo resist layer (not shown) may be removed by using a suitable ashing process.
  • FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to an isolation region of the semiconductor device in accordance with an embodiment.
  • a suitable etching technique such as a wet etching technique is applied to the upper portion of the isolation region 136 .
  • the dielectric material filled in the upper portion of the isolation region 136 has been removed.
  • a recess 502 is formed in the isolation region 136 .
  • the recess 502 is of a height H 2 .
  • H 2 is in a range from about 300 Angstroms to about 500 Angstroms.
  • FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a high voltage gate dielectric layer is deposited over the substrate in accordance with an embodiment.
  • the high voltage gate dielectric layer 602 is conformally deposited over the substrate 101 .
  • the high voltage gate dielectric layer 602 may be formed by using suitable deposition techniques such as CVD and/or the like.
  • the high voltage gate dielectric layer 602 may be formed of an oxide, such as silicon oxide, silicon nitride, composite oxide/nitride/oxide, the like, or a combination thereof. Other acceptable materials can be used for the high voltage gate dielectric layer 602 .
  • the thickness of the high voltage gate dielectric layer 602 is in a range from about 250 ⁇ to about 4,000 ⁇ .
  • the high voltage gate dielectric layer 602 is of an uneven surface (e.g., the region highlighted by a dashed rectangle 604 ) due to the recess 502 (shown in FIG. 5 ) in the isolation region 136 . It should further be noted that the high voltage dielectric layer 602 may be of a multiple layer structure. Alternatively, the high voltage dielectric layer 602 may comprise different dielectric materials.
  • FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a photoresist layer is deposited over the high voltage dielectric layer in accordance with an embodiment.
  • a photoresist layer 702 is deposited over the high voltage gate dielectric layer 602 using a spin on deposition and/or the like.
  • the photoresist layer 702 is exposed and developed such that only the portion over the high voltage region 110 remains.
  • the remaining photoresist layer 702 laterally extends from the isolation region 132 to the isolation region 140 .
  • the portion of the high voltage gate dielectric layer 602 over the low voltage region 150 is exposed by the photoresist layer 702 .
  • FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after an etching process is applied to the high voltage gate dielectric layer in accordance with an embodiment. An etching process is applied to the semiconductor device. As shown in FIG. 8 , the portion of the high voltage gate dielectric layer 602 over the low voltage region 150 has been removed as a result.
  • FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after an etching process is applied to the dielectric layer in accordance with an embodiment. An etching process is applied to the semiconductor device. As shown in FIG. 9 , the portion of the dielectric layer 190 over the low voltage region 150 has been removed as a result.
  • FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after low voltage wells are formed in the low voltage region over the substrate in accordance with an embodiment. Similar to the doping process shown in FIG. 2 , the low voltage region 150 may be doped with various wells. As shown in FIG. 10 , in the low voltage region 150 , n-type wells 122 , 126 and p-type well 124 are formed in a deep n-type well (DNW) 102 , which is formed in the substrate 101 .
  • DGW deep n-type well
  • FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after a thin dielectric layer is formed over the low voltage region in accordance with an embodiment.
  • the thin dielectric layer 1102 is a low voltage gate dielectric layer.
  • the low voltage gate dielectric layer 1102 is formed by using suitable fabrication techniques such as, thermal oxidation and/or the like.
  • the low voltage gate dielectric layer 1102 comprises an oxide, such as silicon oxide.
  • the low voltage gate dielectric layer 1102 can comprise hafnium oxide, tantalum oxide, aluminum oxide, the like, or a combination thereof.
  • the low voltage gate dielectric layer 1102 has a thickness in a range from about 15 ⁇ to about 150 ⁇ .
  • FIG. 11 shows the low voltage gate dielectric layer 1102 is a single layer, the low voltage gate dielectric layer 1102 can be of a multiple layer structure. Alternatively, the low voltage gate dielectric layer 1102 may comprise multiple dielectric materials. It should further be noted that the thickness of the high voltage gate dielectric layer 602 is greater than the thickness of the low voltage gate dielectric layer 1102 .
  • FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a gate electrode layer is deposited over the substrate in accordance with an embodiment.
  • the gate electrode layer 1202 may be formed of polysilicon.
  • the gate electrode layer 1202 may be formed of other commonly used conductive materials such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped poly-crystalline silicon, other conductive materials, combinations thereof, or the like.
  • a metal e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium
  • a metal silicide e.g., titanium
  • the gate electrode layer is deposited over the high voltage gate dielectric layer 602 and low voltage gate dielectric layer 1102 using suitable deposition techniques such as CVD and/or the like.
  • the gate electrode layer 1202 can subsequently be used to form gate electrodes for transistor devices in the high voltage region 110 and transistor devices in the low voltage region 150 .
  • a bottom anti-reflection coating (BARC) layer 1204 is formed over the gate electrode layer 1202 .
  • the BARC layer 1204 may be formed of a nitride material, an organic material, an oxide material and the like.
  • the BARC layer 1204 may be formed using suitable techniques such as CVD and/or the like.
  • the gate electrode layer 1202 over the high voltage region 110 is of an uneven surface due to the uneven surface of the high voltage gate electric layer shown in FIG. 6 .
  • FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment.
  • the gate electrode layer 1202 is patterned to form a high voltage gate electrode layer including a first portion 180 and a second portion 182 , a low voltage gate electrode 186 and a dummy structure 184 at a boundary between the high voltage region 110 and the low voltage region 150 .
  • the high voltage gate electrode is of an even surface.
  • the top surface of the second portion 182 is lower than the top surface of the first portion 180 . Such a lower top surface helps to prevent a short between the high voltage gate electrode and subsequently formed metal layers (not shown).
  • FIG. 14 illustrates a cross sectional view of the semiconductor device shown in FIG. 13 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment.
  • the high voltage gate dielectric layer 602 may be patterned, such as by anisotropically etching to form the openings 1402 , 1404 , 1406 and 1408 as illustrated in FIG. 14 .
  • FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment.
  • an anisotropic etching process is applied to the openings 1402 , 1404 , 1406 and 1408 in accordance with an embodiment.
  • the dielectric materials at the bottoms of the openings 1402 , 1404 , 1406 and 1408 have been removed.
  • a BARC removal process may be applied to the semiconductor device when the etching process is applied to the top surface of the semiconductor device.
  • the BARC layer may be removed by using suitable etching techniques including dry etching, wet etching, a combination thereof and/or the like.
  • FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after high voltage drain/source regions and low voltage drain/source regions are formed in accordance with an embodiment.
  • the drain/source regions 154 and 156 may be formed over the substrate 101 on opposing sides of the isolation region 136 .
  • the first P+ region 152 is formed between the isolation region 132 and isolation region 134 .
  • the second P+ region 158 is formed between the isolation region 138 and the isolation region 140 .
  • the drain/source regions may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like.
  • the drain/source regions may be formed by implanting appropriate n-type dopants such as phosphorus, arsenic, or the like.
  • the doping density of the drain/source regions is in a range from about 10 19 /cm 3 to about 5 ⁇ 10 19 /cm 3 . It should be noted while FIG. 16 illustrates the drain/source regions are n-type, the drain/source regions may be p-type depending on different design needs.
  • the drain/source regions may be formed over the substrate 101 .
  • the drain/source regions e.g., drain/source region 164
  • the drain/source regions may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like.
  • the drain/source regions e.g., drain/source region 164
  • the drain/source regions may be formed by implanting appropriate n-type dopants such as phosphorus, arsenic, or the like.
  • the doping density of the drain/source regions is in a range from about 10 19 /cm 3 to about 5 ⁇ 10 19 /cm 3 . It should be noted while FIG. 16 illustrates the low voltage drain/source regions are n-type, the low voltage drain/source regions may be p-type depending on different design needs.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Description

PRIORITY CLAIM AND CROSS-REFERENCE
This application is a continuation of U.S. patent application Ser. No. 15/174,305, entitled “Lateral MOSFET”, filed on Jun. 6, 2016, which is a divisional of U.S. patent application Ser. No. 13/666,632, entitled “Lateral MOSFET,” filed on Nov. 1, 2012, now U.S. Pat. No. 9,362,272, issued on Jun. 7, 2016, which applications are incorporated herein by reference in their entirety.
BACKGROUND
The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, low on-resistance and high breakdown voltage of transistors are desirable for various high power applications.
As semiconductor technologies evolve, metal oxide semiconductor field effect transistors (MOSFET) have been widely used in today's integrated circuits. MOSFETs are voltage controlled devices. When a control voltage is applied to the gate of a MOSFET and the control voltage is greater than the threshold of the MOSFET, a conductive channel is established between the drain and the source of the MOSFET. As a result, a current flows between the drain and the source of the MOSFET. On the other hand, when the control voltage is less than the threshold of the MOSFET, the MOSFET is turned off accordingly.
According to the polarity difference, MOSFETs may include two major categories. One is n-channel MOSFETs; the other is p-channel MOSFETs. On the other hand, according to the structure difference, MOSFETs can be further divided into three sub-categories, planar MOSFETs, lateral diffused MOS (LDMOS) FETs and vertical diffused MOSFETs.
In comparison with other MOSFETs, the LDMOS transistor has more advantages. For example, the LDMOS transistor is capable of delivering more current per unit area because its asymmetric structure provides a short channel between the drain and the source of the LDMOS transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a cross sectional view of a semiconductor device including a lateral diffusion metal oxide semiconductor (LDMOS) transistor in accordance with an embodiment;
FIG. 2 illustrates a cross sectional view of a semiconductor device after a dielectric layer is deposited over the substrate in accordance with an embodiment;
FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after a patterning process is applied to the semiconductor device in accordance with an embodiment;
FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after an etching process is applied to the semiconductor device in accordance with an embodiment;
FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to an isolation region of the semiconductor device in accordance with an embodiment;
FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a high voltage gate dielectric layer is deposited over the substrate in accordance with an embodiment;
FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a photoresist layer is deposited over the high voltage dielectric layer in accordance with an embodiment;
FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after an etching process is applied to the high voltage gate dielectric layer in accordance with an embodiment;
FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after an etching process is applied to the dielectric layer in accordance with an embodiment;
FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after low voltage wells are formed in the low voltage region over the substrate in accordance with an embodiment;
FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after a thin dielectric layer is formed over the low voltage region in accordance with an embodiment;
FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a gate electrode layer is deposited over the substrate in accordance with an embodiment;
FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment;
FIG. 14 illustrates a cross sectional view of the semiconductor device shown in FIG. 13 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment;
FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment; and
FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after high voltage drain/source regions and low voltage drain/source regions are formed in accordance with an embodiment.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the disclosure, and do not limit the scope of the disclosure.
The present disclosure will be described with respect to embodiments in a specific context, a lateral metal oxide semiconductor field effect transistor (MOSFET). The embodiments of the disclosure may also be applied, however, to a variety of metal oxide semiconductor transistors. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.
FIG. 1 illustrates a cross sectional view of a semiconductor device including a lateral diffused metal oxide semiconductor (LDMOS) transistor in accordance with an embodiment. The LDMOS transistor 100 is formed in a substrate 101. In accordance with an embodiment, the substrate 101 may be formed of silicon, silicon germanium, silicon carbide or the like.
As shown in FIG. 1, there may be three wells formed in the substrate 101. The wells are a first p-type well 112, a first n-type well 114 and a second p-type well 116. In particular, the first n-type well 114 is disposed between the first p-type well 112 and the second p-type well 116.
The first p-type well 112 and the second p-type well 116 are formed by implanting p-type doping materials such as boron, gallium, aluminum, indium, combinations thereof, or the like. In accordance with an embodiment, a p-type material such as boron may be implanted to a doping density of about 1015/cm3 to 1018/cm3. Alternatively, the first p-type well 112 and the second p-type well 116 can be formed by a diffusion process.
Likewise, the first n-type well 114 are formed by implanting n-type doping materials such as phosphorus, arsenic, or the like. In accordance with an embodiment, an n-type material such as phosphorus may be implanted to a doping density of about 1015/cm3 to 1018/cm3. Alternatively, the first n-type well 114 can be formed by a diffusion process.
As shown in FIG. 1, there may be a plurality of isolation regions and active regions formed in the substrate 101. The active regions include a first P+ region 152, a first drain/source region 154, a second drain/source region 156 and a second P+ region 158. The drain/source regions as well as the P+ regions may form a LDMOS transistor.
In accordance with an embodiment, the wells (e.g., p- type wells 112, 116 and n-type well 116) shown in FIG. 1 are high voltage wells. As a result, the LDMOS transistor 100 is a high voltage transistor. Such a high voltage transistor can be used in medium voltage applications having a voltage rating range from about 2V to about 8V. Alternatively, such a high voltage transistor can be sued in high voltage applications in a range from about 8V to about 400V. Furthermore, such a high voltage transistor may be used in ultra-high voltage applications having a voltage rating greater than 400V.
The isolation regions shown in FIG. 1 provide isolation between active regions. For example, the isolation region 132 is formed at an interface in the substrate 101 between the first n-type well 112 and an exterior well or component. The isolation region 134 is employed to isolate active regions (e.g., the first P+ region 152 and the first drain/source region 154) so as to prevent leakage current from flowing between adjacent active regions.
The isolation region 136 functions as a reduced surface field (RESURF) structure. More particularly, the isolation region 136 is an extension of the second drain/source region 156. Such a dielectric extension of the second drain/source region 156 helps to achieve a uniform electric field distribution. As a result, the LDMOS transistor 100 may achieve both higher breakdown voltage and lower on resistance.
It should be noted that a top surface of the isolation region 138 is lower than the top surfaces of other isolation regions (e.g., isolation regions 132 and 134). The gap between the top surface of the isolation region 136 and the top surface of the substrate 101 is filled with a gate dielectric material. The height of the gap is defined as H2 as shown in FIG. 1. The detailed formation process of the gap between the top surface of the isolation region 136 and the top surface of the substrate 101 will be described below with respect to FIG. 5.
The isolation region 138 is formed between the second drain/source region 156 and the second P+ region 158. The isolation region 140 is formed adjacent to the second P+ region 158. The function and structure of the isolation regions 138 and 140 are similar to the function and structure of isolation regions 134 and 132 respectively, and hence are not discussed in detail herein to avoid unnecessary repetition.
The isolation regions (e.g., isolation regions 132, 134, 136, 138 and 140) can be formed by various suitable fabrication techniques (e.g., thermally grown, deposited) and a variety of materials (e.g., silicon oxide, silicon nitride, any combinations thereof and/or the like). In this embodiment, the isolation region 104 may be fabricated by using a shallow trench isolation (STI) technique.
A gate dielectric layer is deposited over the substrate 101. In order to form active regions through ion implantation techniques, there may be a plurality of openings formed between two adjacent gate dielectric blocks. For example, in order to form the first P+ region 152, there is an opening between a first gate dielectric block 172 and a second gate dielectric block 174. The detailed process of forming openings in the gate dielectric layer will be described below with respect to FIGS. 14-16.
A gate electrode layer is formed over the substrate 101. As shown in FIG. 1, the gate electrode layer may be divided into two portions, namely a first gate electrode layer 180 and a second gate electrode layer 182. As shown in FIG. 1, the first gate electrode layer 180 is formed over a first gate dielectric region 176, which is formed on the top surface of the substrate 101. The second gate electrode layer 182 is vertically aligned with the isolation region 136. More particularly, due to the gap between the isolation region 136 and the top surface of the substrate 101, there is a height difference between the top surface of the first gate electrode layer 180 and the top surface of the second gate electrode layer 182. The height difference shown in FIG. 1 is defined as H1. In accordance with an embodiment, H1 is in a range from about 300 Angstroms to about 500 Angstroms.
One skilled in the art will recognize that FIG. 1 illustrates an ideal profile. H1 and H2 may vary after subsequent fabrication processes. The height difference (e.g., H1 and H2) shown in FIG. 1 is used to illustrate the inventive aspects of the various embodiments. The disclosure is not limited to any particular height difference.
It should be noted that the height of the first gate electrode layer 180 is similar to the height of conventional LDMOS transistors' gate electrode layer. Without having a recess at the isolation region 136, the top surface of the second gate electrode layer 182 may be higher than the top surface of conventional LDMOS transistors' gate electrode layer. The protruded second electrode layer 182 may lead to a short between the second electrode layer 182 and subsequently formed metal layers (e.g., a first metal layer M1).
One advantageous feature of having the second gate electrode layer 182 with a lower top surface is that the lower top surface of the second gate electrode 182 helps to prevent the second gate electrode layer 182 from shorting with subsequently formed metal layers (e.g., a first metal layer M1). As a result, the process margin of the LDMOS transistor 100 can be improved. The improved process margin may further simplify the fabrication process and reduce the manufacturing cost of the LDMOS transistor 100.
FIGS. 2-16 illustrates cross sectional views of intermediate steps of fabricating a semiconductor device including the LDMOS transistor shown in FIG. 1 in accordance with an embodiment. FIG. 2 illustrates a cross sectional view of a semiconductor device after a dielectric layer is deposited over the substrate 101 in accordance with an embodiment. The substrate 101 can be a semiconductor substrate, such as a bulk silicon substrate, a semiconductor on insulator (SOI), or the like.
The substrate 101 may include two regions, namely a high voltage region 110 and a low voltage region 150. The high voltage region 110 and the low voltage region 150 are demarcated in this example by two dashed rectangles. The substrate 101 can be doped with various wells, such as according to appropriate high voltage and low voltage applications. In the high voltage region 110, a first p-type well 112, a first n-type well 114 and a second p-type well 116 are formed in the substrate 101.
The high voltage region 110 is used to form a high voltage LDMOS transistor. Likewise, the low voltage region 150 is used to form a low voltage planar transistor. The detailed formation process of the high voltage LDMOS transistor and low voltage planar transistor will be described below with respect to FIGS. 3-16.
As shown in FIG. 2, a dielectric layer 190 is formed over the substrate 101. The dielectric layer 190 may be formed of various dielectric materials commonly used in integrated circuit fabrication. For example, the dielectric layer 190 may be formed of silicon dioxide, silicon nitride or a doped glass layer such as boron silicate glass and the like. Alternatively, dielectric layer may be a silicon oxynitride layer, a polyamide layer, a low dielectric constant insulator and/or the like. In addition, a combination of the foregoing dielectric materials may also be used to form the dielectric layer 190.
In accordance with an embodiment, the dielectric layer 190 may be formed of silicon nitride. The silicon nitride layer 190 may be formed using suitable deposition techniques such as chemical vapor deposition (CVD) and/or the like.
FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after a patterning process is applied to the semiconductor device in accordance with an embodiment. In accordance with an embodiment, a photoresist mask layer 302 is deposited over the dielectric layer 190 through suitable deposition techniques. Furthermore, in consideration with the location of the opening in the dielectric layer 190, suitable photolithography techniques are employed to form an opening 304 in the photoresist layer 302.
FIG. 4 and FIG. 5 illustrate a high voltage gate oxide pre-clean process in accordance with an embodiment. FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after an etching process is applied to the semiconductor device in accordance with an embodiment. An etching process, such as a reactive ion etch (RIE) or other dry etch, an anisotropic wet etch, or any other suitable anisotropic etch or patterning process, is performed to remove a portion of the dielectric layer 190. The remaining photo resist layer (not shown) may be removed by using a suitable ashing process.
FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to an isolation region of the semiconductor device in accordance with an embodiment. A suitable etching technique such as a wet etching technique is applied to the upper portion of the isolation region 136. As a result, the dielectric material filled in the upper portion of the isolation region 136 has been removed. By controlling the strength and direction of the etching process, a recess 502 is formed in the isolation region 136. In accordance with an embodiment, the recess 502 is of a height H2. H2 is in a range from about 300 Angstroms to about 500 Angstroms.
FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a high voltage gate dielectric layer is deposited over the substrate in accordance with an embodiment. The high voltage gate dielectric layer 602 is conformally deposited over the substrate 101. The high voltage gate dielectric layer 602 may be formed by using suitable deposition techniques such as CVD and/or the like.
In accordance with various embodiments, the high voltage gate dielectric layer 602 may be formed of an oxide, such as silicon oxide, silicon nitride, composite oxide/nitride/oxide, the like, or a combination thereof. Other acceptable materials can be used for the high voltage gate dielectric layer 602. The thickness of the high voltage gate dielectric layer 602 is in a range from about 250 Å to about 4,000 Å.
It should be noted that the high voltage gate dielectric layer 602 is of an uneven surface (e.g., the region highlighted by a dashed rectangle 604) due to the recess 502 (shown in FIG. 5) in the isolation region 136. It should further be noted that the high voltage dielectric layer 602 may be of a multiple layer structure. Alternatively, the high voltage dielectric layer 602 may comprise different dielectric materials.
FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a photoresist layer is deposited over the high voltage dielectric layer in accordance with an embodiment. A photoresist layer 702 is deposited over the high voltage gate dielectric layer 602 using a spin on deposition and/or the like. The photoresist layer 702 is exposed and developed such that only the portion over the high voltage region 110 remains. The remaining photoresist layer 702 laterally extends from the isolation region 132 to the isolation region 140. The portion of the high voltage gate dielectric layer 602 over the low voltage region 150 is exposed by the photoresist layer 702.
FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after an etching process is applied to the high voltage gate dielectric layer in accordance with an embodiment. An etching process is applied to the semiconductor device. As shown in FIG. 8, the portion of the high voltage gate dielectric layer 602 over the low voltage region 150 has been removed as a result.
FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after an etching process is applied to the dielectric layer in accordance with an embodiment. An etching process is applied to the semiconductor device. As shown in FIG. 9, the portion of the dielectric layer 190 over the low voltage region 150 has been removed as a result.
FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after low voltage wells are formed in the low voltage region over the substrate in accordance with an embodiment. Similar to the doping process shown in FIG. 2, the low voltage region 150 may be doped with various wells. As shown in FIG. 10, in the low voltage region 150, n- type wells 122, 126 and p-type well 124 are formed in a deep n-type well (DNW) 102, which is formed in the substrate 101.
FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after a thin dielectric layer is formed over the low voltage region in accordance with an embodiment. The thin dielectric layer 1102 is a low voltage gate dielectric layer. The low voltage gate dielectric layer 1102 is formed by using suitable fabrication techniques such as, thermal oxidation and/or the like.
In accordance with an embodiment, the low voltage gate dielectric layer 1102 comprises an oxide, such as silicon oxide. Alternatively, the low voltage gate dielectric layer 1102 can comprise hafnium oxide, tantalum oxide, aluminum oxide, the like, or a combination thereof. The low voltage gate dielectric layer 1102 has a thickness in a range from about 15 Å to about 150 Å.
It should be noted while FIG. 11 shows the low voltage gate dielectric layer 1102 is a single layer, the low voltage gate dielectric layer 1102 can be of a multiple layer structure. Alternatively, the low voltage gate dielectric layer 1102 may comprise multiple dielectric materials. It should further be noted that the thickness of the high voltage gate dielectric layer 602 is greater than the thickness of the low voltage gate dielectric layer 1102.
FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a gate electrode layer is deposited over the substrate in accordance with an embodiment. The gate electrode layer 1202 may be formed of polysilicon. Alternatively, the gate electrode layer 1202 may be formed of other commonly used conductive materials such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped poly-crystalline silicon, other conductive materials, combinations thereof, or the like.
The gate electrode layer is deposited over the high voltage gate dielectric layer 602 and low voltage gate dielectric layer 1102 using suitable deposition techniques such as CVD and/or the like. The gate electrode layer 1202 can subsequently be used to form gate electrodes for transistor devices in the high voltage region 110 and transistor devices in the low voltage region 150.
A bottom anti-reflection coating (BARC) layer 1204 is formed over the gate electrode layer 1202. The BARC layer 1204 may be formed of a nitride material, an organic material, an oxide material and the like. The BARC layer 1204 may be formed using suitable techniques such as CVD and/or the like.
It should be noted that the gate electrode layer 1202 over the high voltage region 110 is of an uneven surface due to the uneven surface of the high voltage gate electric layer shown in FIG. 6.
FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment. The gate electrode layer 1202 is patterned to form a high voltage gate electrode layer including a first portion 180 and a second portion 182, a low voltage gate electrode 186 and a dummy structure 184 at a boundary between the high voltage region 110 and the low voltage region 150. The high voltage gate electrode is of an even surface. In particular, the top surface of the second portion 182 is lower than the top surface of the first portion 180. Such a lower top surface helps to prevent a short between the high voltage gate electrode and subsequently formed metal layers (not shown).
FIG. 14 illustrates a cross sectional view of the semiconductor device shown in FIG. 13 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment. The high voltage gate dielectric layer 602 may be patterned, such as by anisotropically etching to form the openings 1402, 1404, 1406 and 1408 as illustrated in FIG. 14.
FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after an etching process is applied to the top surface of the semiconductor device in accordance with an embodiment. In order to apply an ion implantation process to the high voltage region 110, an anisotropic etching process is applied to the openings 1402, 1404, 1406 and 1408 in accordance with an embodiment. As a result, the dielectric materials at the bottoms of the openings 1402, 1404, 1406 and 1408 have been removed.
A BARC removal process may be applied to the semiconductor device when the etching process is applied to the top surface of the semiconductor device. The BARC layer may be removed by using suitable etching techniques including dry etching, wet etching, a combination thereof and/or the like.
FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after high voltage drain/source regions and low voltage drain/source regions are formed in accordance with an embodiment. In high voltage region 110, the drain/ source regions 154 and 156 may be formed over the substrate 101 on opposing sides of the isolation region 136. The first P+ region 152 is formed between the isolation region 132 and isolation region 134. The second P+ region 158 is formed between the isolation region 138 and the isolation region 140.
In accordance with an embodiment, when the substrate 101 is an n-type substrate, the drain/source regions (e.g., drain/source region 154) may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like. Alternatively, in an embodiment in which the substrate 101 is a p-type substrate, the drain/source regions (e.g., drain/source region 154) may be formed by implanting appropriate n-type dopants such as phosphorus, arsenic, or the like. In accordance with an embodiment, the doping density of the drain/source regions (e.g., drain/source region 154) is in a range from about 1019/cm3 to about 5×1019/cm3. It should be noted while FIG. 16 illustrates the drain/source regions are n-type, the drain/source regions may be p-type depending on different design needs.
In the low voltage region 150, the drain/source regions (e.g., N+ regions 164 and 166) may be formed over the substrate 101. In accordance with an embodiment, when the substrate 101 is an n-type substrate, the drain/source regions (e.g., drain/source region 164) may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like. Alternatively, in an embodiment in which the substrate 101 is a p-type substrate, the drain/source regions (e.g., drain/source region 164) may be formed by implanting appropriate n-type dopants such as phosphorus, arsenic, or the like. In accordance with an embodiment, the doping density of the drain/source regions (e.g., drain/source region 164) is in a range from about 1019/cm3 to about 5×1019/cm3. It should be noted while FIG. 16 illustrates the low voltage drain/source regions are n-type, the low voltage drain/source regions may be p-type depending on different design needs.
Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

What is claimed is:
1. A method comprising:
forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate;
removing an upper portion of the first isolation region to form a recess;
depositing a gate dielectric layer over the first isolation region;
forming a gate electrode layer over the gate dielectric layer; and
patterning the gate electrode layer to form a gate electrode region, wherein:
a first portion of the gate electrode region is vertically aligned with the first isolation region; and
a second portion of the gate electrode region is formed over the substrate, and wherein a top surface of the first portion is lower than a top surface of the second portion.
2. The method of claim 1, further comprising:
depositing a dielectric layer on the top surface of the substrate, wherein the top surface of the first isolation region is covered by the dielectric layer;
patterning the dielectric layer to expose the top surface of the first isolation region; and
removing the upper portion of the first isolation region through an etching process.
3. The method of claim 2, wherein:
after removing the upper portion of the first isolation region through the etching process, a height of the recess is in a range from about 300 Angstroms to about 500 Angstroms.
4. The method of claim 2, further comprising:
patterning the gate dielectric layer to form a first opening and a second opening in the gate dielectric layer, wherein the first opening and the second opening are on opposite sides of the first isolation region.
5. The method of claim 4, further comprising:
after patterning the gate dielectric layer to form the first opening and the second opening, performing an etching process on the dielectric layer to remove the dielectric layer at bottoms of the first opening and the second opening to expose the top surface of the substrate.
6. The method of claim 5, further comprising:
after exposing the top surface of the substrate, forming a first drain/source region through a first ion implantation process, wherein an edge of the first drain/source region is vertically aligned with an edge of the first opening; and
forming a second drain/source region through a second ion implantation process, wherein an edge of the second drain/source region is vertically aligned with an edge of the second opening.
7. The method of claim 1, wherein:
the gate dielectric layer is conformally deposited over the substrate.
8. The method of claim 7, wherein:
the gate dielectric layer has an uneven surface.
9. A method comprising:
forming a plurality of isolation regions in a substrate, wherein a first isolation region is in a high voltage region of the substrate, a second isolation region and a third isolation region are in a low voltage region of the substrate, and a fourth isolation region is in both the high voltage region and the low voltage region of the substrate;
removing an upper portion of the first isolation region to form a trench;
depositing a high voltage gate dielectric layer over the substrate;
removing the high voltage gate dielectric layer over the low voltage region;
depositing a low voltage gate dielectric layer over the low voltage region;
depositing a gate electrode layer over the high voltage gate dielectric layer and the low voltage gate dielectric layer; and
patterning the gate electrode layer to form a first gate electrode region over the first isolation region, a second gate electrode region between the second isolation region and the third isolation region, and a third gate electrode region over the fourth isolation region, wherein a bottom surface of the first gate electrode region is higher than a bottom surface of the second gate electrode region.
10. The method of claim 9, wherein:
the third gate electrode region includes a first portion over the high voltage gate dielectric layer and a second portion in contact with the fourth isolation region, and wherein a bottom of the second portion of the third gate electrode region is lower than a bottom of the first portion of the third gate electrode region.
11. The method of claim 9, further comprising:
forming a fifth isolation region and a sixth isolation region in the high voltage region, wherein the fourth isolation region and the fifth isolation region are on opposite sides of the first isolation region.
12. The method of claim 11, further comprising:
forming a first drain/source region between the fifth isolation region and the first gate electrode region; and
forming a second drain/source region between the sixth isolation region and the first gate electrode region.
13. The method of claim 9, wherein:
the first gate electrode region includes a first portion formed over the first isolation region and a second portion formed over the substrate, and wherein a bottom of the first portion of the first gate electrode region is lower than a bottom of the second portion of the first gate electrode region.
14. The method of claim 9, wherein:
a portion of the high voltage gate dielectric layer is below a top surface of the substrate.
15. A method comprising:
forming a first isolation region in a high voltage region of a substrate and a second isolation region at a boundary between the high voltage region and a low voltage region, wherein a top surface of the first isolation region is level with a top surface of the second isolation region;
removing an upper portion of the first isolation region to form a recess;
depositing a gate dielectric layer over the first isolation region and the second isolation region;
forming a gate electrode layer over the gate dielectric layer; and
patterning the gate electrode layer to form a first gate electrode region over the first isolation region and a second gate electrode region over the second isolation region wherein:
the first gate electrode region comprise a first portion over the first isolation region and a second portion over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.
16. The method of claim 15, further comprising:
forming a first drain/source region and a second drain/source region in the high voltage region, wherein the first drain/source region and the second drain/source region are on opposite sides of the first isolation region.
17. The method of claim 15, wherein:
the second gate electrode region includes a first portion over the high voltage region and a second portion over the low voltage region, and wherein a bottom of the second portion of the second gate electrode region is lower than a bottom of the first portion of the second gate electrode region.
18. The method of claim 15, wherein:
the second gate electrode region extends from a top surface of the gate dielectric layer to the top surface of the second isolation region.
19. The method of claim 15, further comprising:
patterning the gate electrode layer to form a third gate electrode region over the low voltage region, wherein a bottom of the third gate electrode region is lower than a bottom of the first gate electrode region.
20. The method of claim 19, further comprising:
forming a third drain/source region and a fourth drain/source region in the low voltage region, wherein the third drain/source region and the fourth drain/source region are on opposite sides of the third gate electrode region.
US15/624,280 2012-11-01 2017-06-15 Lateral MOSFET Active US10147814B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/624,280 US10147814B2 (en) 2012-11-01 2017-06-15 Lateral MOSFET
US16/177,808 US10347757B2 (en) 2012-11-01 2018-11-01 Lateral MOSFET

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/666,632 US9362272B2 (en) 2012-11-01 2012-11-01 Lateral MOSFET
US15/174,305 US9691895B2 (en) 2012-11-01 2016-06-06 Lateral MOSFET
US15/624,280 US10147814B2 (en) 2012-11-01 2017-06-15 Lateral MOSFET

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/174,305 Continuation US9691895B2 (en) 2012-11-01 2016-06-06 Lateral MOSFET

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/177,808 Continuation US10347757B2 (en) 2012-11-01 2018-11-01 Lateral MOSFET

Publications (2)

Publication Number Publication Date
US20170288054A1 US20170288054A1 (en) 2017-10-05
US10147814B2 true US10147814B2 (en) 2018-12-04

Family

ID=50546235

Family Applications (4)

Application Number Title Priority Date Filing Date
US13/666,632 Active US9362272B2 (en) 2012-11-01 2012-11-01 Lateral MOSFET
US15/174,305 Active US9691895B2 (en) 2012-11-01 2016-06-06 Lateral MOSFET
US15/624,280 Active US10147814B2 (en) 2012-11-01 2017-06-15 Lateral MOSFET
US16/177,808 Active US10347757B2 (en) 2012-11-01 2018-11-01 Lateral MOSFET

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US13/666,632 Active US9362272B2 (en) 2012-11-01 2012-11-01 Lateral MOSFET
US15/174,305 Active US9691895B2 (en) 2012-11-01 2016-06-06 Lateral MOSFET

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/177,808 Active US10347757B2 (en) 2012-11-01 2018-11-01 Lateral MOSFET

Country Status (2)

Country Link
US (4) US9362272B2 (en)
CN (1) CN103811549B (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064726B2 (en) * 2013-03-07 2015-06-23 Texas Instruments Incorporated Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
JP6341802B2 (en) * 2014-08-21 2018-06-13 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
US9735144B2 (en) * 2015-02-11 2017-08-15 Mediatek Inc. Electrostatic discharge (ESD) protection device
US9754788B2 (en) * 2015-07-13 2017-09-05 United Microelectronics Corp. Manufacturing method of semiconductor structure including planarizing a polysilicon layer over an array area and a periphery area
US10916542B2 (en) * 2015-12-30 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed STI as the gate dielectric of HV device
DE102016015953B4 (en) * 2015-12-30 2026-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Deepened STI as gate dielectric of a high-voltage component and manufacturing process
US10290714B2 (en) * 2016-05-31 2019-05-14 Taiwan Semiconductor Manufacturing Company Ltd. Transistor structure with field plate for reducing area thereof
US10431664B2 (en) * 2017-06-30 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and methods thereof
DE102018106266B4 (en) 2017-06-30 2024-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
DE102018107908B4 (en) 2017-07-28 2023-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming an integrated circuit with a sealing layer for forming a memory cell structure in logic or BCD technology, and an integrated circuit with a dummy structure at a boundary of a device region
US10504912B2 (en) 2017-07-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
TWI635611B (en) * 2017-09-25 2018-09-11 Nuvoton Technology Corporation High voltage semiconductor component
CN111199919B (en) * 2019-12-20 2021-05-14 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device and semiconductor device formed by same
CN113054004B (en) * 2021-03-11 2022-08-23 电子科技大学 Reverse electric field coupling isolation structure applied to high-low voltage isolation of integrated circuit
KR102860411B1 (en) * 2021-06-16 2025-09-15 삼성전자주식회사 Semiconductor device

Citations (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291439A (en) 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5293331A (en) 1992-06-01 1994-03-08 National Semiconductor Corporation High density EEPROM cell with tunnel oxide stripe
US5404037A (en) 1994-03-17 1995-04-04 National Semiconductor Corporation EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region
US5514607A (en) 1991-01-03 1996-05-07 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5731237A (en) 1990-12-20 1998-03-24 Fujitsu Limited Method of producing an EPROM with a trench insulating layer
US6084271A (en) 1998-11-06 2000-07-04 Advanced Micro Devices, Inc. Transistor with local insulator structure
US6121086A (en) 1998-06-17 2000-09-19 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
US6194702B1 (en) 1997-08-25 2001-02-27 International Business Machines Corporation Method of forming a complementary active pixel sensor cell
US6242298B1 (en) 1997-08-29 2001-06-05 Kabushiki Kaisha Toshiba Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same
US6246094B1 (en) 1998-10-20 2001-06-12 Winbond Electronics Corporation Buried shallow trench isolation and method for forming the same
US6380019B1 (en) 1998-11-06 2002-04-30 Advanced Micro Devices, Inc. Method of manufacturing a transistor with local insulator structure
US6444554B1 (en) 1997-03-28 2002-09-03 Hitachi, Ltd. Method of making a non-volatile memory and semiconductor device
US6531366B1 (en) 2001-07-12 2003-03-11 Cypress Semiconductor Corporation Method and structure for high-voltage device with self-aligned graded junctions
US6613690B1 (en) 2002-07-17 2003-09-02 Taiwan Semiconductor Manufacturing Company Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers
US6653682B1 (en) 1999-10-25 2003-11-25 Interuniversitair Microelektronica Centrum (Imel,Vzw) Non-volatile electrically alterable semiconductor memory device
US6806530B2 (en) 2002-09-10 2004-10-19 Samsung Electronics Co., Ltd. EEPROM device and method for fabricating same
US6884682B2 (en) 2003-06-30 2005-04-26 Hynix Semiconductor Inc. Method for manufacturing flash memory device
US20050104118A1 (en) 1995-03-07 2005-05-19 California Institute Of Technology, A California Non-Profit Corporation Floating-gate semiconductor structures
US20050151180A1 (en) 2004-01-09 2005-07-14 Taiwan Semiconductor Manufacturing Co. Method to reduce a capacitor depletion phenomena
US20050227440A1 (en) 2003-06-10 2005-10-13 Fujitsu Limited Semiconductor device and its manufacturing method
US20060001108A1 (en) 2004-07-05 2006-01-05 Fujitsu Limited Semiconductor device and method for manufacturing the same
US20060008976A1 (en) 2004-01-14 2006-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Novel random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
US20060006462A1 (en) 2004-07-12 2006-01-12 Chi-Hsuen Chang Method and apparatus for a semiconductor device having low and high voltage transistors
US7038268B2 (en) 2003-01-07 2006-05-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US20060172504A1 (en) 2005-02-03 2006-08-03 Monolithic System Technology, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US20080128819A1 (en) 2006-12-05 2008-06-05 Ki-Wan Bang Lateral mos transistor and method for manufacturing thereof
US20090096036A1 (en) 2007-10-11 2009-04-16 Takashi Ishigaki Semiconductor device and method of manufacturing the same
US20090159938A1 (en) 2006-01-05 2009-06-25 Nxp B.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
US7557004B2 (en) 2006-06-14 2009-07-07 Fujitsu Microelectronics Limited Method for fabricating semiconductor device
US20100025761A1 (en) 2008-07-31 2010-02-04 Voldman Steven H Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits
US20100044790A1 (en) 2008-08-13 2010-02-25 Shinjiro Kato Semiconductor device and method of etc.
US7807546B2 (en) 2003-09-05 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cell having stepped boundary regions and methods of fabrication
US7816726B2 (en) 2007-12-20 2010-10-19 Promos Technologies Pte. Ltd. Nonvolatile memories with laterally recessed charge-trapping dielectric
US7951686B2 (en) 2006-03-30 2011-05-31 Fujitsu Limited Method of manufacturing semiconductor device having device characteristics improved by straining surface of active region
US20110292964A1 (en) 2010-05-26 2011-12-01 Kashyap Avinash S Method for modeling and parameter extraction of LDMOS devices
US8102007B1 (en) 2001-08-13 2012-01-24 Synopsys, Inc. Apparatus for trimming high-resolution digital-to-analog converter
US20120058628A1 (en) 2008-12-29 2012-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-Gate Transistors with Reverse T-Shaped Fins
US20120292688A1 (en) 2011-05-17 2012-11-22 Euipil Kwon Highly integrated mos device and the manufacturing method thereof
US20120301989A1 (en) 2011-05-27 2012-11-29 Canon Kabushiki Kaisha Method for manufacturing solid-state image pickup device
US8329545B1 (en) 2008-12-30 2012-12-11 Micron Technology, Inc. Method of fabricating a charge trap NAND flash memory
US8368161B2 (en) 2009-03-04 2013-02-05 Sony Corporation Solid-state image capturing device, method of manufacturing solid-state image capturing device, and image capturing apparatus
US20130270634A1 (en) 2012-04-12 2013-10-17 Richtek Technology Corporation High voltage device and manufacturing method thereof
US20140117454A1 (en) 2012-10-26 2014-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI)
US9099334B2 (en) * 2011-10-28 2015-08-04 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
US9184053B2 (en) * 2012-01-10 2015-11-10 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310378B1 (en) * 1997-12-24 2001-10-30 Philips Electronics North American Corporation High voltage thin film transistor with improved on-state characteristics and method for making same

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731237A (en) 1990-12-20 1998-03-24 Fujitsu Limited Method of producing an EPROM with a trench insulating layer
US5514607A (en) 1991-01-03 1996-05-07 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5291439A (en) 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5293331A (en) 1992-06-01 1994-03-08 National Semiconductor Corporation High density EEPROM cell with tunnel oxide stripe
US5404037A (en) 1994-03-17 1995-04-04 National Semiconductor Corporation EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region
US20050104118A1 (en) 1995-03-07 2005-05-19 California Institute Of Technology, A California Non-Profit Corporation Floating-gate semiconductor structures
US6444554B1 (en) 1997-03-28 2002-09-03 Hitachi, Ltd. Method of making a non-volatile memory and semiconductor device
US6194702B1 (en) 1997-08-25 2001-02-27 International Business Machines Corporation Method of forming a complementary active pixel sensor cell
US6242298B1 (en) 1997-08-29 2001-06-05 Kabushiki Kaisha Toshiba Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same
US6121086A (en) 1998-06-17 2000-09-19 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
US6246094B1 (en) 1998-10-20 2001-06-12 Winbond Electronics Corporation Buried shallow trench isolation and method for forming the same
US6380019B1 (en) 1998-11-06 2002-04-30 Advanced Micro Devices, Inc. Method of manufacturing a transistor with local insulator structure
US6084271A (en) 1998-11-06 2000-07-04 Advanced Micro Devices, Inc. Transistor with local insulator structure
US6653682B1 (en) 1999-10-25 2003-11-25 Interuniversitair Microelektronica Centrum (Imel,Vzw) Non-volatile electrically alterable semiconductor memory device
US6531366B1 (en) 2001-07-12 2003-03-11 Cypress Semiconductor Corporation Method and structure for high-voltage device with self-aligned graded junctions
US8102007B1 (en) 2001-08-13 2012-01-24 Synopsys, Inc. Apparatus for trimming high-resolution digital-to-analog converter
US6613690B1 (en) 2002-07-17 2003-09-02 Taiwan Semiconductor Manufacturing Company Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers
US6806530B2 (en) 2002-09-10 2004-10-19 Samsung Electronics Co., Ltd. EEPROM device and method for fabricating same
US7038268B2 (en) 2003-01-07 2006-05-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US20050227440A1 (en) 2003-06-10 2005-10-13 Fujitsu Limited Semiconductor device and its manufacturing method
US7939893B2 (en) 2003-06-10 2011-05-10 Fujitsu Semiconductor Limited Semiconductor device and its manufacturing method
US6884682B2 (en) 2003-06-30 2005-04-26 Hynix Semiconductor Inc. Method for manufacturing flash memory device
US7807546B2 (en) 2003-09-05 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cell having stepped boundary regions and methods of fabrication
US20050151180A1 (en) 2004-01-09 2005-07-14 Taiwan Semiconductor Manufacturing Co. Method to reduce a capacitor depletion phenomena
US20060008976A1 (en) 2004-01-14 2006-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Novel random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
US20060001108A1 (en) 2004-07-05 2006-01-05 Fujitsu Limited Semiconductor device and method for manufacturing the same
US7119412B2 (en) 2004-07-05 2006-10-10 Fujitsu Limited Semiconductor device and method for manufacturing the same
US20060006462A1 (en) 2004-07-12 2006-01-12 Chi-Hsuen Chang Method and apparatus for a semiconductor device having low and high voltage transistors
US20060172504A1 (en) 2005-02-03 2006-08-03 Monolithic System Technology, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US20090159938A1 (en) 2006-01-05 2009-06-25 Nxp B.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
US7951686B2 (en) 2006-03-30 2011-05-31 Fujitsu Limited Method of manufacturing semiconductor device having device characteristics improved by straining surface of active region
US7557004B2 (en) 2006-06-14 2009-07-07 Fujitsu Microelectronics Limited Method for fabricating semiconductor device
US20080128819A1 (en) 2006-12-05 2008-06-05 Ki-Wan Bang Lateral mos transistor and method for manufacturing thereof
US20090096036A1 (en) 2007-10-11 2009-04-16 Takashi Ishigaki Semiconductor device and method of manufacturing the same
US7816726B2 (en) 2007-12-20 2010-10-19 Promos Technologies Pte. Ltd. Nonvolatile memories with laterally recessed charge-trapping dielectric
US20100025761A1 (en) 2008-07-31 2010-02-04 Voldman Steven H Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits
US20100044790A1 (en) 2008-08-13 2010-02-25 Shinjiro Kato Semiconductor device and method of etc.
US20120058628A1 (en) 2008-12-29 2012-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-Gate Transistors with Reverse T-Shaped Fins
US8329545B1 (en) 2008-12-30 2012-12-11 Micron Technology, Inc. Method of fabricating a charge trap NAND flash memory
US8368161B2 (en) 2009-03-04 2013-02-05 Sony Corporation Solid-state image capturing device, method of manufacturing solid-state image capturing device, and image capturing apparatus
US20110292964A1 (en) 2010-05-26 2011-12-01 Kashyap Avinash S Method for modeling and parameter extraction of LDMOS devices
US20120292688A1 (en) 2011-05-17 2012-11-22 Euipil Kwon Highly integrated mos device and the manufacturing method thereof
US20120301989A1 (en) 2011-05-27 2012-11-29 Canon Kabushiki Kaisha Method for manufacturing solid-state image pickup device
US9099334B2 (en) * 2011-10-28 2015-08-04 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
US9184053B2 (en) * 2012-01-10 2015-11-10 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20130270634A1 (en) 2012-04-12 2013-10-17 Richtek Technology Corporation High voltage device and manufacturing method thereof
US20140117454A1 (en) 2012-10-26 2014-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI)

Also Published As

Publication number Publication date
US20160284842A1 (en) 2016-09-29
US20170288054A1 (en) 2017-10-05
US9691895B2 (en) 2017-06-27
CN103811549B (en) 2017-04-12
CN103811549A (en) 2014-05-21
US10347757B2 (en) 2019-07-09
US9362272B2 (en) 2016-06-07
US20190074375A1 (en) 2019-03-07
US20140117444A1 (en) 2014-05-01

Similar Documents

Publication Publication Date Title
US10347757B2 (en) Lateral MOSFET
US11031495B2 (en) Apparatus and method for power MOS transistor
US11424244B2 (en) Integrated circuit having a vertical power MOS transistor
US10050126B2 (en) Apparatus and method for power MOS transistor
US9159786B2 (en) Dual gate lateral MOSFET
US9754839B2 (en) MOS transistor structure and method

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4