US10121519B2 - Semiconductor device and control method thereof - Google Patents
Semiconductor device and control method thereof Download PDFInfo
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- US10121519B2 US10121519B2 US15/694,842 US201715694842A US10121519B2 US 10121519 B2 US10121519 B2 US 10121519B2 US 201715694842 A US201715694842 A US 201715694842A US 10121519 B2 US10121519 B2 US 10121519B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
Definitions
- Embodiments described herein relate to generally a semiconductor device and a control method thereof.
- FIGS. 1A to 1C are diagrams illustrating an example of the exterior of a semiconductor device according to a first embodiment, wherein FIG. 1A is a plan view, FIG. 1B is a bottom view, and FIG. 1C is a side view.
- FIG. 2 is a diagram illustrating an example of a system configuration of the semiconductor device according to the first embodiment.
- FIG. 3 is a block diagram illustrating a configuration of a power IC according to the first embodiment.
- FIG. 4 is a diagram illustrating a sequence at the time of powering off the power IC according to the first embodiment.
- FIG. 5 is a flowchart illustrating an operation at the time of powering off the power IC according to the first embodiment.
- FIG. 6 is a schematic circuit diagram illustrating the components of an output side of power channels according to the first embodiment.
- FIG. 7 is a block diagram illustrating a configuration of a power IC and the periphery of the power IC according to a second embodiment.
- a semiconductor device in general, includes a connector configured for connection to a host, a power circuit supplied with a first voltage from the host via the connector, the power circuit including first and second channels configured to generate second and third voltages, respectively, from the first voltage, a semiconductor memory supplied with the second voltage via the first channel, and a controller for the semiconductor memory, supplied with the third voltage via the second channel.
- the power circuit When the first voltage is less than a first threshold, the power circuit turns off the first channel and the second channel.
- FIGS. 1A to 1C illustrate an example of the exterior of a semiconductor device 1 according to a first embodiment.
- FIG. 1A is a plan view
- FIG. 1B is a bottom view
- FIG. 1C is a side view.
- FIG. 2 illustrates an example of a system configuration of the semiconductor device 1 according to the first embodiment.
- the semiconductor device according to the embodiment is, for example, a memory system such as a solid state drive (SSD), but the present disclosure is not limited thereto.
- SSD solid state drive
- the semiconductor device 1 is connected to a host 2 .
- the host 2 is, for example, any of various types of electronic equipment such as a notebook-type portable computer, a tablet terminal, a detachable notebook-type PC, and a mobile phone.
- the host 2 may be a server device used in a data center or the like.
- the semiconductor device 1 can be used as, for example, an external memory of the host 2 .
- the semiconductor device 1 includes a substrate 11 , nonvolatile memories 12 , a controller 13 , a volatile memory 14 capable of operating at a higher speed than the nonvolatile memories 12 , an oscillator (OSC) 15 , an electrically erasable and programmable ROM (EEPROM) 16 , a power circuit 17 , a temperature sensor 18 , and other electronic components such as a resistor and a capacitor.
- OSC oscillator
- EEPROM electrically erasable and programmable ROM
- the oscillator 15 and the EEPROM 16 are not illustrated to simplify the description.
- the nonvolatile memory 12 is, for example, an NAND flash memory (hereinafter abbreviated to an NAND memory). In the following description, the nonvolatile memory 12 will be described as an “NAND memory 12 ,” but the nonvolatile memory 12 is not limited thereto. For example, another nonvolatile memory such as a magnetoresistive random access memory (MRAM) may be used.
- NAND memory 12 NAND flash memory
- MRAM magnetoresistive random access memory
- the volatile memory 14 is, for example, a dynamic random access memory (DRAM).
- DRAM dynamic random access memory
- the volatile memory 14 will be described as a “DRAM 14 ,” but the volatile memory 14 is not limited thereto. Another volatile memory may be used.
- the NAND memory 12 and the controller 13 according to the embodiment are mounted as a semiconductor package which is an electronic component.
- a semiconductor package of the NAND memory 12 a plurality of semiconductor chips are stacked to be sealed in one package.
- the substrate 11 is, for example, a substantially rectangular circuit board formed of a material such as a glass epoxy resin and defines the external dimensions of the semiconductor device 1 .
- the substrate 11 has a first surface 11 a and a second surface 11 b located opposite to the first surface 11 a .
- the first surface 11 a and the second surface 11 b can be called, for example, main surfaces.
- the first surface 11 a is a component-mounted surface on which the NAND memories 12 , the controller 13 , the DRAM 14 , the oscillator 15 , the EEPROM 16 , the power circuit 17 , the temperature sensor 18 , and other electronic components such as a resistor and a capacitor are mounted.
- the second surface 11 b is a non-mounted surface on which components such as the NAND memories 12 are not mounted. Since components are not mounted on the second surface, the semiconductor device 1 can be thin, and thus space saving is achieved. Further, it is also possible to miniaturize the host 2 in which the semiconductor device 1 is mounted in some configurations.
- components such as the NAND memories 12 may also be mounted on the second surface 11 b .
- components such as the NAND memories 12 may also be mounted on the second surface 11 b .
- another function of a test pad or the like for confirming performance of a product may be installed on the second surface 11 b.
- the substrate 11 includes a first edge portion 11 c and a second edge portion 11 d located opposite to the first edge portion 11 c .
- the first edge portion 11 c includes a connector 21 (which may be referred to as an interface unit, a substrate interface unit, a terminal unit, or a connection unit).
- the connector 21 includes, for example, a plurality of connection terminals 21 a .
- the connector 21 is electrically connected to the host 2 and exchange signals (e.g., a control signal and a data signal) with the host 2 .
- the semiconductor device 1 is electrically connected to the host 2 via the interface 3 .
- the host 2 executes data access control on the semiconductor device 1 and executes writing, reading, and erasing of data on the semiconductor device 1 , for example, by transmitting a write request, a read request, and an erasure request to the semiconductor device 1 .
- the semiconductor device 1 is electrically connected to the host power unit 4 (which is a power circuit) via a power line 5 .
- the host power unit 4 supplies various kinds of power used for the semiconductor device 1 via the power line 5 and the connector 21 .
- the interface 2 is, for example, a peripheral component interconnect express (PCIe). That is, a high-speed signal (high-speed differential signal) conforming to the PCIe standard flows between the connector 21 and the host 2 .
- PCIe peripheral component interconnect express
- SAS Serial Attached SCSI
- SATA Serial Advanced Technology Attachment
- NVMe Nonvolatile Memory Express
- USB Universal Serial Bus
- a slit 21 b is formed at a position deviated from a central position in the transverse direction of the substrate 11 and is fitted to a protrusion or the like formed on the connector side of the host 2 .
- the semiconductor device 1 can be prevented from being mounted with an incorrect orientation.
- the power circuit 17 is electrically connected to the host power unit 4 via the connector 21 and the power line 5 .
- the power circuit 17 supplies necessary power from the host power unit 5 to the semiconductor device 1 .
- the power circuit 17 supplies power to the NAND memory 12 , the controller 13 , and the DRAM 14 .
- the power circuit 17 is preferably installed near the connector 21 to prevent a loss of the power supplied from the host 2 .
- the power circuit 17 includes a power IC 17 a .
- Electronic components such as a resistor, a capacitor, and an inductor are connected to the power IC 17 a .
- the power IC 17 a will be described below.
- the power IC 17 a is also called a power unit, a power chip, or a composite power control IC.
- the power IC 17 a is, for example, a Power Management Integrated Circuit (PMIC).
- PMIC Power Management Integrated Circuit
- the power IC 17 a is, for example, a Wafer Level Chip Size Package (WLCSP) and at least one chip is packaged.
- WLCSP Wafer Level Chip Size Package
- the power IC 17 a is not limited thereto.
- the controller 13 controls an operation of the NAND memories 12 . That is, the controller 13 controls writing, reading, and erasing data on and from the NAND memories 12 .
- the controller 13 includes a reset input and executes initialization (or resetting) of a state of the controller 13 or releasing the reset state in accordance with an input signal to activate the semiconductor device 1 as a system normally.
- the signal used to release the reset state is called, for example, power on reset.
- resetting the reset state is assumed to also include both setting the state of the controller 13 to the reset state and maintaining the state of the controller 13 to remain in the reset state.
- the DRAM 14 is an example, a volatile memory, as described above, and is used to preserve management information of the NAND memory 12 or to cache data.
- the oscillator 15 supplies an operation signal with a predetermined frequency to the controller 13 .
- the EEPROM 16 stores a control program or the like as fixed information.
- the temperature sensor 18 monitors, for example, the temperature of the controller 13 .
- the temperature sensor 18 is mounted near, for example, the controller 13 on the substrate 11 , but the position of the temperature sensor 18 is not limited thereto. Further, the temperature sensor 18 may not necessarily be mounted on the substrate 11 , but maybe installed as a function of the controller 13 .
- the temperature sensor 18 measures a surrounding temperature of the position at which the temperature sensor 18 is mounted. A temperature measured by the temperature sensor 18 may be called “a temperature of the semiconductor device 1 .” When the temperature sensor 18 is mounted near the controller 13 , a temperature measured by the temperature sensor 18 may be called “a temperature of the controller 13 .”
- the second surface 11 b is a non-component-mounted surface on which components are not mounted.
- the semiconductor device 1 it is possible to thin the semiconductor device 1 . Further, it is also possible to miniaturize and thin the host 2 on which the semiconductor device 1 is mounted.
- FIG. 3 is a block diagram illustrating a configuration of the power IC 17 a according to the embodiment.
- the power IC 17 a includes a load switch 170 , a power control unit 171 , and a plurality of power channels CH 1 to CH 4 .
- the number of power channels is not limited thereto.
- An input Vin 0 of the load switch 170 is connected to the host 2 (specifically, the host power units 4 ) via wirings (e.g., wiring layers or internal wirings), the connector 21 , and the power line 5 installed in the substrate 11 . Power is first supplied from the host power unit 4 to the input Vin 0 of the load switch 170 .
- An output Vout 0 of the load switch 170 is electrically connected to inputs Vin 1 to Vin 4 of the power channels CH via, for example, wirings that are external to the power IC 17 a .
- power is supplied from the output Vout 0 of the load switch 170 to each power channel CH in the power IC 17 a again via the wirings (e.g., wiring layers or internal wirings) installed in the substrate 11 .
- the power channel CH 1 is, for example, a low drop out (LDO).
- the power channels CH 2 to CH 4 are, for example, DC/DC converters.
- the power channels CH 1 to CH 4 include registers R 1 to R 4 , respectively.
- the LDO is a linear regulator and is of a circuit type in which an input power is converted into a desired output voltage using an on resistance of a power device (e.g., pass transistor) such as a power metal oxide semiconductor field effect transistor (MOSFET) or a power transistor.
- a power device e.g., pass transistor
- MOSFET power metal oxide semiconductor field effect transistor
- the LDO tends to operate as a regulator even when a potential difference between input and output is small.
- the DC/DC converter is a switching regulator, outputs a switching pulse by switching an input voltage, and works as a DC power supply by smoothing the output pulse using a filter formed by an inductor and a coil.
- an output Vout 2 of the power channel CH 2 is connected to the controller 13 and supplies a predetermined voltage to the controller 13 .
- An output Vout 3 of the power channel CH 3 is connected to the DRAM 14 and supplies the predetermined voltage to the DRAM 14 .
- An output Vout 4 of the power channel CH 4 is connected to the NAND memories 12 and supplies a predetermined voltage to the NAND memories 12 .
- a type or connection relationship of each power channel CH is not limited to the above-described type or relation, but can be appropriately changed.
- the power channels CH 1 to CH 4 have various protection functions.
- the various protection functions include an over voltage protection (OVP) function, an under voltage protection (UVP) function, an over current protection (OCP) function, and the like.
- OVP over voltage protection
- UVP under voltage protection
- OCP over current protection
- the UVP function is activated when the output voltage of each power channel CH is less than a predetermined value (e.g., less than a UVP threshold, a threshold, or a second/third thresholds). More specifically, for example, when the output voltage Vout of the power channel CH 1 is less than a predetermined value Vth, the UVP function of the power channel CH 1 is activated.
- the UVP function is activated, for example, when an input and an output of each power channel CH are short-circuited and an overvoltage is input to the output side.
- a result obtained by monitoring whether the above-described UVP function is activated at each power channel CH is stored in each register R provided in each power channel CH.
- “1” is retained (recorded or set) in each register R.
- “0” is retained (recorded or set) in the register R provided in the power channel CH in which the OVP function is activated.
- the register R may also be called, for example, a “POWER GOOD (PG) register.”
- Each register R may be configured to monitor each power channel CH continuously or may be configured to monitor each power channel CH periodically (for example, at each period T 1 ). In the embodiment, each register R is assumed to monitor each power channel CH continuously in the description.
- “1” may be retained (recorded or set) in the register R. Further, “0” may be retained (recorded or set) in the register R provided in the power channel CH in which the UVP function is activated. Additionally, information recorded in the register is not limited thereto. At least information indicating whether the UVP function is activated in each power channel CH is recorded.
- the power control unit 171 is circuit that controls On/Off of the load switch 170 .
- the power control unit 171 monitors each register R of the power channels CH 1 to CH 4 .
- values of the monitoring target registers R 1 to R 4 are changed from “1” to “0,” in other words, the UVP function is activated in the power channels CH, the power control unit 171 switches the load switch 170 to Off.
- the power control unit 171 stops the supply of power to each power channel.
- the power control unit 171 may be configured to monitor each register R continuously or may be configured to monitor each register R periodically (for example, at each period T 2 ). In the embodiment, the power control unit 171 is assumed to monitor each register R continuously in the description.
- FIG. 4 is a diagram illustrating a sequence at the time of powering off the power IC 17 a .
- FIG. 5 is a flowchart illustrating an operation at the time of powering off the power IC 17 a.
- each power channel CH When each power channel CH is turned off, as illustrated in FIG. 4 , the output Vout of each power channel CH is lowered.
- the predetermined value e.g., the UVP threshold or the threshold
- the power control unit 171 turns off the load switch 170 (a point E in FIG. 4 ).
- the UVP threshold is, for example, 0.3 [V] or 0.5 [V], but the present disclosure is not limited thereto.
- the power control unit 171 when the input Vin 0 of the load switch 170 is less than the UVLO threshold, the power control unit 171 does not turn off the load switch 170 and turns off only each channel CH. Further, after then the output of each channel CH is less than the UVP threshold and the register R of each channel CH is set to “0,” the power control unit 171 is configured to turn off the load switch 170 .
- FIG. 6 is a schematic circuit diagram illustrating, for example, the inside of an output side of the power channels CH 2 to CH 4 .
- the power channels CH 2 to CH 4 are, for example, DC-DC converters.
- the power control unit 171 when the input Vin 0 of the load switch 170 is less than the UVLO threshold, the power control unit 171 does not turn off the load switch 170 and turns off only each channel CH. Further, after the output of each channel CH is less than the UVP threshold and the register R of each channel CH is set to “0,” the power control unit 171 is configured to turn off the load switch 170 . By configuring the load switch 170 to be turned off after each power channel CH is turned off, it is possible to shorten a time in which the power is turned off.
- FIG. 7 is a block diagram illustrating the configuration of a power IC 17 b and the periphery of the power IC 17 b according to the embodiment.
- a load switch 175 is installed separately from the power IC 17 b (i.e., installed outside of the package of the power IC 17 b /independently from the power IC 17 b ) and the output Vout 0 of the load switch 175 is connected to the input of each power channel CH of the power IC 17 b.
- the power IC 17 b includes a “POWER GOOD” output.
- the “POWER GOOD” output is a signal indicating whether a protection function is activated inside the power IC. Whether the protection function is activated is output by individually distinguishing, for example, “Low” from. “High” or “Low” from “Hi-Z.”
- the “POWER GOOD” output of the power IC 17 b is, for example, an open drain output. More specifically, a field effect transistor (FET) is installed in an output circuit inside the power IC 17 b and the drain of the field effect transistor is drawn out the outside of the power IC 17 b without being connected inside the power IC 17 b.
- FET field effect transistor
- the “POWER GOOD” output is pull-up on the input side of the load switch 175 . More specifically, the “POWER GOOD” output is connected to the input side of the load switch 175 via a pull-up resistance.
- An enable (EN) terminal is installed in the load switch 175 .
- the load switch 175 is turned on.
- Low (L) is input to the EN terminal, the load switch 175 is turned off.
- the “POWER GOOD” signal is output as a low signal and the load switch 175 is turned off. Therefore, by delaying a timing at which the input enters a state of being less than an operation voltage of the discharge resistance control element ContZ illustrated in FIG. 6 , it is possible to shorten a time in which the power is turned off.
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Abstract
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US20200058331A1 (en) * | 2018-03-12 | 2020-02-20 | Micron Technology, Inc. | Power management integrated circuit load switch driver with dynamic biasing |
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JP7148380B2 (en) * | 2018-12-10 | 2022-10-05 | ローム株式会社 | Drive modules, power controllers, switching power supplies |
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US20180286465A1 (en) | 2018-10-04 |
JP2018169731A (en) | 2018-11-01 |
JP6684745B2 (en) | 2020-04-22 |
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