US10020190B2 - Nano-heterostructure - Google Patents

Nano-heterostructure Download PDF

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US10020190B2
US10020190B2 US15/488,410 US201715488410A US10020190B2 US 10020190 B2 US10020190 B2 US 10020190B2 US 201715488410 A US201715488410 A US 201715488410A US 10020190 B2 US10020190 B2 US 10020190B2
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carbon nanotube
nano
heterostructure
nanometers
metallic
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US20180005825A1 (en
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Jin Zhang
Yang Wei
Kai-Li Jiang
Shou-Shan Fan
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Tsinghua University
Hon Hai Precision Industry Co Ltd
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Hon Hai Precision Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02606—Nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H01L51/0048—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions

Definitions

  • the present disclosure relates to a nano-heterostructure.
  • Heterojunction is an interface region formed by a contact of two different semiconductor materials. According to the conductivity types of different semiconductor materials, the heterojunction can be divided into homogeneous heterojunction (P-p junction or N-n junction) and heterotypic heterojunction (P-n or p-N).
  • a heterostructure can be formed by multilayer heterojunctions. The heterostructure has excellent photoelectric properties, which can be applied to ultra-high-speed switching devices, solar cells and semiconductor lasers.
  • two-dimensional semiconductor materials have excellent electronic and optical properties
  • the two-dimensional semiconductor materials are researched more and more in recent years.
  • the heterogeneous structures of conventional two-dimensional semiconductor materials are usually microstructures, applications of the two-dimensional semiconductor materials are limited.
  • FIG. 1 is a structure schematic view of one embodiment of a nano-heterostructure.
  • FIG. 2 is a flow chart of one embodiment of a method for making a nano-heterostructure.
  • FIG. 3 is structure schematic view of one embodiment of a semiconductor device.
  • FIG. 4 is a circuit diagram of the semiconductor device in FIG. 3 .
  • FIG. 5 is a flow chart of one embodiment of a method for making a semiconductor device.
  • substantially is defined to be essentially conforming to the particular dimension, shape, or other feature which is described, such that the component need not be exactly or strictly conforming to such a feature.
  • the term “comprise,” when utilized, means “include, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
  • the nano-heterostructure 100 comprises a first metallic carbon nanotube 102 , a semiconducting carbon nanotube 104 , a semiconductor layer 106 and a second metallic carbon nanotube 108 .
  • the semiconductor layer 106 comprises a first surface and a second surface opposite to the first surface.
  • the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are located on and in directly contact with the first surface.
  • the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are parallel and spaced away from each other.
  • the second metallic carbon nanotube 108 is located on and in directly contact with the second surface.
  • the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 extend in a first direction.
  • the second metallic carbon nanotube 108 extends in a second direction.
  • An angle can form between the first direction and the second direction. The angle can range from about 0 degrees to about 90 degrees.
  • the first metallic carbon nanotube 102 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube.
  • a diameter of the first metallic carbon nanotube 102 can be ranged from about 0.5 nanometers to about 100 nanometers. In one embodiment, the diameter of the first metallic carbon nanotube 102 ranges from about 0.5 nanometers to about 10 nanometers. In another embodiment, the first metallic carbon nanotube 102 is a single-walled carbon nanotube, and the diameter of the first metallic carbon nanotube 102 is in a range from about 0.5 nanometers to about 2 nanometers. In one embodiment, the first metallic carbon nanotube 102 is a single-walled carbon nanotube, and the diameter of the first metallic carbon nanotube 102 is about 1 nanometer.
  • the semiconducting carbon nanotube 104 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube.
  • a diameter of the semiconducting carbon nanotube 104 can be in a range from about 0.5 nanometers to about 10 nanometers. In one embodiment, the diameter of the semiconducting carbon nanotube 104 is in a range from about 0.5 nanometers to about 5 nanometers. In one embodiment, the semiconducting carbon nanotube 104 is a single-walled carbon nanotube, and the diameter of the semiconducting carbon nanotube 104 is about 1 nanometer.
  • the semiconductor layer 106 can be a two-dimensional structure.
  • a thickness of the semiconductor layer 106 can be ranged from about 1 nanometer to about 200 nanometers. In one embodiment, the thickness of the semiconductor layer 106 ranges from about 5 nanometers to about 30 nanometers. In another embodiment, the thickness of the semiconductor layer 106 is about 8 nanometers.
  • a material of the semiconductor layer 106 can be inorganic compound semiconductors, elemental semiconductors or organic semiconductors. Such as gallium arsenide, silicon carbide, polysilicon, monocrystalline silicon, naphthalene or molybdenum sulfide. In one embodiment, the material of the semiconductor layer 106 is transition metal sulfide. In one embodiment, the material of the semiconductor layer 106 is Molybdenum sulfide (MoS 2 ), and the thickness of the semiconductor layer 106 is about 8 nanometers.
  • the second metallic carbon nanotube 108 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube.
  • a diameter of the second metallic carbon nanotube 108 can be in a range from about 0.5 nanometers to about 100 nanometers. In one embodiment, the diameter of the second metallic carbon nanotube 108 ranges from about 0.5 nanometers to about 10 nanometers. In one embodiment, the second metallic carbon nanotube 108 is a single-walled carbon nanotube, and the diameter of the second metallic carbon nanotube 108 is ranged from about 0.5 nanometers to about 2 nanometers. In one embodiment, the second metallic carbon nanotube 108 is a single-walled carbon nanotube, and the diameter of the second metallic carbon nanotube 108 is about 1 nanometer.
  • a material and a size of the second metallic carbon nanotube 108 can be the same as that of the first metallic carbon nanotube 102 . In another embodiment, the material and the size of the second metallic carbon nanotube 108 are different from that of the first metallic carbon nanotube 102 .
  • the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are parallel and spaced away from each other. In one embodiment, a spacing of the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 is ranged from about 10 nanometers to about 10 microns.
  • the angle formed between the first direction and the second direction ranges from about 60 degrees to about 90 degrees. In one embodiment, the angle formed between the first direction and the second direction is about 90 degrees, that is, an extension direction of the first metallic carbon nanotube 102 and an extension direction of the semiconducting carbon nanotube 104 are both substantially perpendicular to an extension direction of the second metallic carbon nanotube 108 .
  • the second metallic carbon nanotube 108 is crossed with the first metallic carbon nanotube 102 .
  • a first three layered stereoscopic structure 110 can be formed at an intersection of the first metallic carbon nanotube 102 , the second metallic carbon nanotube 108 and the semiconductor layer 106 .
  • a cross-sectional area of the first three layered stereoscopic structure 110 is determined by the diameter of the first metallic carbon nanotubes 102 and the second metallic carbon nanotubes 108 . Since the first metallic carbon nanotube 102 and the second metallic carbon nanotube 108 are both nanomaterials, the cross-sectional area of the first three layered stereoscopic structure 110 is nanoscale.
  • the cross-sectional area of the first three layered stereoscopic structure 110 ranges from about 0.25 nm 2 to about 1000 nm 2 . In another embodiment, the cross-sectional area of the first three layered stereoscopic structure 110 ranges from about 0.25 nm 2 to about 100 nm 2 .
  • the semiconducting carbon nanotube 104 is crossed with the second metallic carbon nanotube 108 .
  • a second three layered stereoscopic structure 120 can be formed at an intersection of the semiconducting carbon nanotube 104 , the semiconductor layer 106 and the second metallic carbon nanotube 108 .
  • a cross-sectional area of the second three layered stereoscopic structure 120 is determined by the diameter of the semiconducting carbon nanotube 104 and the second metallic carbon nanotubes 108 . Since the semiconducting carbon nanotube 104 and the second metallic carbon nanotubes 108 are both nanomaterials, the cross-sectional area of the second three layered stereoscopic structure 120 is nanoscale.
  • the cross-sectional area of the second three layered stereoscopic structure 120 ranges from about 0.25 nm 2 to about 1000 nm 2 . In another embodiment, the cross-sectional area of the second three layered stereoscopic structure 120 ranges from about 0.25 nm 2 to about 100 nm 2 .
  • the diameter of the first metallic carbon nanotube 102 , the diameter of the semiconducting carbon nanotube 104 and the diameter of the second metallic carbon nanotube 108 are all nanoscale.
  • An n-type nano-heterojunction can be formed, without nano-lithography, at the intersection of the first metallic carbon nanotube 102 the semiconductor layer 106 , and the second metallic carbon nanotube 108 .
  • a nano-heterojunction p-n junction can be formed, without nano-lithography, at the intersection of the semiconducting carbon nanotube 104 , the semiconductor layer 106 , and the second metallic carbon nanotube 108 .
  • the nano-heterostructure 100 has lower energy consumption and higher integration.
  • the method comprises the following steps:
  • step (S 1 ) providing a support and forming a first carbon nanotube layer on the support, the first carbon nanotube layer comprises a plurality of first carbon nanotubes;
  • step (S 2 ) forming the semiconductor layer 106 on the first carbon nanotube layer
  • step (S 3 ) covering a second carbon nanotube layer on the semiconductor layer 106 , and the second carbon nanotube layer comprises a plurality of second carbon nanotubes;
  • step (S 4 ) finding and labeling the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 from the first carbon nanotube layer, wherein the first metallic carbon nanotube 102 is parallel to and spaced away from the semiconducting carbon nanotube 104 ; finding and labeling the second metallic carbon nanotube 108 from the second carbon nanotube layer, wherein an extending direction of the second metallic carbon nanotube 108 is crossed with an extending direction of the first metallic carbon nanotube 102 and an extending direction of the semiconducting carbon nanotube 104 ; and removing the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube 102 , the semiconducting carbon nanotube 104 and the second metallic carbon nanotube 108 to form a multilayer structure; and
  • step (S 5 ) annealing the multilayer structure obtained by above steps.
  • the support is used to support the first carbon nanotube layer.
  • a material of the support is not limited.
  • the material of the support is insulation material.
  • the support is a double-layered structure comprising a lower layer and an upper layer.
  • the lower layer is silicon material
  • the upper layer is silicon oxide with a thickness of 300 nanometers.
  • the plurality of first carbon nanotubes can be crossed or parallel to each other. In one embodiment, the plurality of first carbon nanotubes is parallel to each other.
  • a method for forming the first carbon nanotube layer on the support can be a transfer method comprising the following steps:
  • step (S 11 ) growing the first carbon nanotube layer on a substrate
  • step (S 12 ) coating a transition layer on a surface of the first carbon nanotube layer
  • step (S 13 ) separating the transition layer and the first carbon nanotube layer from the substrate.
  • step (S 14 ) putting the transition layer adhered with the first carbon nanotube layer on the support and removing the transition layer to make the first carbon nanotube layer formed on the support.
  • the substrate can be a silicon substrate.
  • a material of the transition layer can be polymethyl methacrylate (PMMA), and a thickness of the transition layer can be ranged from about 0.1 microns to about 1 micron.
  • PMMA polymethyl methacrylate
  • a method for separating the transition layer and the first carbon nanotube layer from the substrate comprises the steps of: transferring the first carbon nanotube layer coated with the transition layer and the substrate into an alkaline solution, and heating the alkaline solution to a temperature ranged from about 70° C. to about 100° C.
  • the first carbon nanotube layer is transferred to the transition layer.
  • the alkaline solution can be sodium hydroxide solution or potassium hydroxide solution.
  • step (S 14 ) in one embodiment, the PMMA was removed by acetone dissolution.
  • a method for forming the semiconductor layer 106 on the first carbon nanotube layer comprises the sub-steps of: providing a semiconductor crystal, tearing the semiconductor crystal several times by a tape until a two-dimensional semiconductor layer is formed on the tape, then disposing the two-dimensional semiconductor layer on the surface of the first carbon nanotube layer, and removing the tape.
  • a molybdenum sulfide single crystal is torn several times by the tape until a molybdenum sulfide layer with nano-thickness is formed on the tape; the tape coated with the molybdenum sulfide layer is covered on the surface of the first carbon nanotube layer; the tape is removed, and at least part of the molybdenum sulfide layer remains on the surface of the first carbon nanotube layer.
  • the plurality of second carbon nanotubes can be arranged substantially along a same direction.
  • the plurality of second carbon nanotubes are parallel to each other.
  • An aligned direction of the plurality of first carbon nanotubes is substantially perpendicular to an aligned direction of the plurality of second carbon nanotubes.
  • a method for covering the second carbon nanotube layer on the semiconductor layer 106 can be a transfer method. The transfer method of the second carbon nanotube layer is the same as that of the first carbon nanotube.
  • Step (S 4 ) comprises the sub-steps of:
  • SEM scanning electron microscopy
  • step ( 41 ) building an XY rectangular coordinate system along with a length direction and a width direction of the support; then finding the first metallic carbon nanotube 102 , the semiconducting carbon nanotube 104 , and the second metallic carbon nanotube 108 , and reading out the coordinate values of the first metallic carbon nanotube 102 and the second metallic carbon nanotube 108 .
  • step (S 5 ) the annealing the multilayer structure obtained by above steps is carried out in a vacuum atmosphere.
  • An annealing temperature can be ranged from about 300° C. to about 400° C.
  • impurities on a surface of the nano-heterostructure 100 can be removed, and a contact between the first carbon nanotube layer, the semiconductor layer 106 and the second carbon nanotube layer can be better.
  • the semiconductor device 200 comprises a nano-heterostructure, a first electrode 201 , a second electrode 202 , a third electrode 203 , and a fourth electrode 204 .
  • the first electrode 201 is electrically insulated from the second electrode 202 , the third electrode 203 , the fourth electrode 204 , and the nano-heterostructure via an insulating layer 205 .
  • the second electrode 202 , the third electrode 203 , and the fourth electrode 204 are electrically connected to the nano-heterostructure. Characteristics of the nano-heterostructure are the same as the nano-hetero structure 100 discussed above.
  • the second electrode 202 , the third electrode 203 , and the fourth electrode 204 are all made of metal, Indium Tin Oxides (ITO), Antimony Tin Oxide (ATO), conductive silver paste, carbon nanotubes or any other suitable conductive materials.
  • the metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys.
  • each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is a conductive film, a thickness of the conductive film is ranged from about 0.01 microns to about 10 microns.
  • each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is a metal composite structure formed by compounding metal Au on a surface of metal Ti.
  • a thickness of the metal Ti is ranged from about 5 nanometers.
  • a thickness of the metal Au is about 50 nanometers.
  • the second electrode 202 is located at one end of the first metallic carbon nanotube 102 and electrically connected to the first metallic carbon nanotube 102 ;
  • the third electrode 203 is located at one end of the second metallic carbon nanotube 108 and electrically connected to the second metallic carbon nanotube 108 ;
  • the fourth electrode 204 is located at one end of the semiconducting carbon nanotube 104 and electrically connected to the semiconducting carbon nanotube 104 .
  • the first electrode 201 can be made of metal, Indium Tin Oxides (ITO), Antimony Tin Oxide (ATO), conductive silver paste, carbon nanotubes or any other suitable conductive materials.
  • the metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys.
  • the first electrode 201 is a layer structure, the insulating layer 205 is located on a surface of the first electrode 201 , the second electrode 202 , the third electrode 203 , the fourth electrode 204 , and the nano-heterostructure is located on the insulating layer 205 and supported by the first electrode 201 and the insulating layer 205 .
  • the insulating layer 205 can be made of hard materials or flexible materials.
  • the hard materials can be silicon nitride or silicon oxide.
  • the flexible materials can be Benzocyclobutene (BCB), polyester or acrylic resin.
  • a thickness of the insulating layer 205 ranges from about 2 nanometers to about 100 microns.
  • An NMOS transistor can be formed by the first metallic carbon nanotube 102 , the semiconductor layer 106 , the second metallic carbon nanotube 108 , the second electrode 202 , the fourth electrode 204 , the first electrode 201 , and the insulating layer 205 .
  • a PMOS transistor can be formed by the semiconducting carbon nanotube 104 , the semiconductor layer 106 , the second metallic carbon nanotube 108 , the third electrode 203 , the fourth electrode 204 , the first electrode 201 , and the insulating layer 205 .
  • FIG. 4 is a circuit diagram of the semiconductor device 200 . If a low electrical level is input to the semiconductor device 200 , the PMOS transistor is turned on, the NMOS transistor is turned off, and a high electrical level is output.
  • the PMOS transistor is turned off, the NMOS transistor is turned on, and a low electrical level is output.
  • An inverter can be formed by the PMOS transistor and the NMOS transistor alternately working so that there is no low impedance DC path between the power supply operating voltage VDD and the common ground terminal voltage VSS. Therefore, a static power consumption of the semiconductor device 200 is minimal.
  • the semiconductor device 200 comprises two nanometer perpendicular heterojunctions; and the semiconductor device 200 is a three-dimensional structure while the in-plane dimensions are on the nanometer scale, which is beneficial to device miniaturization and improves device integration.
  • the method comprises the following steps:
  • Step M 1 providing a support and forming a first carbon nanotube layer on the support, the first carbon nanotube layer comprises a plurality of first carbon nanotubes;
  • Step M 2 forming the semiconductor layer 106 on the first carbon nanotube layer
  • Step M 3 covering a second carbon nanotube layer on the semiconductor layer 106 , and the second carbon nanotube layer comprises a plurality of second carbon nanotubes;
  • Step M 4 finding and labeling the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 from the first carbon nanotube layer, wherein the first metallic carbon nanotube 102 is parallel to and spaced away from the semiconducting carbon nanotube 104 ; finding and labeling the second metallic carbon nanotube 108 from the second carbon nanotube layer, wherein the extending direction of the second metallic carbon nanotube 108 is crossed with the extending direction of the first metallic carbon nanotube 102 and the extending direction of the semiconducting carbon nanotube 104 ; and removing the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube 102 , the semiconducting carbon nanotube 104 and the second metallic carbon nanotube 108 ;
  • Step M 5 forming the third electrode 203 at one end of the first metallic carbon nanotube 102 , forming the fourth electrode 204 at one end of the semiconducting carbon nanotube 104 , and forming the second electrode 202 at one end of the second metal type carbon nanotube 108 ;
  • Step M 6 annealing a structure obtained by above steps.
  • the support is a double-layered structure comprising a lower layer and an upper layer.
  • the lower layer is a conductive layer
  • the upper layer is an insulating layer.
  • the first carbon nanotube layer is formed on the insulating layer.
  • the conductive layer of the support can be the first electrode of the semiconductor device 200 .
  • Characteristics of step M 1 are the same as step S 1 of the second embodiment. Characteristics of step M 2 are the same as step S 2 of the second embodiment. Characteristics of step M 3 are the same as step S 3 of the second embodiment. Characteristics of step M 4 are the same as step S 4 of the second embodiment. Characteristics of step M 6 are the same as step S 5 of the second embodiment.
  • each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is made of metal, alloy, ITO, ATO, conductive silver paste, conductive polymers, conductive carbon nanotubes or any other suitable conductive materials.
  • the metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys.
  • each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is a conductive film, a thickness of the conductive film is ranged from about 0.01 microns to about 10 microns.
  • each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is made of metal, alloy, ITO, or ATO, each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 can be formed by vapor deposition, sputtering, deposition, masking, or etching. If each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 is made of conductive silver paste, conductive polymers, or conductive carbon nanotubes, each of the second electrode 202 , the third electrode 203 , and the fourth electrode 204 can be formed by printing or direct adhesion.
  • each of the second electrode 202 , the third electrode 203 and the fourth electrode 204 is a metal composite structure of Au and Ti.
  • Step M 5 comprises the sub-steps of:

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Abstract

The present disclosure relates to a nano-heterostructure. The nano-heterostructure includes a semiconductor layer, a first metallic carbon nanotube, a semiconducting carbon nanotube and a second metallic carbon nanotube. The semiconductor layer comprises a first surface and a second surface. The first metallic carbon nanotube is located on the first surface and extends in a first direction. The semiconducting carbon nanotube is located on the first surface and extends in the first direction. The semiconducting carbon nanotube is parallel and spaced away from the first metallic carbon nanotube. The second metallic carbon nanotube is located on the second surface and extends in a second direction. An angle forms between the first direction and the second direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims all benefits accruing under 35 U.S.C. § 119 from China Patent Application No. 201610502873.1, filed on Jul. 1, 2016, in the China Intellectual Property Office, the contents of which are hereby incorporated by reference.
FIELD
The present disclosure relates to a nano-heterostructure.
BACKGROUND
Heterojunction is an interface region formed by a contact of two different semiconductor materials. According to the conductivity types of different semiconductor materials, the heterojunction can be divided into homogeneous heterojunction (P-p junction or N-n junction) and heterotypic heterojunction (P-n or p-N). A heterostructure can be formed by multilayer heterojunctions. The heterostructure has excellent photoelectric properties, which can be applied to ultra-high-speed switching devices, solar cells and semiconductor lasers.
Since two-dimensional semiconductor materials have excellent electronic and optical properties, the two-dimensional semiconductor materials are researched more and more in recent years. However, the heterogeneous structures of conventional two-dimensional semiconductor materials are usually microstructures, applications of the two-dimensional semiconductor materials are limited.
BRIEF DESCRIPTION OF THE DRAWINGS
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures, wherein:
FIG. 1 is a structure schematic view of one embodiment of a nano-heterostructure.
FIG. 2 is a flow chart of one embodiment of a method for making a nano-heterostructure.
FIG. 3 is structure schematic view of one embodiment of a semiconductor device.
FIG. 4 is a circuit diagram of the semiconductor device in FIG. 3.
FIG. 5 is a flow chart of one embodiment of a method for making a semiconductor device.
 DETAILED DESCRIPTION
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “another,” “an,” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale, and the proportions of certain parts have been exaggerated to illustrate details and features of the present disclosure better.
Several definitions that apply throughout this disclosure will now be presented.
The term “substantially” is defined to be essentially conforming to the particular dimension, shape, or other feature which is described, such that the component need not be exactly or strictly conforming to such a feature. The term “comprise,” when utilized, means “include, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
Referring to FIG. 1, one embodiment is described in relation to a nano-heterostructure 100. The nano-heterostructure 100 comprises a first metallic carbon nanotube 102, a semiconducting carbon nanotube 104, a semiconductor layer 106 and a second metallic carbon nanotube 108. The semiconductor layer 106 comprises a first surface and a second surface opposite to the first surface. The first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are located on and in directly contact with the first surface. The first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are parallel and spaced away from each other. The second metallic carbon nanotube 108 is located on and in directly contact with the second surface. The first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 extend in a first direction. The second metallic carbon nanotube 108 extends in a second direction. An angle can form between the first direction and the second direction. The angle can range from about 0 degrees to about 90 degrees.
The first metallic carbon nanotube 102 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube. A diameter of the first metallic carbon nanotube 102 can be ranged from about 0.5 nanometers to about 100 nanometers. In one embodiment, the diameter of the first metallic carbon nanotube 102 ranges from about 0.5 nanometers to about 10 nanometers. In another embodiment, the first metallic carbon nanotube 102 is a single-walled carbon nanotube, and the diameter of the first metallic carbon nanotube 102 is in a range from about 0.5 nanometers to about 2 nanometers. In one embodiment, the first metallic carbon nanotube 102 is a single-walled carbon nanotube, and the diameter of the first metallic carbon nanotube 102 is about 1 nanometer.
The semiconducting carbon nanotube 104 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube. A diameter of the semiconducting carbon nanotube 104 can be in a range from about 0.5 nanometers to about 10 nanometers. In one embodiment, the diameter of the semiconducting carbon nanotube 104 is in a range from about 0.5 nanometers to about 5 nanometers. In one embodiment, the semiconducting carbon nanotube 104 is a single-walled carbon nanotube, and the diameter of the semiconducting carbon nanotube 104 is about 1 nanometer.
The semiconductor layer 106 can be a two-dimensional structure. A thickness of the semiconductor layer 106 can be ranged from about 1 nanometer to about 200 nanometers. In one embodiment, the thickness of the semiconductor layer 106 ranges from about 5 nanometers to about 30 nanometers. In another embodiment, the thickness of the semiconductor layer 106 is about 8 nanometers. A material of the semiconductor layer 106 can be inorganic compound semiconductors, elemental semiconductors or organic semiconductors. Such as gallium arsenide, silicon carbide, polysilicon, monocrystalline silicon, naphthalene or molybdenum sulfide. In one embodiment, the material of the semiconductor layer 106 is transition metal sulfide. In one embodiment, the material of the semiconductor layer 106 is Molybdenum sulfide (MoS2), and the thickness of the semiconductor layer 106 is about 8 nanometers.
The second metallic carbon nanotube 108 can be a single-walled carbon nanotube, double-walled carbon nanotube, or multi-walled carbon nanotube. A diameter of the second metallic carbon nanotube 108 can be in a range from about 0.5 nanometers to about 100 nanometers. In one embodiment, the diameter of the second metallic carbon nanotube 108 ranges from about 0.5 nanometers to about 10 nanometers. In one embodiment, the second metallic carbon nanotube 108 is a single-walled carbon nanotube, and the diameter of the second metallic carbon nanotube 108 is ranged from about 0.5 nanometers to about 2 nanometers. In one embodiment, the second metallic carbon nanotube 108 is a single-walled carbon nanotube, and the diameter of the second metallic carbon nanotube 108 is about 1 nanometer. In one embodiment, a material and a size of the second metallic carbon nanotube 108 can be the same as that of the first metallic carbon nanotube 102. In another embodiment, the material and the size of the second metallic carbon nanotube 108 are different from that of the first metallic carbon nanotube 102.
The first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 are parallel and spaced away from each other. In one embodiment, a spacing of the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 is ranged from about 10 nanometers to about 10 microns.
In one embodiment, the angle formed between the first direction and the second direction ranges from about 60 degrees to about 90 degrees. In one embodiment, the angle formed between the first direction and the second direction is about 90 degrees, that is, an extension direction of the first metallic carbon nanotube 102 and an extension direction of the semiconducting carbon nanotube 104 are both substantially perpendicular to an extension direction of the second metallic carbon nanotube 108.
The second metallic carbon nanotube 108 is crossed with the first metallic carbon nanotube 102. A first three layered stereoscopic structure 110 can be formed at an intersection of the first metallic carbon nanotube 102, the second metallic carbon nanotube 108 and the semiconductor layer 106. A cross-sectional area of the first three layered stereoscopic structure 110 is determined by the diameter of the first metallic carbon nanotubes 102 and the second metallic carbon nanotubes 108. Since the first metallic carbon nanotube 102 and the second metallic carbon nanotube 108 are both nanomaterials, the cross-sectional area of the first three layered stereoscopic structure 110 is nanoscale. In one embodiment, the cross-sectional area of the first three layered stereoscopic structure 110 ranges from about 0.25 nm2 to about 1000 nm2. In another embodiment, the cross-sectional area of the first three layered stereoscopic structure 110 ranges from about 0.25 nm2 to about 100 nm2.
The semiconducting carbon nanotube 104 is crossed with the second metallic carbon nanotube 108. A second three layered stereoscopic structure 120 can be formed at an intersection of the semiconducting carbon nanotube 104, the semiconductor layer 106 and the second metallic carbon nanotube 108. A cross-sectional area of the second three layered stereoscopic structure 120 is determined by the diameter of the semiconducting carbon nanotube 104 and the second metallic carbon nanotubes 108. Since the semiconducting carbon nanotube 104 and the second metallic carbon nanotubes 108 are both nanomaterials, the cross-sectional area of the second three layered stereoscopic structure 120 is nanoscale. In one embodiment, the cross-sectional area of the second three layered stereoscopic structure 120 ranges from about 0.25 nm2 to about 1000 nm2. In another embodiment, the cross-sectional area of the second three layered stereoscopic structure 120 ranges from about 0.25 nm2 to about 100 nm2.
The diameter of the first metallic carbon nanotube 102, the diameter of the semiconducting carbon nanotube 104 and the diameter of the second metallic carbon nanotube 108 are all nanoscale. An n-type nano-heterojunction can be formed, without nano-lithography, at the intersection of the first metallic carbon nanotube 102 the semiconductor layer 106, and the second metallic carbon nanotube 108. A nano-heterojunction p-n junction can be formed, without nano-lithography, at the intersection of the semiconducting carbon nanotube 104, the semiconductor layer 106, and the second metallic carbon nanotube 108. When a current gets through the n-type nano-heterojunction, the semiconducting carbon nanotube 104 and the nano-heterojunction P-n junction are in a cut-off state. When a current gets through the semiconducting carbon nanotubes and the nano-heterojunction P-n junction, the n-type nano-heterojunction is in the cut-off state. Since the first metallic carbon nanotube 102 and the second metallic carbon nanotube 108 are all nanoscale, the nano-heterostructure 100 has lower energy consumption and higher integration.
Referring to FIG. 2, one embodiment is described in relation to a method for making the nano-heterostructure 100. The method comprises the following steps:
step (S1), providing a support and forming a first carbon nanotube layer on the support, the first carbon nanotube layer comprises a plurality of first carbon nanotubes;
step (S2), forming the semiconductor layer 106 on the first carbon nanotube layer;
step (S3), covering a second carbon nanotube layer on the semiconductor layer 106, and the second carbon nanotube layer comprises a plurality of second carbon nanotubes;
step (S4), finding and labeling the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 from the first carbon nanotube layer, wherein the first metallic carbon nanotube 102 is parallel to and spaced away from the semiconducting carbon nanotube 104; finding and labeling the second metallic carbon nanotube 108 from the second carbon nanotube layer, wherein an extending direction of the second metallic carbon nanotube 108 is crossed with an extending direction of the first metallic carbon nanotube 102 and an extending direction of the semiconducting carbon nanotube 104; and removing the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube 102, the semiconducting carbon nanotube 104 and the second metallic carbon nanotube 108 to form a multilayer structure; and
step (S5), annealing the multilayer structure obtained by above steps.
In step (S1), the support is used to support the first carbon nanotube layer. A material of the support is not limited. In one embodiment, the material of the support is insulation material. In one embodiment, the support is a double-layered structure comprising a lower layer and an upper layer. The lower layer is silicon material, and the upper layer is silicon oxide with a thickness of 300 nanometers. The plurality of first carbon nanotubes can be crossed or parallel to each other. In one embodiment, the plurality of first carbon nanotubes is parallel to each other.
A method for forming the first carbon nanotube layer on the support can be a transfer method comprising the following steps:
step (S11), growing the first carbon nanotube layer on a substrate;
step (S12), coating a transition layer on a surface of the first carbon nanotube layer;
step (S13), separating the transition layer and the first carbon nanotube layer from the substrate; and
step (S14), putting the transition layer adhered with the first carbon nanotube layer on the support and removing the transition layer to make the first carbon nanotube layer formed on the support.
In step (S11), the substrate can be a silicon substrate.
In step (S12), a material of the transition layer can be polymethyl methacrylate (PMMA), and a thickness of the transition layer can be ranged from about 0.1 microns to about 1 micron.
In one embodiment, in step (S13), a method for separating the transition layer and the first carbon nanotube layer from the substrate comprises the steps of: transferring the first carbon nanotube layer coated with the transition layer and the substrate into an alkaline solution, and heating the alkaline solution to a temperature ranged from about 70° C. to about 100° C. The first carbon nanotube layer is transferred to the transition layer. The alkaline solution can be sodium hydroxide solution or potassium hydroxide solution. In one embodiment, transferring the first carbon nanotube layer coated with the transition layer and the substrate into potassium hydroxide solution, heating the potassium hydroxide solution to about 90° C. for about 20 minutes.
In step (S14), in one embodiment, the PMMA was removed by acetone dissolution.
In step S2, a method for forming the semiconductor layer 106 on the first carbon nanotube layer comprises the sub-steps of: providing a semiconductor crystal, tearing the semiconductor crystal several times by a tape until a two-dimensional semiconductor layer is formed on the tape, then disposing the two-dimensional semiconductor layer on the surface of the first carbon nanotube layer, and removing the tape. In one embodiment, a molybdenum sulfide single crystal is torn several times by the tape until a molybdenum sulfide layer with nano-thickness is formed on the tape; the tape coated with the molybdenum sulfide layer is covered on the surface of the first carbon nanotube layer; the tape is removed, and at least part of the molybdenum sulfide layer remains on the surface of the first carbon nanotube layer.
In step (S3), the plurality of second carbon nanotubes can be arranged substantially along a same direction. In one embodiment, the plurality of second carbon nanotubes are parallel to each other. An aligned direction of the plurality of first carbon nanotubes is substantially perpendicular to an aligned direction of the plurality of second carbon nanotubes. A method for covering the second carbon nanotube layer on the semiconductor layer 106 can be a transfer method. The transfer method of the second carbon nanotube layer is the same as that of the first carbon nanotube.
Step (S4) comprises the sub-steps of:
step (S41): finding the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 from the first carbon nanotube layer via a scanning electron microscopy (SEM), and labeling the coordinate positions of the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104; and finding the second metallic carbon nanotube 108 from the second carbon nanotube layer via the scanning electron microscopy (SEM), and labeling a coordinate position of the second metallic carbon nanotube 108;
step (S42): protecting the first metallic carbon nanotube 102, the semiconducting carbon nanotubes 104, and the second metallic carbon nanotube 108 by electron beam exposure, exposing the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube 102, the semiconducting carbon nanotube 104 and the second metallic carbon nanotube 108, and etching away the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube, the semiconducting carbon nanotube and the second metallic carbon nanotube by plasma etching.
In step (41), building an XY rectangular coordinate system along with a length direction and a width direction of the support; then finding the first metallic carbon nanotube 102, the semiconducting carbon nanotube 104, and the second metallic carbon nanotube 108, and reading out the coordinate values of the first metallic carbon nanotube 102 and the second metallic carbon nanotube 108.
In step (S5), the annealing the multilayer structure obtained by above steps is carried out in a vacuum atmosphere. An annealing temperature can be ranged from about 300° C. to about 400° C. After annealing, impurities on a surface of the nano-heterostructure 100 can be removed, and a contact between the first carbon nanotube layer, the semiconductor layer 106 and the second carbon nanotube layer can be better.
Referring to FIG. 3, one embodiment is described in relation to a semiconductor device 200. The semiconductor device 200 comprises a nano-heterostructure, a first electrode 201, a second electrode 202, a third electrode 203, and a fourth electrode 204. The first electrode 201 is electrically insulated from the second electrode 202, the third electrode 203, the fourth electrode 204, and the nano-heterostructure via an insulating layer 205. The second electrode 202, the third electrode 203, and the fourth electrode 204 are electrically connected to the nano-heterostructure. Characteristics of the nano-heterostructure are the same as the nano-hetero structure 100 discussed above.
The second electrode 202, the third electrode 203, and the fourth electrode 204 are all made of metal, Indium Tin Oxides (ITO), Antimony Tin Oxide (ATO), conductive silver paste, carbon nanotubes or any other suitable conductive materials. The metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys. In one embodiment, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is a conductive film, a thickness of the conductive film is ranged from about 0.01 microns to about 10 microns. In one embodiment, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is a metal composite structure formed by compounding metal Au on a surface of metal Ti. A thickness of the metal Ti is ranged from about 5 nanometers. A thickness of the metal Au is about 50 nanometers. In one embodiment, the second electrode 202 is located at one end of the first metallic carbon nanotube 102 and electrically connected to the first metallic carbon nanotube 102; the third electrode 203 is located at one end of the second metallic carbon nanotube 108 and electrically connected to the second metallic carbon nanotube 108; and the fourth electrode 204 is located at one end of the semiconducting carbon nanotube 104 and electrically connected to the semiconducting carbon nanotube 104.
The first electrode 201 can be made of metal, Indium Tin Oxides (ITO), Antimony Tin Oxide (ATO), conductive silver paste, carbon nanotubes or any other suitable conductive materials. The metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys. In one embodiment, the first electrode 201 is a layer structure, the insulating layer 205 is located on a surface of the first electrode 201, the second electrode 202, the third electrode 203, the fourth electrode 204, and the nano-heterostructure is located on the insulating layer 205 and supported by the first electrode 201 and the insulating layer 205.
The insulating layer 205 can be made of hard materials or flexible materials. The hard materials can be silicon nitride or silicon oxide. The flexible materials can be Benzocyclobutene (BCB), polyester or acrylic resin. A thickness of the insulating layer 205 ranges from about 2 nanometers to about 100 microns.
An NMOS transistor can be formed by the first metallic carbon nanotube 102, the semiconductor layer 106, the second metallic carbon nanotube 108, the second electrode 202, the fourth electrode 204, the first electrode 201, and the insulating layer 205. A PMOS transistor can be formed by the semiconducting carbon nanotube 104, the semiconductor layer 106, the second metallic carbon nanotube 108, the third electrode 203, the fourth electrode 204, the first electrode 201, and the insulating layer 205. FIG. 4 is a circuit diagram of the semiconductor device 200. If a low electrical level is input to the semiconductor device 200, the PMOS transistor is turned on, the NMOS transistor is turned off, and a high electrical level is output. If a high electrical level is input to the semiconductor device 200, the PMOS transistor is turned off, the NMOS transistor is turned on, and a low electrical level is output. An inverter can be formed by the PMOS transistor and the NMOS transistor alternately working so that there is no low impedance DC path between the power supply operating voltage VDD and the common ground terminal voltage VSS. Therefore, a static power consumption of the semiconductor device 200 is minimal.
In one embodiment, the semiconductor device 200 comprises two nanometer perpendicular heterojunctions; and the semiconductor device 200 is a three-dimensional structure while the in-plane dimensions are on the nanometer scale, which is beneficial to device miniaturization and improves device integration.
Referring to FIG. 4, one embodiment is described in relation to a method for making the semiconductor device 200. The method comprises the following steps:
Step M1 providing a support and forming a first carbon nanotube layer on the support, the first carbon nanotube layer comprises a plurality of first carbon nanotubes;
Step M2: forming the semiconductor layer 106 on the first carbon nanotube layer;
Step M3: covering a second carbon nanotube layer on the semiconductor layer 106, and the second carbon nanotube layer comprises a plurality of second carbon nanotubes;
Step M4: finding and labeling the first metallic carbon nanotube 102 and the semiconducting carbon nanotube 104 from the first carbon nanotube layer, wherein the first metallic carbon nanotube 102 is parallel to and spaced away from the semiconducting carbon nanotube 104; finding and labeling the second metallic carbon nanotube 108 from the second carbon nanotube layer, wherein the extending direction of the second metallic carbon nanotube 108 is crossed with the extending direction of the first metallic carbon nanotube 102 and the extending direction of the semiconducting carbon nanotube 104; and removing the plurality of first carbon nanotubes and the plurality of second carbon nanotubes except for the first metallic carbon nanotube 102, the semiconducting carbon nanotube 104 and the second metallic carbon nanotube 108;
Step M5: forming the third electrode 203 at one end of the first metallic carbon nanotube 102, forming the fourth electrode 204 at one end of the semiconducting carbon nanotube 104, and forming the second electrode 202 at one end of the second metal type carbon nanotube 108; and
Step M6: annealing a structure obtained by above steps.
In one embodiment, the support is a double-layered structure comprising a lower layer and an upper layer. The lower layer is a conductive layer, and the upper layer is an insulating layer. The first carbon nanotube layer is formed on the insulating layer. The conductive layer of the support can be the first electrode of the semiconductor device 200.
Characteristics of step M1 are the same as step S1 of the second embodiment. Characteristics of step M2 are the same as step S2 of the second embodiment. Characteristics of step M3 are the same as step S3 of the second embodiment. Characteristics of step M4 are the same as step S4 of the second embodiment. Characteristics of step M6 are the same as step S5 of the second embodiment.
In step M5, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is made of metal, alloy, ITO, ATO, conductive silver paste, conductive polymers, conductive carbon nanotubes or any other suitable conductive materials. The metal can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium or any combination of alloys. In one embodiment, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is a conductive film, a thickness of the conductive film is ranged from about 0.01 microns to about 10 microns.
If each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is made of metal, alloy, ITO, or ATO, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 can be formed by vapor deposition, sputtering, deposition, masking, or etching. If each of the second electrode 202, the third electrode 203, and the fourth electrode 204 is made of conductive silver paste, conductive polymers, or conductive carbon nanotubes, each of the second electrode 202, the third electrode 203, and the fourth electrode 204 can be formed by printing or direct adhesion.
In one embodiment, each of the second electrode 202, the third electrode 203 and the fourth electrode 204 is a metal composite structure of Au and Ti. Step M5 comprises the sub-steps of:
step (M51): coating a layer of photoresist on a surface of the support;
step (M52): separately depositing a metal layer on a surface of the first metallic carbon nanotube 102, a surface of the semiconducting carbon nanotube 104, and a surface of the second metallic carbon nanotube 108 by electron beam exposure, development, or electron beam deposition;
step (M53): peeling off by organic solvents, such as acetone.
It is to be understood that the above-described embodiments are intended to illustrate rather than limit the present disclosure. Variations may be made to the embodiments without departing from the spirit of the present disclosure as claimed. Elements associated with any of the above embodiments are envisioned to be associated with any other embodiments. The above-described embodiments illustrate the scope of the present disclosure but do not restrict the scope of the present disclosure.
Depending on the embodiment, certain of the steps of a method described may be removed, others may be added, and the sequence of steps may be altered. The description and the claims drawn to a method may include some indication in reference to certain steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.

Claims (20)

What is claimed is:
1. A nano-heterostructure comprising:
a semiconductor layer comprising a first surface and a second surface opposite to the first surface;
a first metallic carbon nanotube located on the first surface and extending along a first direction;
a semiconducting carbon nanotube located on the first surface and extending along the first direction, the semiconducting carbon nanotube being parallel and spaced away from the first metallic carbon nanotube; and
a second metallic carbon nanotube located on the second surface and extending along a second direction, an angle being formed between the first direction and the second direction.
2. The nano-heterostructure of claim 1, wherein the angle ranges from about 60 degrees to about 90 degrees.
3. The nano-heterostructure of claim 2, wherein the angle is about 90 degrees.
4. The nano-heterostructure of claim 1, wherein a diameter of the first metallic carbon nanotube is ranged from about 0.5 nanometers to about 100 nanometers.
5. The nano-heterostructure of claim 4, wherein the diameter of the first metallic carbon nanotube ranges from about 0.5 nanometers to about 10 nanometers.
6. The nano-heterostructure of claim 5, wherein the first metallic carbon nanotube is a single-walled carbon nanotube and the diameter of the first metallic carbon nanotube is in a range from about 0.5 nanometers to about 2 nanometers.
7. The nano-heterostructure of claim 1, wherein a diameter of the semiconducting carbon nanotube is in a range from about 0.5 nanometers to about 10 nanometers.
8. The nano-heterostructure of claim 7, wherein the diameter of the semiconducting carbon nanotube is in a range from about 0.5 nanometers to about 5 nanometers.
9. The nano-heterostructure of claim 8, wherein the semiconducting carbon nanotube is a single-walled carbon nanotube and the diameter of the semiconducting carbon nanotube is about 1 nanometer.
10. The nano-heterostructure of claim 1, wherein a thickness of the semiconductor layer ranges from about 5 nanometers to about 30 nanometers.
11. The nano-heterostructure of claim 1, wherein a material of the semiconductor layer is transition metal sulfide.
12. The nano-heterostructure of claim 11, wherein the material of the semiconductor layer is Molybdenum sulfide.
13. The nano-heterostructure of claim 1, wherein a diameter of the second metallic carbon nanotube ranges from about 0.5 nanometers to about 10 nanometers.
14. The nano-heterostructure of claim 13, wherein the second metallic carbon nanotube is a single-walled carbon nanotube and the diameter of the second metallic carbon nanotube is ranged from about 0.5 nanometers to about 2 nanometers.
15. The nano-heterostructure of claim 1, wherein a spacing of the first metallic carbon nanotube and the semiconducting carbon nanotube is ranged from about 10 nanometers to about 10 microns.
16. The nano-heterostructure of claim 1, wherein a first three layered stereoscopic structure is formed at an intersection of the first metallic carbon nanotube, the second metallic carbon nanotube, and the semiconductor layer.
17. The nano-heterostructure of claim 16, wherein a cross-sectional area of the first three layered stereoscopic structure ranges from about 0.25 nm2 to about 1000 nm2.
18. The nano-heterostructure of claim 1, wherein a second three layered stereoscopic structure is formed at an intersection of the semiconducting carbon nanotube, the semiconductor layer, and the second metallic carbon nanotube.
19. The nano-heterostructure of claim 18, wherein a cross-sectional area of the second three layered stereoscopic structure 120 ranges from about 0.25 nm2 to about 1000 nm2.
20. A nano-heterostructure comprising:
a semiconductor layer comprising a first surface and a second surface opposite to the first surface;
a first metallic carbon nanotube located on the first surface and extending along a first direction;
a semiconducting carbon nanotube located on the first surface and extending along the first direction, the semiconducting carbon nanotube being parallel and spaced away from the first metallic carbon nanotube; and
a second metallic carbon nanotube located on the second surface and extending along a second direction, an angle being formed between the first direction and the second direction;
wherein a first three layered stereoscopic structure is formed at an intersection of the first metallic carbon nanotube, the second metallic carbon nanotube and the semiconductor layer; and a second three layered stereoscopic structure is formed at an intersection of the semiconducting carbon nanotube, the semiconductor layer and the second metallic carbon nanotube.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11217727B2 (en) * 2019-11-08 2022-01-04 Tsinghua University Light emitting diode

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564947A (en) * 2016-07-01 2018-01-09 清华大学 Nano-heterogeneous structure
CN112786678B (en) * 2019-11-08 2022-11-22 清华大学 Semiconductor structure and semiconductor device
CN112786715B (en) * 2019-11-08 2022-11-22 清华大学 Solar cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872334B2 (en) * 2007-05-04 2011-01-18 International Business Machines Corporation Carbon nanotube diodes and electrostatic discharge circuits and methods
US9773990B1 (en) * 2016-07-01 2017-09-26 Tsinghua University Semiconductor device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE465519T1 (en) * 1999-02-22 2010-05-15 Clawson Joseph E Jr ELECTRONIC COMPONENT BASED ON NANOSTRUCTURES
JP2003504857A (en) * 1999-07-02 2003-02-04 プレジデント・アンド・フェローズ・オブ・ハーバード・カレッジ Apparatus using nanoscopic wire, array, and method of manufacturing the same
JP3859199B2 (en) * 2000-07-18 2006-12-20 エルジー エレクトロニクス インコーポレイティド Carbon nanotube horizontal growth method and field effect transistor using the same
EP1463853A4 (en) * 2001-12-18 2005-09-28 Univ Yale Controlled growth of single-wall carbon nanotubes
EP1758126A3 (en) * 2002-07-25 2007-03-14 California Institute Of Technology Nanoscale selection circuit
JP4501339B2 (en) * 2002-11-29 2010-07-14 ソニー株式会社 Method for manufacturing pn junction element
US7525833B2 (en) * 2005-10-21 2009-04-28 Hewlett-Packard Development Company, L.P. Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers
US7786465B2 (en) * 2005-12-20 2010-08-31 Invention Science Fund 1, Llc Deletable nanotube circuit
JP5157074B2 (en) * 2006-03-16 2013-03-06 富士通株式会社 Field effect transistor and manufacturing method thereof
US8217386B2 (en) * 2006-06-29 2012-07-10 University Of Florida Research Foundation, Inc. Short channel vertical FETs
CN100472755C (en) * 2006-09-19 2009-03-25 北京大学 Integration method for single-wall carbon nano tube part
CN102194623B (en) * 2010-03-17 2013-11-20 清华大学 Preparation method of transmission electron microscope microgrid
CN102244002B (en) * 2011-07-14 2013-01-09 合肥工业大学 Preparation method of heterojunction with metal/semiconductor nanometer wire crossing structure
CN102420244B (en) * 2011-11-14 2013-10-09 清华大学 One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof
CN103377749B (en) * 2012-04-25 2016-08-10 北京富纳特创新科技有限公司 Electronic component
CN103219403B (en) * 2013-04-19 2016-06-08 苏州大学 Photo-detector based on two-dimensional layer atomic crystal material
US9472686B2 (en) * 2013-08-02 2016-10-18 Northwestern University Gate-tunable P-N heterojunction diode, and fabrication method and application of same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872334B2 (en) * 2007-05-04 2011-01-18 International Business Machines Corporation Carbon nanotube diodes and electrostatic discharge circuits and methods
US9773990B1 (en) * 2016-07-01 2017-09-26 Tsinghua University Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11217727B2 (en) * 2019-11-08 2022-01-04 Tsinghua University Light emitting diode

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