UA75958U - FORMER OF A PACK OF IMPULSES OF TYPE MEANDRES OF ADJUSTABLE DURATION AND A FIXED QUANTITY AMOUNTING TWO - Google Patents
FORMER OF A PACK OF IMPULSES OF TYPE MEANDRES OF ADJUSTABLE DURATION AND A FIXED QUANTITY AMOUNTING TWOInfo
- Publication number
- UA75958U UA75958U UAU201204101U UAU201204101U UA75958U UA 75958 U UA75958 U UA 75958U UA U201204101 U UAU201204101 U UA U201204101U UA U201204101 U UAU201204101 U UA U201204101U UA 75958 U UA75958 U UA 75958U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- meandres
- impulses
- pack
- former
- Prior art date
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Pulse Circuits (AREA)
Abstract
Формувач пачки імпульсів типу меандр перенастроюваної тривалості і фіксованої кількості, яка дорівнює двом, що містить два реверсивні двійкові лічильники, перший із яких, налагоджений на режим віднімання, має вхід подачі імпульсів синхронізації, вхід дозволу синхронного паралельного завантаження і входи подачі даних при завантаженні, вхід дозволу режиму лічби, вхід асинхронної установки у нульовий стан, вихід переповнювання; JK-тригер зі входом асинхронної установки у нульовий стан; два інвертори; перший і другий елементи АБО; ланцюжок, що складається з послідовно з'єднаних резистора і конденсатора; стартостопний пристрій, якій містить синхронний D-тригер зі входом асинхронної установки у нульовий стан, перший і другий елементи І. Введена спрощена структура другого реверсивного лічильника за рахунок запобігання ланцюгу синхронного паралельного завантаження.Pulse packer type meander of adjustable duration and a fixed amount equal to two, containing two reversible binary counters, the first of which, adjusted to the subtraction mode, has an input pulse synchronization input, input synchronous parallel loading and inputs digital mode permissions, asynchronous zero input, overflow output; JK-trigger with asynchronous zero input; two inverters; the first and second elements OR; a circuit consisting of a series-connected resistor and a capacitor; startup device, which contains a synchronous D-flip-flop with the input of the asynchronous zero setting, the first and second elements I. Introduced a simplified structure of the second reversible counter by preventing the synchronous parallel load circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201204101U UA75958U (en) | 2012-04-03 | 2012-04-03 | FORMER OF A PACK OF IMPULSES OF TYPE MEANDRES OF ADJUSTABLE DURATION AND A FIXED QUANTITY AMOUNTING TWO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201204101U UA75958U (en) | 2012-04-03 | 2012-04-03 | FORMER OF A PACK OF IMPULSES OF TYPE MEANDRES OF ADJUSTABLE DURATION AND A FIXED QUANTITY AMOUNTING TWO |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UA75958U true UA75958U (en) | 2012-12-25 |
Family
ID=50844332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| UAU201204101U UA75958U (en) | 2012-04-03 | 2012-04-03 | FORMER OF A PACK OF IMPULSES OF TYPE MEANDRES OF ADJUSTABLE DURATION AND A FIXED QUANTITY AMOUNTING TWO |
Country Status (1)
| Country | Link |
|---|---|
| UA (1) | UA75958U (en) |
-
2012
- 2012-04-03 UA UAU201204101U patent/UA75958U/en unknown
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