UA73100U - Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number - Google Patents

Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number

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Publication number
UA73100U
UA73100U UAU201202602U UAU201202602U UA73100U UA 73100 U UA73100 U UA 73100U UA U201202602 U UAU201202602 U UA U201202602U UA U201202602 U UAU201202602 U UA U201202602U UA 73100 U UA73100 U UA 73100U
Authority
UA
Ukraine
Prior art keywords
counter
input
shaper
pulses
reversible
Prior art date
Application number
UAU201202602U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Николай Григорьевич Коробков
Елена Николаевна Коробкова
Василий Григорьевич Рубанов
Вячеслав Сергеевич Харченко
Original Assignee
Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт" filed Critical Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт"
Priority to UAU201202602U priority Critical patent/UA73100U/en
Publication of UA73100U publication Critical patent/UA73100U/en

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  • Manipulation Of Pulses (AREA)

Abstract

A shaper of periodic sequence of pulses with programmable width and a pulse ratio equal to the whole number comprises two reversible binary counters, first of which is a reversible countdown counter, have a clock input, a counting mode enable input, an asynchronous reset, an overflow output; moreover, the first counter comprises a synchronous parallel load input and a loading data input, an inverter, two OR elements, a circuit comprising in series connected resistor and capacitor, a start/stop device comprising a synchronous D-flip-flop having an asynchronous reset, first and second AND elements. Third reversible countdown binary counter is introduced containing a clock input, a synchronous parallel load input and a loading data input, a counting mode enable input, an asynchronous reset, an overflow output, a binary multiplier, a third OR element, a third AND element, a second inverter. Number of bits of the third counter is more then number of bits of the first counter.
UAU201202602U 2012-03-05 2012-03-05 Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number UA73100U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201202602U UA73100U (en) 2012-03-05 2012-03-05 Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201202602U UA73100U (en) 2012-03-05 2012-03-05 Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number

Publications (1)

Publication Number Publication Date
UA73100U true UA73100U (en) 2012-09-10

Family

ID=50850396

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201202602U UA73100U (en) 2012-03-05 2012-03-05 Shaper of periodic sequence of pulses with programmable width and pulse ratio equal to whole number

Country Status (1)

Country Link
UA (1) UA73100U (en)

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