UA72601U - Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets - Google Patents

Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets

Info

Publication number
UA72601U
UA72601U UAU201201043U UAU201201043U UA72601U UA 72601 U UA72601 U UA 72601U UA U201201043 U UAU201201043 U UA U201201043U UA U201201043 U UAU201201043 U UA U201201043U UA 72601 U UA72601 U UA 72601U
Authority
UA
Ukraine
Prior art keywords
packets
shaper
pause
pulses
packet
Prior art date
Application number
UAU201201043U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Николай Григорьевич Коробков
Елена Николаевна Коробкова
Василий Григорьевич Рубанов
Вячеслав Сергеевич Харченко
Original Assignee
Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт" filed Critical Национальный Аэрокосмический Университет Им. Н.Е.Жуковского "Харьковский Авиационный Институт"
Priority to UAU201201043U priority Critical patent/UA72601U/en
Publication of UA72601U publication Critical patent/UA72601U/en

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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A shaper of periodic sequence of packets of pulses of fixed width equal to one cycle with adjustable pulse number in a packet and a pause between the packets contains: two binary counters, first of which has a clock input, a counting mode enable input, an asynchronous reset, the second counter is a reversible countdown counter having a synchronous parallel load enable input and a loading data input, an asynchronous reset, an overflow output, an inverter, first and second element OR, a circuit element comprising in series connected resistor and capacitor, a synchronous D flip-flop having asynchronous reset, first and second two-input elements AND. The third reversible counter is introduced.
UAU201201043U 2012-02-01 2012-02-01 Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets UA72601U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201201043U UA72601U (en) 2012-02-01 2012-02-01 Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201201043U UA72601U (en) 2012-02-01 2012-02-01 Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets

Publications (1)

Publication Number Publication Date
UA72601U true UA72601U (en) 2012-08-27

Family

ID=50849857

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201201043U UA72601U (en) 2012-02-01 2012-02-01 Shaper of periodic sequence of packets of pulses of fixed width equal to one cycle, with adjustable pulsenumber in packet and pause between packets

Country Status (1)

Country Link
UA (1) UA72601U (en)

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