UA70755U - Buffer stage - Google Patents

Abstract

A buffer stage comprises ten transistors, two current sources, positive and negative power distribution buses, input and output buses, the input bus is connected to buses of fourth and fifth transistors, collectors of second and seventh transistors are connected to buses of positive and negative power distribution buses respectively, second terminals of first and second current sources are connected to positive and negative power distribution buses respectively. Buses of first and eighth transistors are connected to the buses and collectors of third and sixth transistors respectively, the collectors and buses of ninth and tenth transistors are united one to another, as well as to the collectors of forth and fifth transistors and connected to the output bus. Eleventh, twelfth, thirteen, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth transistors are introduced.