UA36645C2 - Digital filter with linear delta modulation - Google Patents

Abstract

The proposed DIGITAL filter with linear delta modulation contains a delta modulator (1), four pulse counters (2 … 5), a timing pulse generator (6), a register (7), two data registers (8, 9), a random access memory (10), a read-only memory (11), a multiplexer (12), a NOT-AND logic element (13), two accumulators (14, 15), and a digital-to-analog converter (16). The present invention provides for increasing speed of response and resolution of the filter.

Description

Description of the invention

The invention belongs to computer technology and can be used in devices for digital processing of 2 signals and industrial control systems with delta modulation and pulse-code modulation of random processes, for example, in digital filtering and spectral analysis.

Known digital non-recursive filters containing a shift register, coefficient memory unit, multipliers, adders, registers and perform digital filtering of signals with pulse-code modulation (PCM) by multiplying multi-bit counts of the input signal by multi-bit weighting factors and summing up 70 multiplication results | 11.

The disadvantage of such filters is that for the high accuracy of the implementation of the amplitude-frequency characteristic, a high bit rate of coefficients and counts of the input signal is used, which, along with a larger amount of hardware costs for the memory block of coefficients, multipliers and a shift register, reduces the speed of the filter due to higher costs time to perform the multiplication operation. The use of matrix 19 multipliers in such filters allows to increase the speed of operation, but leads to an increase in hardware costs.

A digital filter with linear delta modulation (LDM) is also known, which contains a pulse generator, a pulse distributor, the first and second counters, a pulse shaper, blocks of permanent and random access memory, the first and second reversible counters, element I, first - third adders , first and second accumulating adders, first and second buffer registers, EXCLUSIVE OR element, leading edge shaper, multiplexer |21.

In this digital filter, both the input signal and the weighting coefficients are presented in the format of linear delta modulation, which made it possible to obtain the maximum simplification and high speed of the multiplication operation. Pre-transformation of the impulse characteristic made it possible to sharply reduce the number of non-zero members, which reduced the number of operations for calculating the digital convolution of signals in the format of linear s 29 delta modulation. Gee)

However, in each operating cycle of a known device, a significant part of the time is spent on forming a sequence of addresses of permanent and RAM blocks. This is explained by the fact that sequences of addresses of memory blocks in a known device are formed using counters, a permanent memory block and an adder, which leads to a delay in the formation of addresses proportional to the total delay of signal propagation in these 30 blocks, which means that it leads to significant unproductive expenditure of time and the corresponding limitation of speed of "I known device. In addition, the speed of the known digital filter is limited by a significant number of arithmetic operations performed in the filter per unit of time. Reduction of unproductive time spent in each cycle and ee, reduction of the number of cycles for calculating the output signal of the filter allows to increase the speed of operation, but it cannot be implemented in this device. 3о The closest to the proposed invention, in terms of technical essence, is a digital filter with linear o delta modulation, containing a linear delta modulation modulator, the information input of which is the filter input, a multiplexer, the first information input of which is combined with the information input of the block RAM block Y is connected to the output of the modulator, the output of the RAM block is connected to the second information input of the multiplexer, the permanent memory block, the output of which and the output of the multiplexer Z 40 are connected to the first and second inputs of the equivalence element, the output of which is connected to of the control input from the reversing counter, the outputs of which are connected to the information inputs of the first accumulating adder,

From" the outputs of which are connected to the information inputs of the second accumulating adder, the outputs of which are connected to the inputs of the digital-to-analog converter, the output of which and the outputs of the second accumulating adder are the second and first outputs of the filter, the clock generator, the output of which is connected to the counter inputs of the reversible and 45 of the first binary counter, the first input of the pulse generator and the enable input of the PROHIBITION element, the output of which is connected to the counting input of the second binary counter, the outputs of the digits of which are connected

Ge") to the inputs of the permanent memory block and the OR-NOT element, the output of which is connected to the control inputs of the multiplexer and the RAM block, the address inputs of which are combined with the inputs of the I element and would be connected to the bit outputs of the first binary counter, the overflow output of which is connected to the clock input "iz" 20 of the modulator, the output of element | connected to the prohibition input of the PROHIBITION element and the second input of the pulse generator, the output of which is connected to the clock inputs of the first and second accumulating adders |ZI. sl In this filter, unproductive time spent on forming a sequence of addresses of permanent and RAM blocks is excluded - these sequences are formed synchronously, which, along with the use of the linear delta modulation format for presenting the input signal and weighting sequence, made it possible to ensure a sufficiently high speed of the device.

GF) However, during the discretization period, a significant number of arithmetic operations (equal to the length of the weight sequence) are performed in the known filter, which does not allow to obtain a higher speed.

We should also note that the low bit rate of the weight sequence in the format of linear delta modulation - equal to one, prevents the increase in the resolution of the filters known from |2, З). The use of a weighted 60 sequence with a higher bit rate, for example, in the format of multilevel delta modulation (LDM), allows to increase the resolution, but leads to a decrease in performance due to the need to perform multiplication operations.

The invention is based on the task of improving a digital filter with linear delta modulation by means of structural optimization, which allows to achieve an increase in speed and resolution of a digital filter with linear delta modulation.

The task is solved due to the fact that due to the introduction of a shift register, the first and second buffer registers, the third and fourth counters and the corresponding connections into the known device, the input signal is processed in the format of linear delta modulation using a weight sequence in in the format of multilevel delta modulation, with the sampling frequency of the input signal, characteristic of linear delta modulation. The output signal of the digital filter is presented in the format of pulse-code modulation with a sampling frequency characteristic of this type of (PCM) modulation.

Thus, due to such a presentation of signals, ensured by the introduction of the specified blocks and connections, the number of arithmetic 70 operations per unit of time in the proposed filter is significantly less than in the prototype, which significantly increases its speed. In addition, elementary additions are grouped in the proposed device into groups and are performed simultaneously in each group by tabular transformation for the entire group according to the digital convolution formula. This makes it possible to drastically reduce the number of arithmetic operations performed according to the digital convolution formula (much less than the length of the weight sequence), as well as to replace their execution by reading from the memory block, which also leads to a corresponding increase in performance. At the same time, such a replacement /5 allows you to REMOVE the restriction on the bitness of the weight sequence and obtain any predetermined resolution of the digital filter by changing the bitness of the weight sequence (changing the contents of the permanent memory block). In addition, we note that another factor in obtaining high performance of the proposed filter is the complete exclusion of unproductive time spent in each cycle and ensuring the synchronous formation of addresses of permanent and RAM blocks.

The essence of the invention is that a digital filter with linear delta modulation contains a clock generator, a linear delta modulation modulator, the information input of which is the filter input, a multiplexing block, the first information inputs of which are connected to the outputs of the RAM block, the first accumulating adder , the outputs of which are connected to the information inputs of the second accumulating adder, the outputs of which are the first outputs of the filter and are connected to the inputs of the digital-to-analog converter, the output of which is

Is the second output of the filter, the first counter, the bit outputs of which are connected to the address inputs of the RAM unit, the control input of which is combined with the control input of the multiplexing unit and i) is connected to the output of OR-NOT elements, the inputs of which are combined with the first address inputs of the permanent memory block and connected to the bit outputs of the second counter, and also contains a shift register, the first and second buffer registers, the third and fourth counters, the information input of the shift register is connected to the output of the Modulator, the bit outputs of the shift register are connected to the information inputs of the first buffer register, the outputs of which are connected to the information inputs of the RAM block and the second information inputs of the multiplexing block, the outputs of which are connected to the second address inputs of the permanent memory block, the outputs of which are connected to the information inputs the first accumulating adder, the clock input of which is combined with the counter inputs of the first and second counters nicks and connected to the overflow output of the fourth counter, the counter input of which is combined with the input of the same name of the third counter and connected to the output of the clock generator, the overflow output of the third counter is connected to the clock inputs of the modulator and the shift register, the clock inputs of the first and second buffer registers are combined with the clock input of the second accumulating adder, the presetting permission input of the first counter and are connected to the output of the OR-NO element, the information inputs of the second buffer register are connected to the bit outputs of the first counter, the information inputs of which are connected to the outputs of the second buffer register. There is a close cause-and-effect relationship between the entire set of essential features and the specified technical result. The designated blocks entered into the device are known and widely used. However, only theirs;" inclusion in a known device allows you to discover new properties in it, and their functional relationship contributes to the achievement of the expected technical result.

Fig. 1 shows the functional diagram of the digital filter, Fig. 2 shows the time diagrams of operation 2) of the filter.

A digital filter with linear delta modulation contains (Fig. 1): modulator 1 of linear delta modulation

Me, (LDM), first - fourth counters 2 - 5, clock generator b, shift register 7, first and second 8, 9

Ge" buffer registers, unit 10 of RAM, unit 11 of permanent memory, unit 12 of multiplexing, element 13 OR-NOT, first and second 14, 15 accumulating adders, digital-to-analog converter 16. In Fig. 1 pi are marked input 17, first and second outputs 18, 19 of the filter. Fig. 2 shows the following signals: a - clock pulses from generator 6, b - pulses at the overflow output of counter 4, c - change of quantization steps at the output of modulator 1, d - pulses at the overflow output of counter 5, (Ф) d - pulses at the output of the element 13 OR-NO, ka e - change of signals at the outputs of the multiplexing block 12, z - the state of the counter 3. In the signals (Fig. 2 e, g), the addresses of memory blocks 10 and 11 are conventionally shown. Modulator information input 1

LDM is the input 17 of the filter, the output of the modulator 1 is connected to the information input of the shift register 7, the bit outputs of which are connected to the information inputs of the first buffer register 8.

The first information inputs of the multiplexing block 12 are connected to the outputs of the RAM block 10, the information inputs of which are combined with the second information inputs of the multiplexing block 12 and connected 65 TO the outputs of the first buffer register 8. The first inputs of the block. 11 non-volatile memories are combined with element inputs. 13 OR-NO and connected to the bit outputs of the second counter 3. The second inputs of block H of permanent memory are connected to the outputs of the block. 12 multiplexing, the outputs of the permanent memory units 11 are connected to the information inputs of the first 14 accumulating adder, the outputs of which are connected to the information inputs of the second 15 accumulating adder, the outputs of which are the first 18 filter outputs, and are connected to the inputs of the digital-to-analog converter 16, the output of which is the second 19 output of the filter. The output of the clock generator 6 is connected to the counter inputs of the third and fourth counters 4 and 5, the overflow output of the latter is connected to the clock input of the first accumulating adder 14 and the counter inputs of the first and second counters 2 and 3. The overflow output of the third counter 4 is connected to the clock inputs of the modulator 1 and register 7 shift. The address inputs of the RAM unit 10 are combined with the information inputs of the second 70 buffer register 9 and are connected to the bit outputs of the first counter 2, the information inputs of which are connected to the outputs of the second buffer register 9. The clock inputs of the first and second buffer registers 8, 9 about connected to the control inputs of the RAM unit 10, the multiplexing unit 12, the clock input of the second accumulating adder 15, the input of the permission to pre-set the first counter 2 and connected to the output of the element 13 OR NO.

The proposed device works as follows.

The following algorithm is implemented in a digital filter with linear delta modulation.

It is known |4) that the sampling frequency for linear delta modulation is тТ-1.. Shte", where Тр is the frequency

Nyquist, M » 1 - a coefficient that depends on the properties of the input signal and the parameters of the delta modulator.

At a given sampling frequency t"!, the modulator efficiently processes the frequency band (0, t ), which is ensured by the appropriate limitation of the signal spectrum at the modulator input within the specified limits using a low-pass filter. Thanks to this, at the same time, the operation of the modulator in the steepness overload mode and the absence of nonlinear distortions in the transformed signal. Thus, the presence of the indicated limitation of the spectrum of the input signal allows for decimation (reduction) of the sampling frequency t" of the input EM signal

VR « M times, i.e. the spectrum of the thinned signal will not be wider than the input one, but belongs to the band d) frequencies mentioned above (0, tya! ), which means that there will be no overlapping of the spectrum. Therefore, during the decimation of delta-modulated signals in Р « M times, with the limitation of the upper frequency of the spectrum of the input signal by the frequency т , there is no need to carry out preliminary low-frequency filtering of delta-modulated signals, IC o)

Of which is usually used before decimation of signals with pulse-code modulation (5). -

Reducing the sampling frequency allows for the same element base to increase the resolution of the filter, due to the possibility of implementing more complex filtering algorithms, for example, by increasing the length and bit rate (|b| of the weight sequence, or increasing the speed of the filters by sharply reducing |se)

From the number of operations performed in the filter per unit of time. Moreover, reducing the sampling frequency of the digital filter also allows you to sharply reduce the speed requirements for the equipment for further processing of the output signal of the digital filter and, thanks to this, to increase its bandwidth.

The output signal of a digital filter with linear delta modulation, the input signal of which is presented in the format of linear delta modulation (LDM), and the weight sequence - in the format of multilevel delta modulation (BDM) with a sampling frequency of T7, and the output signal is presented in the format of pulse -code modulation (ICM) with a lower sampling frequency t" -t Irkh tya, on the basis of (7, 8), is written in the form 0-1 - weighted BDM, ud), n » 0 - output PCM of the sequence, p « M - thinning coefficient. (22) Dividing the convolution (1) into two consecutive sums, we obtain the algorithm implemented in the filter:

F p (

ЧК» 50 Mp - VAM, i-th sl and mA K chu - XX, vk pa,

Cogigttny or i

GF) tu Uh uk

Kk-i o de 2 J MA a z t - X VEyu pev . 60 PT)

This algorithm is implemented as follows.

Before starting filtering, it is necessary to reset the accumulating adders 14, 15 and counters 2 - 5 (the reset circuits in Fig. 1 are not shown). At the same time, zero signal values are set on analog 19 and digital 18 outputs. Such zeroing must also be carried out in case of random failures, for example, at 65 power supply, to avoid the accumulation of errors in the output signal of the filter. At the same time, the values of P-bit words consisting of a sequence of values (0, 1) are entered into registers 7, 8 and memory block 10.

Generator 6 generates a continuous sequence of pulses (Fig. 2a) with a frequency of 7 - M / rt", where M is the length of the weight sequence, p is the thinning coefficient, T is the sampling frequency of the input signal in the format

LDM Moreover, the transition that causes a change in the state of counters 2 - 5 is a transition at their counter input from a single state to zero, that is, the change in the state of the counters occurs along the trailing edge of the signal at their counter inputs. We will also assume that the recording of the signal value from the information inputs of register 9 takes place on the trailing edge of the signal on its clock input, and the recording of the signal value from the information inputs of counter 2 takes place on the leading edge of the signal on its presetting permission input.

Pulses (Fig. 2a) are received at the counting input of counter 4 with the division factor M/r (M - Otov(r)) at the 70th overflow output of which a sequence of pulses (Fig. 2b) with a frequency of T 7 is formed. After each pulse (Fig. .26), which enters the clock input of the modulator 1, at its output the value of the quantization step of the input signal (with a spectrum limited by the upper frequency tya! ) (fig. 2c) is fixed in the n-th sampling period -

YOU VabO - (1 same edbO) / 2, VybO is 40, 1), db is (1, 1), which is stored at the output of blocks 1 until the arrival of the next 75 pulse (Fig. 2b) from the overflow output of counter 4. Sequence of steps quantization of the input signal (Vas, po» 0 is received at the information input of the shift register 7, as a result of which in the n-th sampling period a value is formed on the bit outputs of the block 7 from P successive values of the quantization steps of the drivers. These values are given in the form of a p-bit code to the information inputs of the first 8 buffer registers, with a bit rate of r.

The sequence of pulses (Fig. 2a) from the generator b is also supplied to the counter input of the counter 5, which has a division ratio p. At the overflow output of the counter 5, a sequence of pulses (Fig. 2d) is formed with a frequency of T7 7 M/rg, that is, with a frequency of during which M/r pulses are formed during the period of TE rt at the overflow output of counter 5. Pulses (Fig. 2d) are received at the inputs of counters 2 and З, which have a coefficient of division M/r. Signals from the bit outputs of the counter З arrive at the inputs of element 13 OR-NOT, which isolates the zero state of counter 3. On the leading edge of the signal (Fig. 2d) from the output of element 13 OR-NOT in register 8 i) a p-bit word formed is recorded with P successive values of the quantization steps of the input signal.

At the same time, the value of the output signal of the second buffer register 9 is written to the counter 2 on the same signal edge (Fig. 2e), and the signal value from the bit outputs of the counter 2 is written to the register 9, which provides circulation of the addresses of the memory blocks 10 and 11 - in each subsequent time interval rt"! the addresses of the memory block 10 are shifted by one unit in the direction of advance relative to the addresses M of the memory block 11. Ge)

The signal (Fig. 2d) is the control for the RAM block 10 and the multiplexing block 12 - at a high level of this signal, the block 10 switches to the recording mode, and the block 12 switches to the position in which the signal from the 3З35 OUTPUTS of the register 8 arrives at the second inputs of the memory block 11. co

Thanks to the recirculation of the addresses of the memory block 10 relative to the signal at the bit outputs of the counter Z, the value from the outputs of the register 8 to the memory block 10 is written at the address | - Ktod (M / R). At a low signal level (Fig. 2d), block 10 switches to the reading mode and the signal from its outputs through the multiplexing block 12 enters the second inputs of the memory block 11. Therefore, during the time period T; - rt to the second inputs of block « 11 a sequence of M/r P-bit words, formed by steps of quantization of the input signal - s (wolf VO di KOKO. Let's denote this word by 8.0). Then, during the time rt, the second inputs of the memory block 11:z" receive M/r values 52) recorded in the memory block 10 at the addresses | - (d i- K) tod(M / R), h- Mr, that is, the sequence of values (5.29) g - K - (M / R -1)to4(M / R), where 4 is the signal on the digit counter outputs 3.

In memory block 11, partial sums about vro, (22) from ter and about de d-yM/r-i, 7 signal values at the digit outputs of the counter Z, which are read from block 11 according to their 20 values of vk, which correspond to steps of quantization of the input signal of geo unit-1. For this sp, the address field (first inputs) of the memory block 11 is divided into M / R groups, which are addressed by the signal values at the bit outputs of the counter Z, and the specific value of VU is read from the memory block 11 by the values of the corresponding quantization steps vk, coming to the second inputs of the memory block 11. The recording of the values of VU, о is carried out consecutively, starting from the zero address of block 11 according to increasing addresses, and the m/th group of values ger) uue(0,M/r-1) is addressed by the value of the signal at the bit outputs of the counter With the next ko K-sh as follows: m - (M / r - ad)tod(M/r), Ch- b M7r-1. 60 The signal from the outputs of the block 11 enters the information inputs of the first adder 14, therefore, at the end of the K-th time interval of the accumulation of rt at the outputs of the block 14, the value of the internal sum (2) is formed in the n - K-th sampling period: hm - K-(M /R - a) tod(M / R) -(M/R - a) tod(M / R) - K.

The indicated relationship between the indices of the sequences yvkOO) and (vu) ) at the corresponding addresses of memory blocks 10 and 65 11 is illustrated in Fig. 2 for the case Ktod(M / r) - 0.

At the end of the running period, the value accumulated in the adder 14 is written to the adder 15, where it is summed up with its previous value. In the next, K-1st period, the value of the signal at the outputs of block 14 will change by the value of the value, therefore, after K periods of rt, taking into account the zero initial value, the signal at the outputs of adder 14 will be equal to Uuk. Thus, in 95 adder 14, combined functions of two successive accumulating adders, i.e. formation of the value of ХУук according to (2). Accumulation of Tuuyu values in the adder 15 gives according to (1) the value of the output signal of the CHUK filter) in PCM format, which is converted by the digital-to-analog converter 16 into the analog form y() and is fed, respectively, to the first and second outputs 18 and 19 of the filter. 70 When filtering periodic signals, the output signal of the filter, as well as the first difference (2) are periodic functions of time, and the absence of overflow of the adder 14 is ensured by choosing its bit rate from the condition of the maximum value of the amplitude of the first difference.

Therefore, during time T; - rt (the period of receipt of the output readings of the filter in PCM format), in the proposed device, M / R arithmetic operations of summing tabular values are performed (U to calculate 19 of the first difference (2). In the prototype and similar devices, M similar operations are performed during the period T, which shows the high efficiency of the proposed device - the number of arithmetic operations per unit of time is reduced by P? times. Taking into account that the summation of tabular values is carried out, which are calculated in advance and stored in block 11 of permanent memory, the time spent on summation in the prototype and the declared device can be taken as equal. This allows us to conclude that this device has a p? times higher speed, or, equivalently, it allows processing of input signals with a wider, P2 times, band at a given sampling frequency T7 and the corresponding limitation of the input spectrum signal

The summation of tabular values (U) allows you to choose any resolution of the filter that satisfies the given weighting coefficients (ЭЙ. Moreover, changing the bitness of the weight sequence does not change the speed of the filter, but only leads to a change in the content of block 11 of the permanent memory, which can be Ge) is easily performed on the PZP. For example, with the length of the weight sequence M - 256 and the coefficient p - 8, the required division coefficient of the counter Z is equal to M/ p - 256/8 - 32, which is provided by a five-digit counter.

The necessary number of inputs of the memory block 11 in this case is equal to г - r ж Isdo(M/r) - 13 and is implemented by a single microcircuit of type 556RT16 with a memory volume of C - 213 cells.

Note that for the given example, the speed of the proposed digital filter with linear delta modulation is higher than that of the prototype, in P? -64 times while simultaneously increasing the resolution of Ge by choosing the appropriate resolution of the weight sequence. The length of the weight sequence is M - 256 in format

BDM allows you to get high-quality processing of any complex input signal. ise)

Thus, the use in the known device of counters 4, 5 and registers 7 - 9 with the corresponding co connections made it possible to increase the speed and increase the resolution of the digital filter with linear delta modulation. Other blocks can be made similarly to the prototype.

SOURCES

1. Rabiner L. Gould V. Theory and application of digital signal processing / Trans. with English Ed. Y.N. "

Aleksandrov. - M.: Mir. - 1978. - 848 p. from p. 2. A.S. Mo1424119 of the USSR, MKY NOZNI7/06, NOZM3/02. Digital filter with linear delta modulation /

Tymchenko A.V. (USSR). Mo4140738/24-24; Application 29.10.86. Publ. 15.09.88, Bull. Moza4. - 6 s. ;" Z. A.s. Mo1425841 USSR, MKY NOZM33/02, NOZNI17/06. Digital filter with linear delta modulation /

Tymchenko A.V. (USSR). Mo4219944/24-24; Application 31.03.87. Publ. 23.09.88, Bull. Mo35. - bs. 4. Volkomirskaya L.B., Pohrybnoi V.A., Reznikov A.V., Timchenko A.V. Methods of digital filtering 2) geophysical signals / Preprint Mo49(659). - M.: IZMYRAN., 1986. - Z5p. 5. R.V. Croshier, L.R. Rabiner. Interpolation and decimation of digital signals: Methodical review //

Me. TIYZR. - 1981. - Vol. 69, Moz - P. 14 - 49.

Ge» 6. Pohrybnoi V.A., Tymchenko A.V. Calculation of digital filters with delta modulation // Radioelectronics. - 1988. - T31, Mo3. - P. 15-21. ve 7. Pohrybnoi V.A. On-board systems! signal processing - Kyiv: Nauk, dumka, 1984. - 216p. - P. 88 - 89. sp 8. Tymchenko A.V. New methods of digital filtering of delta-modulated signals //

Radio electronics. - 1998. - T.41, Mo9, - p. 41-48.

Claims (1)

Formulation of the invention F) GI Digital filter with linear delta modulation, containing a clock generator, a linear delta modulation modulator, the information input of which is the filter input, a multiplexing block, the first information blocks whose inputs are connected to the outputs of the RAM block, the first accumulating an adder, the outputs of which are connected to the information inputs of the second accumulating adder, the outputs of which are the first outputs of the filter and are connected to the inputs of the digital-to-analog converter, the output of which is the second output of the filter, the first counter, the bit outputs of which are connected to the address inputs block of RAM, the control input of which is combined with the control input of the multiplexing block and connected to the output of the OR-NOT element, the inputs of which 65 are combined with the first address inputs of the permanent memory block and connected to the bit outputs of the second counter, which differs in that the shift register, the first and second buffer registers, the third and fourth counters, the information input of the shift register is connected to the output of the modulator, the bit outputs of the shift register are connected to the information inputs of the first buffer register, the outputs of which are connected to the information inputs of the RAM block and the second information inputs of the Multiplexing block, the outputs of which are connected to the second address inputs of the permanent memory block, the outputs of which are connected with the information inputs of the first accumulating adder, the clock input of which is combined with the counter inputs of the first and second counters and is connected to the overflow output of the fourth counter, the counter input of which is combined with the input of the same name of the third counter and is connected to the output of the clock generator, the overflow output of the third counter connected from the clock we are the inputs of the modulator and the 7/o Shift register, the clock inputs of the first and second buffer registers are combined with the clock input of the second accumulating adder, the input of the permission to pre-set the first counter and are connected to the output of the OR-NO element, the information inputs of the second buffer register are connected to the bit outputs of the first counter, the information inputs of which are connected to the outputs of the second buffer register. with more 6) IF) « (Se) (Se) so - and? (95) (o) (o) sh» sl ime) 60 b5