UA127443C2 - DIGITAL FREQUENCY METER - Google Patents

Abstract

A digital frequency meter belongs to control and measurement equipment and can be used to measure frequency in the range from low to ultra-high frequencies. The digital frequency meter contains an input shaper, a D-trigger, two logical AND elements, a sample frequency generator, two counters, a calculation and control unit, made with the possibility of setting the value of the quantization error, and a frequency divider. Additionally, an EXCLUSIVE OR logical element is introduced, the output of which is connected to the first input of the second logical element AND, the second input of this element is connected to the output of the sample frequency generator and the input of the frequency divider. The first input of the logic element is EXCLUSIVE OR connected to the output of the D-trigger, the first input of the first logic element AND and the input of switching the direction of counting pulses of the second counter. The second input of the logic element is EXCLUSIVE OR connected to the output of the frequency divider and the D-input of the D-flip-flop, and the C-input of the D-flip-flop is connected to the second input of the first logic element AND and directly or indirectly to the output of the input shaper, the input of which is device input. The outputs of the first and second logic elements AND are connected to the inputs of the first and second counters, respectively, the outputs of the two counters are connected to the inputs of the calculation and control unit, the output of which is connected to the sample frequency generator and the frequency divider. Two series-connected dividers by 10 and a multiplexer, which is made with the ability to receive a sequence of pulses from the output of the input shaper, which are fed to the "0" input of the multiplexer and the input of the first divider, and a sequence of pulses from the output of the first divider, which are fed to the input "1" of the multiplexer and the input of the second divider, and the sequence of pulses from the output of the second divider, which are fed to the input "2" of the multiplexer, which is made with the ability to provide a signal for selecting the division coefficient of the input sequence of pulses from the calculation and control unit to the address inputs of the multiplexer, and the output of the multiplexer is connected to the C-input of the D-trigger and the input of the first logic element I. Technical result: performing an adaptive change of the clock frequency of the sample generator depending on the measurement conditions and reducing the methodical error of the frequency measurement.

Description

trigger and the input of the first logical element I. Technical result: implementation of adaptive change of the clock frequency of the sample generator depending on the measurement conditions and reduction of the methodical error of the frequency measurement. bi nn: deya va ZK o t EV Ya nn Z

Fig.

The invention belongs to control and measurement technology and can be used to measure frequency in the range from low to ultra-high frequencies.

A known digital frequency counter 1), which includes an input signal reception port that converts the input signal into a sequence of pulses, a first counter equipped with a first reading register, a measurement period pulse reception port and a first synchronization circuit through which the output of the measurement period pulse reception port with connected to the control input of the first reading register, a sample frequency generator, forming sample pulses, a second counter provided with a second reading register, processing and indication means, as well as an inverter and a second synchronization circuit, while the input signal receiving port is connected through the second circuit synchronization with the clock input of the first counter, the sample frequency generator is connected: to the clock input of the second counter, to the clock input of the second synchronization circuit and through the inverter to the clock input of the first synchronization circuit, the control input of the second reading register is connected to the output of the first synchronization circuit, and the outputs of each counter are connected through counter reading registers to the means of processing and indication.

Synchronization circuits are designed in such a way that in response to each input pulse they form an output pulse, the edge of which coincides with the leading edge of the pulses that are fed to their clock inputs.

A significant disadvantage of such a frequency meter is a large methodical error of frequency measurement and a limited range of frequency measurement.

At the same time, the upper limit of Ekhitah of this range is determined by the formula:

Ekhtakh-"0.5T0, (1) and the lower limit Ekhtip of the frequency measurement range of this device is determined by the following formula:

Ekhtip 21/(bd"Tc), (2) where o is the sample clock frequency, bd is the relative error of the frequency measurement,

Tc is the time required to measure the frequency with a given error.

At 0-1 MHz, Tc-0.01 sec., bd-:0.1 95 we will have Echtip2100 kHz and Echtach"500 kHz

The closest to the proposed digital frequency counter is a device (|2| for measuring frequency, which contains an input shaper, an O-trigger, two logic elements Y, a sample frequency generator, two counters and a frequency divider, the output of which is connected to the YO input of the trigger , the output of which is connected to the inputs of the first and second logic elements AND, the output of the second logic element AND is connected to the second counter, the output of the first logic element I! is connected to the first counter, the output of the sample frequency generator is connected to the input of the frequency divider, and the C-input trigger - with the second input of the first logical element | and the output of the input shaper, the input of which is the input of the device, and the outputs of the first and second counters are the outputs of the device, according to the invention, a second controlled frequency divider and a calculation and control unit with the possibility of setting the value of the quantization error are introduced, at the same time, the output of the division coefficient setting of the calculation and control unit is connected to the corresponding input of the second frequency divider, the first input of which is connected to the output of the clock frequency generator and the input of the first frequency divider, the output of the second frequency divider is connected to the second input of the second logic element I, the outputs of two counters are connected to the inputs of the calculation and control unit.

This allows you to adaptively set the desired sample clock frequency in accordance with the predetermined quantization error, ensuring clock frequency redundancy and reducing the power consumption of the integrated microcircuits of the frequency meter, but this device has a large methodical error of frequency measurement.

The basis of the invention is the task of creating a device for measuring frequency, which would provide for the possibility of adaptively changing the clock frequency of the sample generator depending on the measurement conditions and reducing the methodical error of measuring the frequency.

The task is solved by the fact that the digital frequency meter contains an input shaper, an O-trigger, two AND logical elements, a sample frequency generator, two counters, a calculation and control unit with the possibility of setting the value of the quantization error and a frequency divider, entered, an EXCLUSIVE OR logical element, output which is applied to the first input of the second logic element AND, the second input of this element is connected to the output of the sample frequency generator and the input of the frequency divider, and the first input of the logic element is EXCLUSIVE OR connected to the output of the U-flip-flop, the first input of the first logic element AND and by the input for switching the direction of pulse counting of the second counter, the second input of the logic element EXCLUSIVE

OR is connected to the output of the frequency divider and the Y-input of the flip-flop, and the C-input of the flip-flop is connected to the second 60 input of the first logic element AND and directly or indirectly to the output of the input shaper, the input of which is the input of the device, and the outputs of the first and second logic elements And connected to the inputs of the first and second counters, respectively, the outputs of the two counters are connected to the inputs of the calculation and control unit, the output of which is connected to the generator of the sample frequency and the divider to control the output frequency of the generator and the division coefficient of the divider when forming the sample time interval.

This allows you to adaptively set the desired sample clock frequency according to the preset quantization error.

The drawings explain the essence of the invention.

In fig. 1 shows the structural diagram of the proposed frequency meter.

In fig. 2 time diagrams of frequency measurement.

Fig. 3 shows the scheme of a frequency meter with an extended frequency range of measured frequencies.

The proposed frequency counter contains input shaper 1, O-trigger 3, two logic elements

And 6,7, sample frequency generator 5, two counters 8, 9, and counter 9 is reversible, calculation and control unit 10, divider 2 and logic element EXCLUSIVE OR 4.

The periodic signal, the frequency of which must be measured, is fed to the input of the input shaper 1, which forms a sequence of rectangular pulses with steep fronts and slices (Fig. 2a).

The formed pulse sequence is fed to the clock C-input of the Y-trigger Z, the Y-input of which is gated from the output of the frequency divider 2, which forms the first time interval To (Fig. 26).

At the same time, a second sample time interval To" (Fig. 2d) is formed at the output of the U-trigger Z, such that its edge corresponds to the pulse of the sequence that appeared immediately after the beginning of the first sample interval, and the cut corresponds to the pulse that occurred immediately after the end of the first sample time interval. The first time interval To is filled with pulses of their input frequency (Fig. 2c) and is counted by counter 8. Signals To and To' are applied to the inputs of the logic element

EXCLUSIVE OR 4 forms at its output two time intervals (Fig. d2d), which are filled with the sample frequency io (Fig. 2e) and are fed to the input of the second counter 9 (Fig. 26). During the first interval at the output of the counter 9, the code will decrease by the number t, during the second - increase by the number k. During the formation of the sample interval, the divider 2 counts M pulses of the sample frequency io (Fig. 2g). In this way, the first sample interval is measured more accurately frequency measurement time.

In accordance with the desired quantization error, the sample clock frequency is determined: to-1ATo"bahi), (3) where To is the first sample time interval.

In addition, the sample frequency is selected so that it is at least 10 times higher than their input frequency.

After that, the calculation and control unit 10 calculates the unknown frequency of them according to the formula: ih-p"ToDM-t-K) (4).

The described frequency meter can measure the maximum frequency, which is calculated according to formula 1.

At t0-100 MHz Ekhitakh«e50 MHz.

To expand the range of input frequencies between input shaper 1 and the rest of the frequency meter circuit, we introduce additional dividers 11, 12 and multiplexer 13 so that the sequence of pulses from the output of input shaper 1 is fed to input "0" of multiplexer 13 and the input of divider 11, the sequence of pulses from the output of the divider 11 is fed to input "1" of multiplexer 13 and the input of divider 12, and the sequence of pulses from the output of divider 12 is fed to input "2" of multiplexer 13. Dividers 11 and 12 have a division factor of 10. The output of multiplexer 13 is connected to the C-input of the trigger With and input of logic element I 6. The signal for selecting the division coefficient of the input sequence of pulses is fed from the calculation and control unit 10 to the address inputs A and B of the multiplexer 13. The circuit of a frequency meter with an extended frequency range of measured frequencies is shown in fig. 3.

In addition to the described frequency meter, this method of measuring the frequency can easily be implemented on ARM microcontrollers of the 5IMZ2 (5TM) family, in which the clock frequency of the generators can be changed by software loading into the corresponding registers the numbers of multiplication and division of the frequency of the quartz generator. The system of clocking and formation of the reference frequency of microcircuits of 32-bit AVM-microcontrollers of the 5ТМ32 family is described in work |З).

The technical result obtained after the introduction of the above changes is an increase in the accuracy of signal frequency measurement. Thus, when measuring the frequency of the AOSOUZA-10.00 MHz generator with a short-term stability of 5-1079, we obtained at 10-100 MHz, M-10000000, t-10, K-9 and a measurement time of 1 sec. the reading of the frequency meter is 10000000.1 MHz and the methodological error of the frequency measurement is 10,

Sources of information: 60 1. Patent VO 2210785 СХ018 23/10.

2. Patent OA 79849 2018 23/00. 3. O.

Valpa. "Modern 32-bit AVM-microcontrollers of the 5TMZ32 series: clocking system", Sovremennaya zlektronika, Mo 6, 2013. P. 18-22.

Claims (2)

FORMULA OF THE INVENTION 1. A digital frequency counter containing an input shaper, a SW flip-flop, two logic elements |, a sample frequency generator, two counters, a calculation and control unit, made with the possibility of setting the value of the quantization error, and a frequency divider, which is distinguished by the fact that it contains additionally introduced logic element EXCLUSIVE OR, the output of which is connected to the first input of the second logic element AND, the second input of this element is connected to the output of the sample frequency generator and the input of the frequency divider, and the first input of the logic element EXCLUSIVE OR is connected to the output O -trigger, the first input of the first logic element and the input of switching the direction of pulse counting of the second counter, the second input of the EXCLUSIVE OR logic element is connected to the output of the frequency divider and the O-input of the O-trigger, and the C-input of the JO-trigger is connected to the second input of the first logical element AND and directly or indirectly with the output of the input shaper, the input of which is the input of the device, and the outputs of the first and second logical elements | connected to the inputs of the first and second counters, respectively, the outputs of the two counters are connected to the inputs of the calculation and control unit, the output of which is connected to the sample frequency generator and the frequency divider. 2. Digital frequency counter according to claim 1, which is distinguished by the fact that two dividers by 10 are additionally introduced in series and a multiplexer, which is made with the ability to receive a sequence of pulses from the output of the input shaper, which are fed to the input "0" of the multiplexer and the input of the first divider , and the sequence of pulses from the output of the first divider, which are fed to the input "1" of the multiplexer and the input of the second divider, and the sequence of pulses from the output of the second divider, which are fed to the input "2" of the multiplexer, which is made with the ability to provide a selection signal to the address inputs of the multiplexer of the division coefficient of the input sequence of pulses from the calculation and control unit, and the output of the multiplexer is connected to the C-input of the JO-trigger and the input of the first logic element I. and | and with se J fev t i and Ku u KK KK KK KK KATYU KK KK KKU KTK KK KTK KK HERE KK Kt Fig. 1