UA123047U - PERIODIC SEQUENCE FORMER WITH ADJUSTED PULSE DURATION, PAUSES AND DELAYS OF STARTING FORWARD TO STARTING PULSE - Google Patents

Abstract

The batch sequencer with a reconfigurable pulse duration, pause and delay start of the start relative to the start pulse contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has a pulse input input, synchronous load input and digital mode resolution input, asynchronous zero input, overflow output; a circuit consisting of a series-connected resistor and a capacitor connected to a power source; a starter device comprising a synchronous D-flip-flop with the input of the asynchronous zero setting, the first and second two-input elements And; the first, second and third elements OR. A synchronous DL-flip-flop was introduced with the input of the transition resolution - L and the input of the asynchronous installation to the zero state, included according to the scheme of a single-digit counter (the inverse output of the flip-flop is connected to its input D).

Description

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The useful model belongs to the pulse, computing and measuring equipment, designed for the formation of a periodic sequence with adjustable duration of pulses, pause and delay of the start of formation relative to the starting pulse.

There are well-known shapers that contain a quartz reference generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Fundamentals of digital technology. - M.: "MIR", 2001. - Fig. 5.13-5.18).

The disadvantage of known devices is the complexity of the internal structure.

Well-known pulse shapers with adjustable duration (Ukrainian patents for utility model MoMo 56879, 57976, 58272, 59473, 59474, 59481, 61842, 61845, 62967, 63177).

The disadvantage of the devices is the complexity of the structure, due to the need to use two multi-bit binary counters.

The closest in terms of technical essence and the result achieved is a generator of a periodic sequence with adjustable pulse duration, pause and delay of the start of formation relative to the starting pulse (Ukraine patent for a utility model Mo 61853, which contains two binary counters, the first of which is reversible, configured on a subtraction mode having a sync pulse input, a synchronous parallel load enable input and a load data input, a count mode enable input, an asynchronous set to zero input, an overflow output; a circuit consisting of a resistor and a capacitor connected in series, connected to a power source; a start-stop device that includes a synchronous O-flip-flop with an input of the asynchronous unit in the zero state, first and second two-input elements AND!; first, second and third OR elements, while the first input of the first OR element is connected to the output SW flip-flop, the output of the first OR element is connected to the first input of the second element I; the common point of the series-connected resistor and capacitor is connected to the information input of the JO-trigger, with one input of the first and the second input of the second element I; the output of the first element I is connected to the input of the asynchronous installation of the SW-trigger in the zero state; the output of the second element AND is connected to the inputs of the asynchronous installation of counters in the zero state; clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output

From an external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of the known device is the complexity of the scheme of reconfiguring the generator for a given duration of pulses, which is due to the need to use a second counter that determines the given duration and, as a result, high power consumption and high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that the generator of a periodic sequence with adjustable duration of pulses, pauses and delays of the start of formation relative to the starting pulse contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for allowing synchronous parallel loading and inputs of data supply during loading, the input of the permission of the counting mode, the input of the asynchronous installation in the zero state, the output of the overflow; a circuit consisting of a series-connected resistor and capacitor connected to a power source; start-stop device, which contains a synchronous SW-trigger with an input of an asynchronous installation in the zero state, the first and second two-input elements I; the first, second and third elements OR; at the same time, the first input of the first OR element is connected to the output of the SW flip-flop; the output of the first element OR is connected to the first input of the second element AND!; the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with one input of the first and the second input of the second element I; the output of the first element is connected to the input of the asynchronous installation of the SW-trigger in the zero state; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses, according to the useful model, a synchronous SW flip-flop is introduced with the transition enable input - I and the 60th input of the asynchronous installation in the zero state, included according to the one-bit counter scheme (inverse trigger output connected to its input 0), the direct output of the Y-trigger, which forms the output of the shaper, is connected to the second input of the first OR element, the clock input of the O-trigger is connected to the input of the shaper, and the input of the asynchronous unit to the zero state with connected to the output of the second element I; the OI-trigger transition enable input is connected to the output of the second OR element, the first input of which is connected to the overflow output of the first counter, and the second - to the output of the third OR element and the enable input of synchronous parallel loading of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element; the values of the signals at the inputs of the parallel loading of the first counter, which ensure the adjustment of the shaper to the given time parameters of the output sequence of pulses (the duration of the delay, the duration of the pulses, the duration of the pause, are formed by the values of the signals from the overflow output of the first counter and the outputs of the SW-trigger, so when setting the shaper to the formation sequence of pulses, the duration of which is equal to ten periods of clock pulses (supplied to the input of the shaper from the output of the external quartz generator), and the duration of the pause is equal to twelve periods with a delay of the start of formation relative to the start pulse, the duration of which is equal to three periods, the first input of parallel loading of the counter with connected to the overflow output, the second input of the parallel loading counter is connected to the inverse output of the bi-flip-flop, the third input of the parallel loading counter is connected to the direct output of the bi-flip-flop, the fourth input of the parallel loading of the connector is connected to its first output.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for configuring the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and inputs for supplying loaded data Оо-Оз, an input for enabling the counting mode Ро , the input of the asynchronous installation into the zero state H, the overflow output Pa; synchronous SW flip-flop 2 with transition enable input

It is the input of the asynchronous installation in the zero state of MV; synchronous SO-trigger Z with the input of the asynchronous unit in the zero state B; the first (4) and second (5) elements of I!; first (6), second (7), third (8) elements OR; resistor (9) and capacitor 10 are connected in series, connected to the same power source.

The common point of the series-connected resistor 10 and capacitor 11 is connected to the information input of the trigger 3, with the first inputs of the elements 4, 5. The second input of the element 4 forms the input of the supply of stop pulses (bor) of the formation of output pulses. The output of element 4 is connected to the input of the asynchronous installation of the trigger Z in the zero state. The second input of element 5 is connected to the output of element 6. The output of element 5 is connected to the inputs of the asynchronous installation in the zero state of the counter 1 and I-trigger 2. The first input of element 6 is connected to the output of trigger 3. The second input of element 6 with is connected to the direct output (O:) and -trigger 2, which forms the output (GE) of the shaper. The overflow output (Ra) of counter 1 is connected to the first input of element 7.

The second input of element 7 is connected to the output (I) of element 8 and the enable input of synchronous parallel loading of counter 1. The output (I) of element 7 is connected to the input (I) of enable transition of PI-trigger 2.

The outputs of the second (01), third (02) and fourth (Oz) digits of counter 1 are connected to the inputs of element 8.

When setting the shaper to form a sequence of pulses, the duration of which is equal to ten periods (10T) of clock pulses (supplied to the shaper input from the output of the external quartz generator), and the duration of the pause is equal to twelve periods (127) with a delay of the start of the formation relative to the start pulse, the duration of which is equal to three periods (ZT), the first input (Оо0) of parallel loading of the counter is connected to the overflow output, the second input (01) of parallel loading of the counter is connected to the inverse output of the I flip-flop, the third input (O2) of parallel loading of the counter with connected to the direct output of the Obi flip-flop, the fourth input (Oz) of the parallel load counter is connected to its first output (Oo).

The clock inputs of the counter 1 and trigger 2 form the input (C) of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external quartz generator. The clock input of the flip-flop Z forms the start pulse supply input.

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 10 and a capacitor 11 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs , i.e. on inputs A of the asynchronous installation in the zero state of trigger 3, trigger 2 and counter 1.

After the transient process associated with turning on the power supply, counter 1 and flip-flops go to the zero state, forming a logical zero level at the direct outputs of flip-flops 2, C and at the output of element 6, which is connected to the input of element 5, which provides the logic zero level at the inputs B of the asynchronous reset of counter 1 and trigger 2 and after the end of the transition process associated with the charge of capacitor 11. Since the mode of asynchronous reset of the counter and trigger has priority over all the latter modes, then as long as the logic zero level remains at the input of element b (and therefore at its output), when clock pulses arrive, the zero state of counter 1 and flip-flop 2 will remain unchanged, that is, the zero value at the output of the shaper will remain unchanged, the single value at its overflow output will remain unchanged and at the input of the permission to load the counter 1, a single value at the input and output of element 7, i.e. at input I. trigger 2.

During the arrival of the start pulse (5iap) to the clock input C of the flip-flop Z on its edge, the flip-flop goes into a single state), forming the level of a logical unit at its output (0-1), at the output of element 6, and therefore at the input and output of element 5 , which provides the level of a logical unit at the inputs B of counter 1 and flip-flop 2, removing the blocking. Since there is a logical zero level at the input Y of counter 1, and a level of logical one at the input Y of trigger 2, then by the time of the arrival of the next clock pulse, counter 1 is in the loading readiness mode, and trigger 2 is in the transition prohibition mode.

And then during the introduction of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals that are generated at the corresponding inputs 0o-Yuz (О3020100-0011-3). The counter goes to state 0011-3, which leads to the formation of a zero value at the overflow output of counter 1, a single value at the output of element 8 and input |! of the counter, which leads to the prohibition of loading the counter and the permission of the counting (subtraction) mode. The zero state of trigger 2 (the zero value of the signal at the output of the shaper) remains unchanged.

During the entry of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of trigger 2 remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 8, 7. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode. | then during the arrival of the next clock pulse along its edge, counter 1 is again loaded in parallel with the values of the signals generated at the inputs 0o-Oz (О3020100-1010-10). The counter goes to the state Oz0200100-1010-10. Flip-flop 2 will go to the single state, forming a single value at the output of the shaper.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the unit state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 7, 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode. And then, during the arrival of the next clock pulse along its edge, the counter 1 is loaded in parallel with the values of the signals that are formed on the moves 0o-ЯОз (О3020100-1100-12). During the introduction of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 8,7. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode.

In the future, the processes are repeated. Thus, after the end of the transient process associated with the removal of the blocking, during input C of the generator of a periodic sequence of pulses with a period T, a periodic sequence of pulses is generated at the direct output of trigger 2, the duration of which is equal to 10T, and the duration of the pause is equal to 12T, with delay relative to the starting pulse, which is equal to ЗТ.

The process of forming the output sequence of pulses is stopped by applying a pulse corresponding to the logic zero level to the stop input (Stor), which forms an active signal level at the input A of the asynchronous unit of the Y-trigger Z, which leads to its transition to the zero state (0-0) . The OR pulse is, as a rule, asynchronous with respect to the pulses of the external generator and to the state of trigger 2.

If, at the time of pulse 5ior, flip-flop 2 is in the zero state, then when the U-trigger З goes to the zero state, a logical 0 level will be formed at the inputs of element 6 and its output, causing a logical zero level at the input and output of element 5, which will lead to transition of counter 1 to the zero state, and therefore to the termination of the generation process.

If at the moment of pulse 5ior trigger 2 will be in a state other than zero, then the output of the shaper connected to the input of element b will have a level of logical unity, determining the level of logical unity at its output and the input of element 5. Since the second input of element 5 also has a level of a logical unit, determined by the voltage on capacitor 11, which was charged when the power source was turned on, then there will be a level of a logical unit at the EB inputs of the counter and trigger 2. It follows from this that at the moment of the introduction of the pulse 5ior, the termination of the generation will not happen, thereby determining the prevention of distortion of the last pulse in the output sequence. And only with the introduction of further clock pulses, when the transition of trigger 2 to the zero state will occur at the inputs of element b and its output, a level of logical 0 will be formed, causing a level of logical zero at the input and output of element 5, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the generation process. With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the transition graph of the shaper consisting of two rings (the upper ring is the transition graph of counter 1, the lower ring is the transition graph of trigger 2) with a common vertex corresponding to the zero state of the counter and trigger 2, and in Fig. From are graphs illustrating the operation for the option of setting the shaper to a duration of pulses equal to 10T, a pause between them equal to 12T, and a delay (from) the beginning of the formation of pulses at the output relative to the start pulse, which is determined by the value (О3020100-0011-3 .

Since the start pulses are asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range:

ZT "Iz" 4.

Unlike the known device, the simplification of the structure of the second counter made it possible to simplify the technology of its manufacture, reduce the power consumption and cost.

Claims (1)

USEFUL MODEL FORMULA Periodic sequence generator with adjustable pulse duration, pause and From the delay of the start of formation relative to the start pulse, containing two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for enabling synchronous parallel loading and inputs for supplying data during loading, an input for enabling the counting mode, an input for asynchronous settings in the zero state, overflow output; a circuit consisting of a series-connected resistor and capacitor connected to a power source; a start-stop device, which contains a synchronous SW-trigger with an input of an asynchronous installation in the zero state, the first and second two-input elements I; the first, second and third elements OR; at the same time, the first input of the first OR element is connected to the output of the SW flip-flop; the output of the first OR element is connected to the first input of the second AND element; the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with one input of the first and the second input of the second element I; the output of the first element I is connected to the input of the asynchronous installation of the Y-trigger in the zero state; the output of the second element AND is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; clock input The O-trigger forms the input of the supply of start pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses, which is distinguished by the fact that a synchronous Oi-trigger is introduced with the input of the transition permission I! and the input of the asynchronous installation in the zero state, turned on according to the scheme of a one-bit counter (the inverse output of the flip-flop is connected to its input 0), the direct output of the OI flip-flop, which forms the output of the shaper, is connected to the second input of the first OR element, the clock input of the OI - the trigger is connected to the input of the shaper, and the input of the asynchronous unit in the zero state is connected to the output of the second element I; the transition enable input of the Pi flip-flop is connected to the output of the second OR element, the first input of which is connected to the overflow output of the first counter, and the second - to the output of the third OR element and the enable input of synchronous parallel loading of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element; the values of the signals at the inputs of the parallel loading of the first counter, which provide tuning of the shaper to the given time parameters of the output sequence of pulses (delay duration, because the duration of the pulses, the duration of the pause, are formed by the values of the signals from the overflow output of the first counter and the outputs of the 0-trigger, so when setting the shaper to form a sequence of pulses, the duration of which is equal to ten periods of clock pulses (which are fed to the shaper input from the output of an external quartz generator), and the duration of the pause is equal to twelve periods with a delay of the start of formation relative to the start pulse, the duration of which is equal to three periods, the first input of the parallel load of the counter is connected to the overflow output, the second input of the parallel load of the counter is connected to the inverse output of the Obi flip-flop output, the third input parallel loading of the counter is connected to the direct output of the 0 flip-flop, the fourth input of the parallel loading of the counter is connected to its first output. ee Tk V with :Y ; 41 C SVI Ko Y tu E: Noechi I -- 5 | i and i i KU Z Z I! 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