UA127021U - FORMER OF THE PERIODIC SEQUENCE OF IMPULSE PULSES WITH ADJUSTABLE PERIOD OF DURATION AND DELAY OF STARTING FORMATION AFTER STARTING - Google Patents

Abstract

A waveform pulse type waveform tuner with a configurable period duration and a delay of the start of the formation relative to the starting pulse contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has the input of the synchronous parallel loading mode and the inputs of which determine the input signals. output pulse sequence parameters; a second one-digit counter made on a synchronous DL-flip-flop with the input of the asynchronous setting to the zero state, which provides the generation of pulses at the output; a starter device comprising a synchronous D-flip-flop with an asynchronous zero input that enables the pulse output to be started and stopped.

Description

The useful model belongs to pulse, computing and measuring technology, designed for the formation of a periodic sequence of pulses of the meander type with adjustable period duration and delay of the start of formation relative to the starting pulse.

There are well-known generators that contain a quartz setting generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Basic digital technology. - M. "MIR". - 2001. - Fig. 5.13 5.18).

The disadvantage of known devices is the complexity of the internal structure.

Well-known pulse generators with adjustable duration (Ukrainian patents for useful model MoMo 575947, 71808, 59473, 7885).

The disadvantage of the devices is the complexity of the structure.

The closest in terms of technical essence and the result achieved is the generator of a periodic sequence of pulses of the meander type with adjustable period duration and delay of the start of formation relative to the starting pulse (patent of Ukraine for utility model Mo 59481), which contains two binary counters, one of which is reversible, configured for subtraction mode, which has a synchronization pulse supply input, a synchronous parallel download enable input and data feed inputs during download, a count mode enable input, an asynchronous reset input in the zero state, an overflow output; the first, second and third elements OR; a start-stop device, which contains a chain consisting of a series-connected resistor and a capacitor, a synchronous SW flip-flop with an input of an asynchronous installation in the zero state, the first and second elements AND, while the common point of the series-connected resistor and capacitor is connected to the information the input of the SW-trigger, with the first inputs of elements I; output of the first element I! connected to the input of the asynchronous unit of the U-trigger in the zero state; the output of the second element I is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the second input of the second element AND is connected to the output of the first OR element, the first input of which is connected to the output of the ОХО-trigger; the output of the first OR element is connected to the first input of the second AND element.

The disadvantage of the known device is the complexity of the circuit for adjusting the shaper to the given duration of the time parameters of the output pulses, which is due to the need to use two reversing counters that determine the given parameters and, as a result, high power consumption and high cost.

The useful model is based on the task of simplifying the tuning of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that in the generator of a periodic sequence of pulses of the meander type with adjustable period duration and delay of the start of formation relative to the starting pulse, which contains two binary counters, one of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for permission synchronous parallel download and data feed inputs during download, input of the digit mode permission, input of the asynchronous installation in the zero state, overflow output; the first, second and third elements OR; a start-stop device, which contains a chain consisting of a series-connected resistor and a capacitor, a synchronous SW flip-flop with an input of an asynchronous installation in the zero state, the first and second elements AND, while the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with the first inputs of elements I; output of the first element I! connected to the input of the O-trigger asynchronous installation in the zero state; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper, the input of the supply of a periodic sequence of pulses from the output of the external quartz generator; clock input

The O-trigger forms the input of the supply of start pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the second input of the second element is connected to the output of the first OR element, the first input of which is connected to the output of the SW flip-flop; the output of the first OR element is connected to the first input of the second element AND, according to the useful model, a synchronous OI flip-flop is introduced with the transition enable input - Y and the input of the asynchronous installation in the zero state, included according to the scheme of a one-bit counter (the inverse output of the AND flip-flop with is connected to its input 0), the direct output of the 0-trigger, which forms the output of the shaper, is connected to the second input of the first OR element, the clock input of the OII-trigger is connected to the input of the shaper, and the input of the asynchronous unit to the zero state with 'connected to the output of the second element /!; the transition enable input of the AND flip-flop is connected to the output of the second element

OR, the first input of which is connected to the overflow output of the first counter, and the second to the output of the third OR element and the input of allowing synchronous parallel loading of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element; the values of the signals at the inputs of the parallel loading of the first counter, which ensure the setting of the shaper to the given time parameters of the output sequence of pulses, the value of the delay duration is formed by the value of the signal from the overflow output of the counter, the values of the duration of pulses and pauses are formed by the value of the signal from the output of the first bit of the counter, so when setting the shaper for the formation of a meander-type sequence, the duration of pulses and pauses of which is equal to seven periods of clock pulses (supplied to the input of the shaper from the output of an external quartz generator), and the duration of the delay of the start of formation relative to the start pulse is equal to ten periods, the first and third inputs of parallel loading are connected the output of the first digit of the counter, the second input of the parallel load is connected to the level of a logical unit, the fourth input of the parallel load is connected to the overflow output of the counter.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for configuring the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and inputs for supplying loaded data Оо-Оз, an input for enabling the counting mode Ро , the input of the asynchronous installation into the zero state H, the overflow output Pa; synchronous O! flip-flop 2 with transition enable input

It is the entry of the asynchronous installation into the zero state of the CA; synchronous SO-trigger Z with the input of the asynchronous installation in the zero state B; the first (4) and second (5) elements of I!; the first (6), second (7) and third (8) elements OR; resistor 9 and capacitor 10 are connected in series, connected to the JHE power source.

The common point of the series-connected resistor 9 and capacitor 10 is connected to the information input of the trigger 3, with the first inputs of the elements 4, 5. The second input of the element 4 forms the input of the supply of stop pulses (bor) of the formation of output pulses. Output of element 4

Zo is connected to the input of the asynchronous installation of the trigger Z in the zero state. The second input of element 5 is connected to the output of element 6. The output of element 5 is connected to the inputs of the asynchronous installation in the zero state of counter 1 and 0 of trigger 2. The first input of element 6 is connected to the output of trigger 3. The second input of element 6 is connected to the direct output (C) 0 - trigger 2, which forms the output (GE) of the shaper. The overflow output (Ra) of counter 1 is connected to the first input of element 7.

When setting the generator to form a meander-type sequence, the duration of pulses and pauses of which is equal to seven periods of clock pulses, the first (Осо) and third (О2) inputs of the parallel load are connected to the output of the first digit (Оо) of the counter, the second (Ри) input of the parallel the load is connected to the logic unit level, the fourth (Oz) input of the parallel load is connected to the overflow output of the counter and the element 7 input.

The output of element 7 is connected to the input (I) of enabling the 0-trigger 2 transition. The outputs of the second (0), third (Og2) and fourth (Oz) digits of counter 1 are connected to the inputs of element 8. The clock inputs of counter 1 and the trigger 2 form the input (C) of the shaper - the input for supplying a periodic sequence of pulses from the output of the external quartz generator. The clock input of the flip-flop Z forms the start pulse supply input (stage).

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 9 and a capacitor 10 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs , i.e. on inputs A of the asynchronous installation in the zero state of triggers 2, З and counter 1.

After the end of the transient process associated with turning on the power source, the counter 1 and the flip-flops go to the zero state, forming: a logical zero level at the outputs 01-Oz, at the output of element 8, at the first input of element 7, at the input of enabling synchronous loading, the level of logic one at the overflow output of counter 1, at the second input of element 7, the level of logic zero at the direct outputs of triggers 2, C and at the output of element 6, which is connected to the input of element 5, which provides a level of logic zero at the inputs B of the asynchronous installation to the zero state of counter 1 and trigger 2 and after the end of the transition process associated with the charge of capacitor 11. Since the mode of asynchronous setting of the counter and trigger to the zero state has priority over all the last modes, then as long as at the input of element 6 (and, therefore, at its output) the level of logical zero will be preserved, when clock pulses arrive, the zero state of counter 1 and trigger 2 will remain unchanged im, i.e. the zero value at the output of the shaper, the unit value at its overflow output and at the input of the counter loading permit 1 will remain unchanged, the unit value at the input and output of element 7, i.e. at the input of I. trigger 2.

During the arrival of the start pulse (5iap) to the clock input C of the flip-flop Z on its edge, the flip-flop goes into a single state, forming the level of a logical unit at its output (0-1), the output of element 6, and therefore at the input and output of element 5, which provides the level of a logical unit at the inputs B of counter 1 and flip-flop 2, removing the blocking. Since the input I of counter 1 has a level of logical zero, and the input I of trigger 2 has a level of logical one, then at the time of the arrival of the next clock pulse, counter 1 is in the loading readiness mode, and trigger 2 is in the transition prohibition mode. And then, during the entry of the first (after the end of the transition process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at the Oo-Yuz inputs (O3020100-1010-10). The counter goes to state 1010, which leads to the formation of a zero value at the overflow output of counter 1, a single value at the output of element 8 and input I. of the counter, to prohibit loading of counter I and enable the counting (subtraction) mode.

The zero state of trigger 2 (the zero value of the signal at the output of the shaper) remains unchanged.

During the introduction of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 8, 7. As a result, counter 1 will go into loading mode, and trigger 2 into transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals at the inputs О0о-ХОз (О3020100-0111-7).

The counter goes to the state 0111. Flip-flop 2 will go to the single state, forming a single value at the output of the shaper.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the unit state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 8, 7. As a result, the counter is 1

Zo will go into download mode, and trigger 2 will go into transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals generated at the Oo-Oz inputs (О30201О00-0111-7). During the introduction of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of flip-flop 2 will remain unchanged. As soon as the content of counter I becomes equal to 0001, a zero value is formed at the outputs of elements 7, 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode.

In the future, the processes are repeated. Thus, after the end of the transition process associated with the removal of blocking, during input C of the generator of a periodic sequence of pulses with a period of T, a periodic sequence of pulses is generated at the direct output of trigger 2, the duration of which pulses and pauses is equal to 7T, with a delay relative to the starting momentum, which is equal to 10T.

The process of forming the output sequence of pulses is stopped by applying a pulse corresponding to the logic zero level to the stop input (Stor), which forms an active signal level at input A of the asynchronous unit U-trigger 3, which leads to its transition to the zero state (0-0) . The OR pulse is, as a rule, asynchronous with respect to the pulses of the external generator and to the state of trigger 2.

If, at the time of pulse 5ior, flip-flop 2 is in the zero state, then when the U-trigger З goes to the zero state, a logical 0 level will be formed at the inputs of element 6 and its output, causing a logical zero level at the input and output of element 5, which will lead to transition of counter 1 to the zero state, and therefore to the termination of the generation process.

If, at the time of pulse 2ior, trigger 2 is in a state other than zero, then at the output of the shaper connected to the input of element 6, there will be a level of logic unit, determining the level of logic unit at its output and input of element 5. Since at the second input of the element 5 also the level of a logical unit, determined by the voltage on the capacitor 10, which was charged when the power source was turned on, then there will be a level of a logical unit at the inputs K of the counter and trigger 2. It follows from this that at the moment of introduction of the Bier pulse, the termination of the generation will not occur, thereby preventing the distortion of the last pulse in the output sequence. And only with the introduction of further clock pulses, when the transition of trigger 2 to the zero state will occur at the inputs of element 6 and its output, because the level of logic 0 will be formed, causing the level of logical zero at the input and output of element 5, which will lead to the transition of counter 1 to the zero state , and therefore to the termination of the generation process. With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the transition graph of the shaper consisting of two rings (the upper ring is the transition graph of counter 1, the lower ring is the transition graph of trigger 2) with a common vertex corresponding to the zero state of the counter and trigger 2, and in Fig. C shows graphs illustrating the operation for the option of setting the shaper to the duration of pulses and a pause, which is equal to 7T, with a delay (IZ) of the beginning of the formation of pulses at the output relative to the start pulse, which is determined by the value (О3020100-1010-10). Since the start pulses are asynchronous in relation to the clock pulses, the duration of the delay of the start of formation is in the range: 101 "Iz"11T.

Unlike the known device, the simplification of the structure of the second counter made it possible to simplify the technology of its manufacture, reduce the power consumption and cost.

Claims (1)

USEFUL MODEL FORMULA The generator of a periodic sequence of pulses of the meander type with an adjustable duration of the period and the delay of the start of the formation relative to the start pulse, which contains two binary counters, one of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for enabling synchronous parallel loading and inputs for data supply during loading, the input of the permission of the counting mode, the input of the asynchronous installation in the zero state, the overflow output; the first, second and third elements OR; a start-stop device, which contains a chain consisting of a series-connected resistor and a capacitor, a synchronous SW flip-flop with an input of an asynchronous installation in the zero state, the first and second elements AND, while the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with the first inputs of elements I; the output of the first element is connected to the input of the asynchronous installation of the O-trigger in the zero state; the output of the second element I is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the U-trigger forms the input of the supply of start-up pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the second input of the second AND element is connected to the output of the first OR element, the first input of which is connected to the output of the SW flip-flop; the output of the first OR element is connected to the first input of the second element AND, which differs in that a synchronous OI flip-flop is introduced with the transition enable input Y and the input of the asynchronous setup in the zero state, included according to the scheme of a one-bit counter (the inverse output of the 0 flip-flop with connected to its input 0), the direct output of the 0 flip-flop, which forms the output of the shaper, is connected to the second input of the first OR element, the clock input of the OI flip-flop is connected to the input of the shaper, and the input of the asynchronous unit to the zero state is connected with the output of the second element I; the PI flip-flop transition enable input is connected to the output of the second OR element, the first input of which is connected to the overflow output of the first counter, and the second - to the output of the third OR element and the enable input of synchronous parallel loading of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element; the values of the signals at the inputs of the parallel loading of the first counter, which ensure the setting of the shaper to the given time parameters of the output sequence of pulses, the value of the delay duration is formed by the value of the signal from the overflow output of the counter, the values of the duration of pulses and pauses are formed by the value of the signal from the output of the first bit of the counter, so when setting the shaper for the formation of a meander-type sequence, the duration of pulses and pauses of which is equal to seven periods of clock pulses (supplied to the input of the shaper from the output of an external quartz generator), and the duration of the delay of the start of formation relative to the start pulse is equal to ten periods, the first and third inputs of parallel loading are connected the output of the first digit of the counter, the second input of the parallel load is connected to the level of a logical unit, the fourth input of the parallel load is connected to the overflow output of the counter. with | r Not And with (oh! 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