UA113634U - SINGLE BATCH OF THE PATCHES OF PROGRAMMED QUANTITY AND DELAY OF BEGINNING OF THE PACKING OF THE PACK ABOUT THE STARTING PULSE - Google Patents

Abstract

A single pulse generator with a programmable number and delayed start of the formation of the bundle relative to the starting pulse contains a synchronous D-trigger with the input of the asynchronous zero setting, reversible binary counter, tuned to subtraction mode, inverter, first and second elements the third element And, a circuit consisting of a series-connected resistor and a capacitor. Additionally introduced: fourth element I, second inverter, element OR-NOT, first, second and third synchronous DL-triggers with zero input asynchronous installation, forming a cyclic device (second counter) with the sequence 000-001-011-111 -110-100-000.

Description

NI is connected to the inputs of both flip-flops; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element, the output of which is connected to the enable input of the synchronous parallel loading mode of the first counter and to the second input of the OR-NOT element; the clock inputs of the 0 flip-flops are connected to the input of the shaper; the inputs of the asynchronous installation in the zero state of OiI -triggers are connected to the output of the second element I.

The claimed former has a new composition of elements and a new organization of relationships between them, that is, it contains a new set of features that provide new technical properties. The technical result, as a consequence of these properties, is the simplification of the structure of the former.

In fig. 1 shows the schematic diagram of the former.

The shaper includes: a first reversible binary counter (1) configured for subtraction mode, which has a C clock input, a summation/subtraction input I, a synchronous parallel loading enable input I, and data inputs Oo-Oz, an enable input of the Po counting mode, the input of the asynchronous installation into the zero state of PH, the overflow output of Pa.; the first (2), second (3) and third (4) synchronous 0 flip-flops with the input of the asynchronous unit in the zero state, which form a cyclic device (second counter) with the sequence of transitions 000-001-011-111-110-100-000 ; synchronous O-trigger (5) with the input of the asynchronous installation in the zero state; the first (6), second (7), third (8) and fourth (9) elements of I; the first (10) and second (11) OR elements; element OR-NO (12); first (13) and second (14) inverters; a chain consisting of a resistor (15) and a capacitor (16) connected in series.

The direct output of flip-flop 2 is connected to the O input of flip-flop 3. The direct output of flip-flop C is connected to the input

O trigger 4. The direct output of trigger C is connected to the first input of element 8, the output of which is connected to the first input of element 9, to the second input of element 10 and the input of inverter 14. The output of inverter 14 is connected to the second input of element 6. The second input of the element 9, the output of which, forming the output E of the shaper, is connected to the input of the supply of clock pulses C. The second input of the element 8 is connected to the inverse output of the trigger 3. The output of the inverter 13 is connected to the first input of the element 12. The output of the element 12 connected to inputs !. triggers 2, 3, 4. The outputs of the second (0), third (02) and fourth (Oz) digits of the counter 1 are connected to the inputs of element 11, the output of which is connected to the second input of element 12 and input I! of counter 1. The clock inputs of counter 1 and triggers 2, 3, 4 are connected to the input of shaper C, the inputs of the asynchronous installation in the zero state of counter 1 and triggers 2, 3, 4 are connected to the output of element 7. The common point of the series-connected resistor 15 and capacitor 16 is connected to the input of the SW trigger 5, the input of the element 6 and the input of the element 7, the output of which is connected to the inputs of the asynchronous installation in the zero state of the first and second counters. The output of the element 6 is connected to the input of the asynchronous installation of the trigger 5 in the zero state. Inputs 03020100 of parallel loading of counter 1 form inputs of rzr2bibo programming of the shaper for a given number of pulses at the output. The clock input C of the trigger 5 forms the start input (ia) of the formation of output pulses.

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 15 and a capacitor 16 connected to the supply voltage bus и4E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 6 and 7, ensuring the formation of a logical zero level at their outputs, connected to the KE inputs of the asynchronous installation in the zero state of counter 1 and triggers 2, 3, 4, 5. After the end of the transient process associated with turning on the power source, the triggers and counter 1 go to the zero state, forming a logical zero level at the direct outputs and on the output of overflow Ra of counter 1, on the direct outputs of PO! triggers, at the outputs of elements 11,12, at the input of allowing synchronous loading of counter 1, a single value at the output of inverter 13, a zero value at the output of elements 7, 8, 9 (at the output of the shaper), which leads to the formation of a logical zero level at the output of the element 10, which is connected to the input of element 7, which ensures the confirmation of the logical zero level at its output, and after the end of the transition process associated with the charge of the capacitor 16, which ensures the logical zero level at the inputs of the MK asynchronous unit to the zero state of counter 1 and OI triggers. Since the mode of asynchronous setting to the zero state has priority in relation to all the last modes, as long as the zero level is maintained at the input of element 7 (and therefore at its output), the zero state of the counter and 0. triggers and the zero value at the output shaper will remain unchanged.

During the arrival of the trigger pulse (siap) at the input C of the flip-flop 5 on its edge, the flip-flop goes into a single state (0-1), forming a level of a logical unit at the output of element 10, and therefore at the input and output of element 7, which provides a level of a logical unit on inputs B of counter 1 and b-triggers, removing the blocking of the zero value, as a result of which counter 1 goes into the mode of readiness to receive information from inputs Yuo-Oz.

Then, during the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the Yurzbr2ribo signals, which are applied to the corresponding inputs ХОз-ХОо, which leads to the formation of a single value on counter overflow outputs 1, unit value at the element output

11, until the loading mode is disabled and the counting (subtraction) mode of counter 1 is enabled. Since the zero value at the output of element 12 remained unchanged, the zero state of the Obi flip-flops also remained unchanged. During the arrival of the next and subsequent clock pulses, the content of counter 1 will decrease, and the zero state of the Obi flip-flops will remain unchanged, that is, the zero value at the direct outputs of the PI flip-flops, at the outputs of elements 8, 9 (at the output of the shaper) will remain unchanged until until the content of counter 1 becomes equal to 0001. As a result of this transition, a logical zero level is formed at the output of element 11 and at the Y input of counter 1, and a logical one level is formed at the output of element 12, which leads to the transition of counter 1 to the download mode, and the second of the counter (01 -triggers) - in the mode of transition to the next state, and then during the arrival of the next clock pulse along its edge, counter 1 is again loaded in parallel with the values of the signals Brzir2r,ro, which are applied to the corresponding inputs YuOz-Oo, which leads to the formation of a single value at the output of element 11 (at the input Y of counter 1), which again leads to the prohibition of the loading mode, the permission of the counting (subtraction) mode counter 1, and the second counter goes to state 001. The zero value at the output of elements 8, 9 (at the output of the shaper) will remain unchanged. During the introduction of subsequent clock pulses, the processes are similar. As soon as the second counter goes to a state of 100 at the output of element 8, a logical unit level will be formed. A logical zero level is formed at the output of the inverter 13, which leads to the transition of the trigger 5 to the zero state. The formation of a logical unit at the output of element 8, connected to the input of element 9, allows the passage of clock pulses from the input of the generator to its output, until the second counter goes to the next state, as a result of which a logical zero level will be formed at the outputs of elements 8, 9 , causing the level of zero at the input of element 10 and the input and output of element 7 (at the inputs of the counter 1 and ОЙ - triggers), which will lead to the transition of the counters to the zero state, that is, the generation process will stop. With the arrival of the next start pulse, all processes are repeated.

Thus, after the end of the transition process associated with the removal of blocking, during the input C of the generator of a periodic sequence of pulses with a period T, a packet of clock pulses is generated at the output of the generator, with a programmed number M, which is determined by the value of the control word B (M- B) and the delay (iZ) of the start of formation relative to the starting pulse, the value of which also depends on the meaning of the control word B and the moment of onset of the Tay pulse (5ВТev«(5В1)Т).

In fig. 2 shows a graph of transitions of the shaper consisting of three rings (the lower ring is the transition graph of counter 1, the upper one is the transition graph of the cyclic device (the second counter), the middle ring is the value of the signal at the output of the shaper) with a common peak corresponding to the zero state of the counters, and in fig. C - time diagrams illustrating the work for the B-3 programming variant, which determines the parameters of the output sequence of pulses - the number of pulses is 3, the duration of the delay of the start of formation relative to the start pulse is within the range of more than 151 and less than 16T.

Unlike the known device, the claimed former has a new composition of elements and a new organization of relationships between them, that is, it contains a new set of features that provide new technical properties. The technical result, as a consequence of these properties, is the simplification of the structure of the former.

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