UA103635U - Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series - Google Patents

Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series

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Publication number
UA103635U
UA103635U UAU201505898U UAU201505898U UA103635U UA 103635 U UA103635 U UA 103635U UA U201505898 U UAU201505898 U UA U201505898U UA U201505898 U UAU201505898 U UA U201505898U UA 103635 U UA103635 U UA 103635U
Authority
UA
Ukraine
Prior art keywords
series
input
pulses
shaper
pause
Prior art date
Application number
UAU201505898U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Вячеслав Сергійович Харченко
Олексій Аркадійович Фурманов
Original Assignee
M E Zhukovsky Nat Aerospace University Kharkiv Aviat Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by M E Zhukovsky Nat Aerospace University Kharkiv Aviat Inst filed Critical M E Zhukovsky Nat Aerospace University Kharkiv Aviat Inst
Priority to UAU201505898U priority Critical patent/UA103635U/en
Publication of UA103635U publication Critical patent/UA103635U/en

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series include: two reversible binary counters, each of which has an input supply pulse synchronization input adjustment on mode summation / subtraction, entry permit simultaneous parallel downloads and inputs supply data input permit counting mode, asynchronous input settings in the zero state, the output overflow; the first and second elements OR; inverter; chain consisting of series connected resistor and capacitor; synchronous D-flip-flop with asynchronous input settings in the zero state, the first and second elements I. Introduced: two-charge summed up counter that has an input supply synchronization pulses, entry permit counting mode, asynchronous input settings in the zero state; the third element OR; a second inverter; NAND element.
UAU201505898U 2015-06-15 2015-06-15 Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series UA103635U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201505898U UA103635U (en) 2015-06-15 2015-06-15 Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201505898U UA103635U (en) 2015-06-15 2015-06-15 Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series

Publications (1)

Publication Number Publication Date
UA103635U true UA103635U (en) 2015-12-25

Family

ID=55172157

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201505898U UA103635U (en) 2015-06-15 2015-06-15 Shaper periodic sequence of three impulse code series of programmable duration of the pause between pulses in the series

Country Status (1)

Country Link
UA (1) UA103635U (en)

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