TWM680973U - Random access memory with two-terminal memory cells - Google Patents

Abstract

A random access memory includes: at least one memory cell array, the memory cell array includes: at least one memory cell, the memory cell has two terminals, a first terminal of the memory cell is connected to a word line, a second terminal of the memory cell is connected to a bit line, the memory cell includes: a type of diode has an anode and a cathode, the anode of the diode is connected to the word line; and a memory element has two terminals, a first terminal of the memory element is connected to the cathode of the diode, and a second terminal of the memory element is connected to the bit line, wherein, the characteristic of the diode has a forward conduction voltage, and the memory element stores data, the low resistance state of the memory element is the first state of the data, and the high resistance state of the memory element is the second state of the data.

Description

Random access memory with two-terminal memory cells

This disclosure relates to memory, and particularly to random access to memory.

Random access memory (RAM) is mainly classified into static random access memory (SRAM) and dynamic random access memory (DRAM). Static random access memory (SRAM) is mainly composed of six transistors (6T SRAM). The advantage of six transistor SRAM is that it does not require data refresh during operation, and its manufacturing process is compatible with that of general logic circuit chips. The disadvantage is that the chip area occupied by six transistor SRAM cells is larger than that of dynamic random access memory cells (1T1C DRAM) composed of one transistor and one capacitor. Dynamic random access memory (DRAM) is mainly composed of a transistor and a capacitor (1T1C DRAM). The advantage of DRAM with a transistor and a capacitor is that it occupies a smaller chip area. The disadvantage is that its manufacturing process is not compatible with the current general logic circuit chip manufacturing process, and the manufacturing process of the capacitor needs to be performed separately. Many current general logic circuit chips require random access memory (RAM) with a large number of memory cells to temporarily store large amounts of data during chip operation. The demand for high-density or high-capacity/high-speed RAM with stackable memory cells at a lower cost continues to increase. Therefore, the current demand is for RAM that can be co-fabricated with general logic circuits on a single chip at a lower cost, and that occupies a smaller chip area while maintaining high density or high capacity/high speed with stackable memory cells.

This disclosure provides different embodiments to address the aforementioned needs. One embodiment of this disclosure is a random access memory, comprising: at least one memory cell array, the memory cell array comprising: at least one memory cell having two endpoints, the first endpoint of the memory cell being connected to a word line, and the second endpoint of the memory cell being connected to a bit line, the memory cell comprising: a (Type A) A diode having an anode and a cathode, the anode of the diode being connected to the character line; and a memory element having two terminals, a first terminal of the memory element being connected to the cathode of the diode, and a second terminal of the memory element being connected to the character line, wherein the diode has a forward conduction voltage, and the memory element stores data, the low resistance state of the memory element being a first data state, and the high resistance state of the memory element being a second data state.

This disclosure provides different embodiments to address the aforementioned needs. One embodiment of this disclosure is a random access memory, comprising: at least one memory cell array, the memory cell array including: at least one memory cell having two endpoints, the first endpoint of the memory cell being connected to a word line, and the second endpoint of the memory cell being connected to a word line; the memory cell including: a memory element having two endpoints, the first endpoint of the memory element being connected to the word line; and a (Type A) A diode having an anode and a cathode, the anode of the diode being connected to a second terminal of the memory element, and the cathode of the diode being connected to a bit line. The diode has a forward conduction voltage, and the memory element stores data. The low resistance state of the memory element is the first data state, and the high resistance state of the memory element is the second data state.

According to at least one embodiment of this disclosure, the diode system is a Zener diode, which further has the characteristic of having a reverse Zener voltage.

According to at least one embodiment of this disclosure, the low-resistance state of the memory element is determined by a first voltage signal condition applied to the two terminals of the memory element, the high-resistance state of the memory element is determined by a second voltage signal condition applied to the two terminals of the memory element, and the reading of data stored in the memory element is performed by applying a third voltage signal condition to the two terminals of the memory element to detect the voltage of the memory element. The system is in a resistive state, wherein the first voltage signal condition and the second voltage signal condition have the same voltage polarity, and the absolute voltage value of the second voltage signal condition is greater than the absolute voltage value of the first voltage signal condition, while the absolute voltage value of the third voltage signal condition is less than the absolute voltage values of both the first and second voltage signal conditions; wherein the memory element is a resistive RAM (RRAM) element or a phase change memory (PCM) element.

According to at least one embodiment of this disclosure, the low-resistance state of the memory element is determined by a first voltage signal condition applied to two terminals of the memory element, the high-resistance state of the memory element is determined by a second voltage signal condition applied to two terminals of the memory element, and the reading of data stored in the memory element is performed by applying a third voltage signal condition. The two terminals of the memory element are used to detect the resistance state of the memory element, wherein the voltage polarities of the first voltage signal condition and the second voltage signal condition are opposite, and the absolute voltage value of the third voltage signal condition is less than the absolute voltage values of the first voltage signal condition and the second voltage signal condition; wherein the memory element is a resistive memory. RAM (RRAM) elements, phase change memory (PCM) elements, ferroelectric RAM (FeRAM) elements, or magnetic tunneling junction memory (MTJ) elements, wherein the magnetic tunneling junction memory element includes a fixed magnetization layer and a free magnetization layer separated by a tunneling barrier layer.

According to at least one embodiment of this disclosure, the memory cell array includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The plurality of memory cells are arranged in an array above a substrate plane in a first direction and a second direction perpendicular to the first direction, parallel to the substrate plane. The plurality of word lines are arranged along the first direction, and the plurality of bit lines are arranged along the second direction. The random access memory further includes a word... The system includes a character line decoding driver circuit, a character line sensing circuit, and a character line decoding driver circuit. The plurality of character lines are connected to the character line decoding driver circuit, and the plurality of bit lines are connected to both the character line sensing circuit and the character line decoding driver circuit. The character line decoding driver circuit includes a plurality of character line switches, each individually connected to the plurality of character lines. These character line switches are either transistor switches or transmission gate switches.

According to at least one embodiment of this disclosure, the random access memory further includes a plurality of memory cell arrays, wherein the plurality of memory cells in each memory cell array are connected to a plurality of word lines and a plurality of bit lines in a manner perpendicular to the substrate plane to form a memory cell array layer; wherein each memory cell array is located on different planar layers to form a plurality of [missing information - likely related to the substrate plane]. A plurality of memory cell array layers, wherein the plurality of word lines and the plurality of bit lines of the plurality of memory cell array layers are vertically connected downward from the edges of the plurality of memory cell array layers to the substrate plane to respectively connect to the word line decoding driver circuit, the bit line sensing circuit, and the bit line decoding driver circuit located on the substrate plane, thereby forming a three-dimensional structure comprising the plurality of memory cell array layers.

According to at least one embodiment of this disclosure, the conditions for the low-resistance state of a memory element storing one of the plurality of memory cells include: the word line decoding driver circuit applying a word line voltage to the word line of the memory cell and the bit line decoding driver circuit applying a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a first voltage signal condition, the first voltage signal condition determining... The memory element is in a low-resistance state, and the word line decoder driver keeps the other word lines floating by turning off the word line switches connected to them. The bit line decoder driver applies a voltage signal equal to the word line voltage minus the diode's forward conduction voltage to the other bit lines, or the bit line decoder driver keeps the other bit lines floating.

According to at least one embodiment of this disclosure, the conditions for the high-resistance state of the memory element storing one of the plurality of memory cells include: the word line decoding driver circuit applies a word line voltage to the word line of the memory cell, and the bit line decoding driver circuit applies a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a second voltage signal condition, the second voltage signal condition determining... The memory element is in a high-resistance state, and the word line decoder driver keeps the other word lines floating by turning off the word line switches connected to them. The bit line decoder driver applies a voltage signal equal to the word line voltage minus the diode's forward conduction voltage to the other bit lines, or the bit line decoder driver keeps the other bit lines floating.

According to at least one embodiment of this disclosure, the conditions for reading stored data from the memory element of one of the plurality of memory cells include: the word line decoding driver applies a word line voltage to the word line of the memory cell, and the bit line decoding driver applies a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a third voltage signal condition, which cannot determine the high resistance state or low resistance state of the memory element, wherein the voltage value of the first terminal of the memory element is higher than that of the second terminal of the memory element. The voltage value at the endpoint is still high, and the character line decoding driver circuit, by turning off the character line switches connected to other character lines to keep the other character lines in a floating state, then causes the character line to start sensing through the character line sensing circuit. Other character lines either start sensing through the character line sensing circuit or the character line decoding driver circuit keeps other character lines in a floating state. After a first time interval following the character line starting to sense through the character line sensing circuit, the character line decoding driver circuit transmits the sensed voltage value of the character line.

According to at least one embodiment of this disclosure, the conditions for maintaining the stored data of the memory elements in the plurality of memory cells of the memory cell array include: the word line decoding driver keeps all word lines in a floating state by turning off the word line switches connected to all word lines; the bit line decoding driver applies a predetermined bit line voltage to all bit lines; or the bit line decoding driver keeps all bit lines in a floating state.

According to at least one embodiment of this disclosure, the character line decoder driver applies a character line voltage to a character line, and maintains other character lines in a floating state by turning off character line switches connected to other character lines, and the bit line decoder driver applies the same or different bit line voltages to the plurality of bit lines, so that the plurality of memory cells connected to the character lines simultaneously perform the writing and storage of a plurality of data.

According to at least one embodiment of this disclosure, the character line decoding driver applies a character line voltage to a character line, and the character line decoding driver keeps the other character lines in a floating state by turning off character line switches connected to the other character lines, and then causes the plurality of character lines to start sensing through the character line sensing circuit; and after a first time interval following the start of sensing by the plurality of character lines, the character line decoding driver transmits the sensed voltage value of the plurality of character lines, so that the plurality of memory cells connected to the character line can simultaneously read a plurality of data.

0V: Zero volt voltage

101: Character Line Decoding Driver Circuit

102: Bit line decoder driver circuit, bit line sensing circuit

103: Timing Control Circuit

All BLs: All Bit Lines

All WLs: All character lines

All WLs Floating: All character lines are floated.

Barrier Layer: A barrier layer

BL, BL 1, BL 2, BL 3, BLs: Bitline

D: Diode

Fixed Layer: Fixed magnetization layer

Free Layer: Free magnetization layer

MC, MC 1, MC 2, MC 3, MC 4, MC 5, MC 6, MC 7, MC 8, MC 9: Memory Cells

ME: Memory element

Memory Cell Array Layer 1, Memory Cell Array Layer 2, Memory Cell Array

Layer 3: Memory cell array layer

Memory Control Circuit Layer

MSW, MSW1, MSW2, MSW3: Transistors

MTJ: Magnetic Tunneling Junction Memory Component

No Operation: No operation

Other BLs: Other bit lines

Other WLs: Other character lines

Other WLs Floating: Other character lines floating

Read: 謀取

Sensing: to sense or perceive

SL: Select Line

Substrate: substrate

T1: First Time Zone

Vap: Antiparallel magnetization voltage of MTJ (Magnetic Tunneling Junction Memory) element.

Vpp: The sum of the antiparallel magnetization voltage of the magnetic tunneling junction memory element (MTJ) and the forward conduction voltage of the Zener diode (ZD) plus the parallel magnetization voltage of the MTJ and the reverse Zener voltage of the Zener diode (ZD) (absolute value).

Vr: Read voltage of MTJ (Magnetic Tunneling Junction) memory element

Vt: Forward conduction voltage of the Zener diode (ZD)

WL, WL 1, WL 2, WL 3, WLs: Character lines

WL Control 1, WL Control 2, WL Control 3: Control Signals

Write 0: Write 0

Write 1: Write 1

ZD: Zinner Diode

A better understanding can be obtained by referring to the attached diagrams when reading the implementation methods described below; it should be noted that the dimensions of the features in the diagrams are not drawn to scale, and the positions in the diagrams are for illustrative purposes only; the dimensions may be increased or decreased, or the positions adjusted, for clarity and ease of understanding.

Figure 1 shows a prior art random access memory cell comprising one MTJ (Magnetic Tunnel Junction) memory element, one transistor, and three endpoints.

Figure 2 is an embodiment of the random access memory cell disclosed herein, comprising one memory element, one diode, and two endpoints.

Figure 3 is an embodiment of the random access memory cell disclosed herein, comprising one memory element, one diode, and two endpoints.

Figure 4 is an embodiment of the random access memory cell disclosed herein, comprising one memory element, one zircon, and two endpoints.

Figure 5 is an embodiment of the random access memory cell disclosed herein, comprising one memory element, one zircon, and two endpoints.

Figure 6 is an embodiment of the random access memory cell disclosed herein, comprising one MTJ (Magnetic Tunnel Junction) memory element, one Zener diode, and two endpoints.

Figure 7 is an embodiment of the random access memory cell disclosed herein, comprising one MTJ (Magnetic Tunnel Junction) memory element, one Zener diode, and two endpoints.

Figure 8 is an illustration of an MTJ (Magnetic Tunnel Junction) memory element.

Figure 9 is an illustration of an MTJ (Magnetic Tunnel Junction) memory element.

Figure 10 is an illustration of an MTJ (Magnetic Tunnel Junction) memory element.

Figure 11 is an embodiment of the random access memory cell array disclosed herein, comprising one MTJ (Magnetic Tunnel Junction) memory element, one Zener diode, and two endpoints.

Figure 12 is an embodiment of the random access memory cell array disclosed herein, comprising one MTJ (Magnetic Tunnel Junction) memory element, one Zener diode, and two endpoints.

Figure 13 is an embodiment of the random access memory cell array layer disclosed herein, comprising one MTJ (Magnetic Tunnel Junction) memory element, one Zener diode, and two endpoints.

Figure 14 is an embodiment of random access memory (RAM) disclosed herein, comprising a plurality of random access memory cell array layers.

Figure 15 is an example of an embodiment of the operational conditions for writing data 1 to a memory cell in the random access memory cell array disclosed herein.

Figure 16 is an example of an embodiment of the operational conditions for writing data 0 to a memory cell in a random access memory cell array disclosed herein.

Figure 17 is an example of the operational conditions for reading data from a memory cell in the random access memory cell array disclosed herein.

Figure 18 is an example of an embodiment of the operational conditions for maintaining data in memory cells within a random access memory cell array disclosed herein.

The following disclosure provides different embodiments of this disclosure to implement different features of the disclosed object, and these embodiments are by way of illustration only and not limitation.

A better understanding of the embodiments of this disclosure can be obtained by referring to the accompanying drawings; it should be noted that the dimensions of the features in the drawings are not to scale, and the positions in the drawings are for illustrative purposes only; dimensions may be increased or decreased, or positions adjusted, for clarity and ease of understanding.

Currently, various forms of random access memory (RAM) exist, such as static random access memory (6T SRAM) with six transistors and dynamic random access memory (1T1C DRAM) consisting of one transistor and one 3D capacitor. However, both 6T SRAM and 1T1C DRAM have the disadvantages mentioned above in the prior art. Many current general logic circuit chips require random access memory with a large number of memory cells to temporarily store large amounts of data during chip operation; and the demand for lower-cost, high-density, or high-capacity or high-speed random access memory with stackable memory cells continues to increase. Therefore, there is a current demand for random access memory (RAM) that can be co-fabricated with general logic circuits on a single chip at a lower cost, and for high-density, high-capacity, or high-speed RAM that occupies a small chip area and can three-dimensionally stack memory cells.

Referring to Figure 1, a prior art is a memory cell MC for random access memory as shown in Figure 1, which includes one MTJ (Magnetic Tunnel). A random access memory cell consisting of a magnetic tunneling junction memory element (MTJ), a transistor MSW, and three endpoint wires: a word line (WL), a bit line (BL), and a select line (SL). The MTJ is used to store data. The WL and BL lines are used to select the MTJ. The MSW is used as a control switch for selecting the MTJ. The SL line, in conjunction with the BL line, controls the read/write voltage signals for the MTJ's stored data. However, the prior art's transistor MSW and three terminal wires cause the memory cell to occupy a fixed area of the chip substrate, making it difficult to achieve high density of randomly accessed memory or to stack memory cells in three dimensions.

To address the aforementioned needs and overcome the shortcomings of prior art where random access memory (RAM) cells occupy a large area of a fixed chip substrate, making it difficult to achieve high density or three-dimensional stacking of RAM cells, this disclosure proposes a RAM cell and RAM cell array comprising only one memory element, one diode, and two terminal connections. Furthermore, the RAM cell array proposed in this disclosure is unaffected by data stored in other memory cells besides the currently operating memory cell during operation, and does not affect the data stored in other memory cells besides the currently operating memory cell. The random access memory (RAM) cell disclosed herein, comprising only one memory element, one diode, and two terminal connections, occupies a smaller chip substrate area than the prior art RAM cell comprising one memory element, one transistor, and three terminal connections. Therefore, with the same chip substrate area, the RAM density can be increased, costs can be saved, and it is easier to stack memory cells in three dimensions.

Referring to Figure 2, this disclosure proposes different embodiments to address the aforementioned requirements. One embodiment proposed in this disclosure is a random access memory as shown in Figure 2, comprising: at least one memory cell array, the memory cell array including: at least one memory cell MC, the memory cell MC having two endpoints, the first endpoint of the memory cell being connected to a word line WL, and the second endpoint of the memory cell MC being connected to a bit line BL, the memory cell MC including: a (Type A) A diode D has an anode and a cathode, the anode of which is connected to the character line WL; and a memory element ME has two terminals, the first terminal of which is connected to the cathode of the diode D, and the second terminal of which is connected to the character line BL. The diode D has a forward conduction voltage (Vt), and the memory element ME stores data. The low resistance state of the memory element ME is the first data state, and the high resistance state of the memory element is the second data state.

The memory element ME in Figure 2 has the same data storage function as the magnetic tunneling junction memory element MTJ in the prior art Figure 1. The memory element ME can be a resistive RAM (RRAM) element or a phase change memory (PCM) element. The transistor MSW in the prior art Figure 1, used as the magnetic tunneling junction memory element MTJ, avoids mutual interference between different memory cells MC during read and write operations. However, the prior art Figure 1 occupies a larger chip substrate area and makes it difficult to three-dimensionally stack memory cells MC. Figure 2 of this disclosure utilizes character lines (WL) to select memory elements (ME) and employs the unipolar current characteristic of diodes (D) to avoid mutual interference between different memory cells (MC) during read and write operations. This improves the density of random access memory, saves costs, and facilitates the three-dimensional stacking of memory cells (MC).

Referring to Figure 3, this disclosure proposes different embodiments to address the aforementioned requirements. One embodiment proposed in this disclosure is a random access memory as shown in Figure 3, comprising: at least one memory cell array, the memory cell array including: at least one memory cell MC, the memory cell MC having two endpoints, the first endpoint of the memory cell MC being connected to a word line WL, and the second endpoint of the memory cell MC being connected to a bit line BL, the memory cell MC including: a memory element ME, the memory element ME having two endpoints, the first endpoint of the memory element ME being connected to the word line WL; and a (Type A) A diode D has an anode and a cathode. The anode of the diode D is connected to a second terminal of the memory element ME, and the cathode of the diode D is connected to the bit line BL. The diode D has a forward conduction voltage (Vt), and the memory element ME stores data. The low resistance state of the memory element ME is the first data state, and the high resistance state of the memory element ME is the second data state.

The memory element ME in Figure 3 has the same data storage function as the magnetic tunneling junction memory element MTJ in the prior art Figure 1. The memory element ME can be a resistive RAM (RRAM) element or a phase change memory (PCM) element. The transistor MSW in the prior art Figure 1 is used as the magnetic tunneling junction memory element MTJ to avoid mutual interference between different memory cells MC during reading and writing. However, the prior art Figure 1 occupies a larger chip substrate area and is not easy to stack memory cells MC in three dimensions. Figure 3 of this disclosure utilizes character lines (WL) to select memory elements (ME) and employs the unipolar current characteristic of diodes (D) to avoid mutual interference between different memory cells (MC) during read and write operations, thereby increasing the density of random access memory, saving costs, and facilitating the three-dimensional stacking of memory cells (MC).

The memory element ME can store binary data of logic 1 or logic 0, which is determined by the low resistance state (first data state) or high resistance state (second data state) of the memory element ME; the low resistance state (first data state) can be logic 1 or logic 0, and the high resistance state (second data state) can be logic 0 or logic 1.

Referring to Figure 4, this disclosure proposes different embodiments to address the aforementioned requirements. One embodiment is a memory cell MC in a random access memory array, as shown in Figure 4. The Zener diode ZD in the memory cell MC is an embodiment of a diode D shown in Figure 2. The Zener diode ZD in Figure 4 further features a reverse Zener voltage (Vz).

The memory element ME in Figure 4 has the same data storage function as the magnetic tunneling junction memory element MTJ in the prior art Figure 1. The memory element ME can be a resistive RAM (RRAM) element, a phase change memory (PCM) element, a ferroelectric RAM (FeRAM) element, or a magnetic tunneling junction memory (MTJ) element. The transistor MSW in the prior art Figure 1 is used as the magnetic tunneling junction memory element MTJ to avoid mutual interference between different memory cells MC during reading and writing. However, the prior art Figure 1 occupies a larger chip substrate area and is not easy to stack memory cells MC in three dimensions. Figure 4 of this disclosure utilizes the character line WL to select memory elements ME and employs the unipolar current characteristic of a ZD at lower bias voltage to avoid mutual interference between different memory cells MC during read and write operations. It also utilizes the bipolar current characteristic of the ZD at higher reverse bias voltage to perform write operations on memory elements ME that require bipolar data writing. This increases the density of random access memory, saves costs, and facilitates the three-dimensional stacking of memory cells MC.

Referring to Figure 5, this disclosure proposes different embodiments to address the aforementioned requirements. One embodiment is a memory cell MC in a random access memory array, as shown in Figure 5. The Zener diode ZD in the memory cell MC is an embodiment of a diode D shown in Figure 3. The Zener diode ZD in Figure 5 further features a reverse Zener voltage (Vz).

The memory element ME in Figure 5 has the same data storage function as the magnetic tunneling junction memory element MTJ in the prior art Figure 1. The memory element ME can be a resistive RAM (RRAM) element, a phase change memory (PCM) element, a ferroelectric RAM (FeRAM) element, or a magnetic tunneling junction memory (MTJ) element. The transistor MSW in the prior art Figure 1 is used as the magnetic tunneling junction memory element MTJ to avoid mutual interference between different memory cells MC during reading and writing. However, the prior art Figure 1 occupies a larger chip substrate area and is not easy to stack memory cells MC in three dimensions. Figure 5 of this disclosure utilizes the character line WL to select memory elements ME and employs the unipolar current characteristic of a ZD at lower bias voltage to avoid mutual interference between different memory cells MC during read and write operations. It also utilizes the bipolar current characteristic of the ZD at higher reverse bias voltage to perform write operations on memory elements ME that require bipolar data writing. This increases the density of random access memory, saves costs, and facilitates the three-dimensional stacking of memory cells MC.

Referring to Figure 6, according to at least one embodiment of this disclosure, the MTJ (Magnetic Tunnel Junction) memory element is an embodiment of the memory element ME. Other embodiments of the memory element ME may be resistive RAM (RRAM), phase change memory (PCM), or ferroelectric RAM (FeRAM), and the diode D is a zircon diode ZD.

Referring to Figure 7, according to at least one embodiment of this disclosure, the MTJ (Magnetic Tunnel Junction) memory element is an embodiment of the memory element ME. Other embodiments of the memory element ME may be resistive RAM (RRAM), phase change memory (PCM), or ferroelectric RAM (FeRAM), and the diode D is a nano-diode ZD.

Referring to Figure 8, the figure shows an MTJ (Magnetic Tunnel Junction) memory element. The MTJ has two endpoints and is mainly composed of three layers: a tunneling barrier layer, a fixed magnetization layer, and a free magnetization layer, separated by the barrier layer. The arrows in the figure indicate the magnetization direction. The magnetization direction of the fixed magnetization layer is fixed during the manufacturing process. The bidirectional arrows for the free magnetization layer indicate that its magnetization direction can be determined during the data writing process of the MTJ, either in the same direction or opposite to the magnetization direction of the fixed magnetization layer.

Referring to Figure 9, the figure shows an MTJ (Magnetic Tunnel Junction) memory element. When an anti-parallel magnetization direction voltage (Vap) is applied to the MTJ, the magnetization direction of the free layer is reversed compared to the magnetization direction of the fixed layer, creating a high-resistance state between the two terminals of the MTJ.

Referring to Figure 10, the figure shows an MTJ (Magnetic Tunnel Junction) memory element. When a parallel magnetization direction voltage (Vp) is applied to the MTJ, the magnetization direction of the free layer and the fixed layer are aligned, creating a low-resistance state between the two endpoints of the MTJ.

The magnetic tunneling junction (MTJ) memory element and the z-nano diode (ZD) can be constructed by deposition, using methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. The tunneling barrier layer can be made of magnesium oxide (MgO) or other suitable materials. The fixed magnetization layer can be composed of cobalt iron boron (CoFeB) and antiferromagnetic materials (AFM) including platinum (Pt), or other suitable materials. The free magnetization layer can also be made of cobalt iron boron (CoFeB) or other suitable materials.

According to at least one embodiment of this disclosure, the low-resistance state of the memory element ME is determined by a first voltage signal condition applied to the two terminals of the memory element ME, the high-resistance state of the memory element ME is determined by a second voltage signal condition applied to the two terminals of the memory element ME, and the reading of data stored in the memory element ME is performed by applying a third voltage signal condition to the two terminals of the memory element ME to detect the memory. The resistive state of the element ME, wherein the voltage polarity of the first voltage signal condition and the second voltage signal condition is the same, and the absolute voltage value of the second voltage signal condition is greater than the absolute voltage value of the first voltage signal condition, and the absolute voltage value of the third voltage signal condition is less than the absolute voltage values of the first voltage signal condition and the second voltage signal condition; wherein the memory element ME can be a resistive RAM (RRAM) element or a phase change memory (PCM) element.

Referring to FIGS. 2 to 5 , the memory element ME can obtain the first voltage signal condition, the second voltage signal condition and the third voltage signal condition at the two end points of the memory element ME by applying a forward bias voltage greater than the forward conduction voltage (Vt) of the diode D (or Zener diode ZD) between the word line WL and the bit line BL. Resistive RAM (RRAM) elements or Phase Change Memory (PCM) elements can be designed to switch between low resistance states and high resistance states by applying unipolar currents or unipolar bias voltages of different sizes, and use smaller bias voltages to read the resistance state of the memory element.

According to at least one embodiment of this disclosure, the low resistance state of the memory element ME is determined by a first voltage signal condition applied to the two terminals of the memory element ME, the high resistance state of the memory element ME is determined by a second voltage signal condition applied to the two terminals of the memory element ME, and the reading of data stored in the memory element ME is performed by applying a third voltage signal condition. The memory element ME has two terminals for detecting its resistive state. The first voltage signal condition and the second voltage signal condition have opposite voltage polarities. The absolute voltage value of the third voltage signal condition is less than the absolute voltage values of the first and second voltage signal conditions. The memory element ME can be a resistive memory. RAM (RRAM) elements, phase change memory (PCM) elements, ferroelectric RAM (FeRAM) elements, or magnetic tunneling junction memory (MTJ) elements, wherein the MTJ element includes a fixed magnetization layer and a free magnetization layer separated by a tunneling barrier layer.

Referring to FIGS. 4 and 5 , the memory element ME can obtain the first voltage signal condition, the second voltage signal condition and the third voltage signal condition at the two end points of the memory element ME by applying a forward bias voltage greater than the forward conduction voltage (Vt) of the Zener diode ZD and a reverse bias voltage greater than the Zener voltage (Vz) of the Zener diode ZD between the word line WL and the bit line BL. Resistive RAM (RRAM), phase change memory (PCM), ferroelectric RAM (FeRAM), and magnetic tunnel junction memory (MTJ) devices can be designed to switch between low and high resistance states by applying different or the same amount of bipolar current or bipolar bias voltage, and the resistance state of the memory device can be read with a small forward bias voltage.

Resistive RAM (RRAM) devices utilize the formation or interruption of conductive filaments within a material to change its resistance, thereby achieving the purpose of data storage. A basic RRAM consists of two layers of metal electrodes and a transition metal oxide (TMO) layer in between. The key advantage is that the TMO layer generates different resistance values depending on the applied bias voltage. Depending on the polarity of the voltage applied to the variable resistance memory, the resistance switching modes can be classified into two types: unipolar and bipolar. Unipolar uses voltages of the same polarity but different magnitudes for setting (i.e., low resistance state) and resetting (i.e., high resistance state), with the resetting process using Joule heating to melt the conductive filament. Bipolar uses voltages of opposite polarities for setting (i.e., low resistance state) and resetting (i.e., high resistance state). The memory material layer of the variable resistance memory can be, for example, a resistive material of metal oxide, such as iron oxide, aluminum oxide, nickel oxide, potassium oxide, titanium oxide, or other suitable oxide materials. Different properties can be obtained by adjusting the memory material layers according to the method of oxide material deposition, the oxygen-to-metal ratio, and other process conditions.

Phase-change memory (PCM) devices utilize phase-change materials to change their crystalline structure (crystalline state - low resistance or amorphous state - high resistance) through heating and cooling, switching between these states to store data. PCM controls the phase-change state (crystalline state - low resistance or amorphous state - high resistance) of the material by adjusting the magnitude and pulse width of the current applied to it. Applying a shorter and larger current pulse to heat the material and then rapidly cooling it causes the phase-change material to form the amorphous state, which has high resistance. The memory material layer of phase-change memory can be a chalcogenide alloy, such as GeSbTe (GST).

Ferroelectric RAM (FeRAM) devices store data by switching between high-resistance and low-resistance states by changing the polarization direction of the ferroelectric material. Ferroelectric materials possess an equilibrium-state bulk electric dipole moment. Typically, the magnitude and orientation of the dipole moment polarization can be controlled by applying a suitable external electric field. Changes in orientation indicate the stored data (high-resistance or low-resistance state). The ferroelectric layer of ferroelectric memory can be made of iron dioxide (HfO2) and doped ferroelectric materials, or barium titanium oxide (BaTiO3) ferroelectric materials, etc. Data storage is achieved by utilizing the spontaneous polarization principle of ferroelectric materials. The electric dipole moment in a ferroelectric material changes its polarization direction when different electric fields are applied. Different polarization directions result in different resistance states. After the applied electric field is removed, the ferroelectric material can retain some polarization, thus maintaining either a high or low resistance state to store data.

Referring to Figure 11, according to at least one embodiment of this disclosure, the memory cell array MC1-MC9 includes a plurality of memory cells MC1-MC9, a plurality of character lines WL1-WL3, and a plurality of bit lines BL1-BL3. The plurality of memory cells MC1-MC9 are arranged in an array above a substrate plane in a first direction and a second direction perpendicular to the first direction, parallel to the substrate plane. The plurality of character lines WL1-WL3 are arranged along the first direction, and the plurality of bit lines BL1-BL3 are arranged along the second direction. The random access memory further includes a number of character lines. The circuit includes a character line decoder driver 101, a character line sensing circuit 102, and a character line decoder driver 102. The plurality of character lines WL1~WL3 are connected to the character line decoder driver 101, and the plurality of character lines BL1~BL3 are connected to the character line sensing circuit 102 and the character line decoder driver 102. The character line decoder driver 101 includes a plurality of character line switches MSW1~3, each of which is connected to the plurality of character lines WL1~WL3. The plurality of character line switches MSW1~3 are transistor switches or transmission gate switches. The random access memory further includes a timing control circuit 103, which is connected to a character line decoder driver circuit 101, a bit line sensing circuit 102, and a bit line decoder driver circuit 102. The character line decoder driver circuit 101 controls the plurality of character line switches MSW1 to 3 via control signals from WL Control1 to 3. In Figure 11, the magnetic tunneling junction memory element MTJ is an embodiment of the memory element ME in Figure 2 and Figure 4. These magnetic tunneling junction memory elements MTJ in Figure 11 can be implemented by replacing them with resistive RAM (RRAM), phase change memory (PCM), or ferroelectric RAM (FeRAM) elements to achieve the same data storage purpose. The Zener diode ZD in Figure 11 is an embodiment of the diode D in Figure 2 and the Zener diode ZD in Figure 4.

The memory cell arrays MC1-MC9 in Figure 11 are only examples of a single memory cell array consisting of nine 3x3 memory cells (MC1-MC9). The actual number of memory cells in a random access memory array can be designed according to the specific requirements of the chip.

The character line decoding driver circuit 101 in Figure 11 provides the voltage signals required for a plurality of character lines WL1~WL3. The bit line sensing circuit 102 and the bit line decoding driver circuit 103 provide the voltage signals required for a plurality of bit lines BL1~BL3, and sense and read the voltage signals of the plurality of bit lines BL1~BL3 for transmission. The timing control circuit 103 controls the circuit operation timing of the character line decoding driver circuit 101, the bit line sensing circuit 102, and the bit line decoding driver circuit 103.

Referring to Figure 12, according to at least one embodiment of this disclosure, the memory cell array MC1-MC9 includes a plurality of memory cells MC1-MC9, a plurality of character lines WL1-WL3, and a plurality of bit lines BL1-BL3. The plurality of memory cells MC1-MC9 are arranged in an array above a substrate plane in a first direction and a second direction perpendicular to the first direction, parallel to the substrate plane. The plurality of character lines WL1-WL3 are arranged along the first direction, and the plurality of bit lines BL1-BL3 are arranged along the second direction. The random access memory further includes a number of character lines. The circuit includes a character line decoder driver 101, a character line sensing circuit 102, and a character line decoder driver 102. The plurality of character lines WL1~WL3 are connected to the character line decoder driver 101, and the plurality of character lines BL1~BL3 are connected to the character line sensing circuit 102 and the character line decoder driver 102. The character line decoder driver 101 includes a plurality of character line switches MSW1~3, each of which is connected to the plurality of character lines WL1~WL3. The plurality of character line switches MSW1~3 are transistor switches or transmission gate switches. The random access memory further includes a timing control circuit 103, which is connected to a character line decoder driver circuit 101, a bit line sensing circuit 102, and a bit line decoder driver circuit 102. The character line decoder driver circuit 101 controls the plurality of character line switches MSW1 to 3 via control signals from WL Control1 to 3. In Figure 12, the magnetic tunneling junction memory element (MTJ) is an embodiment of the memory element ME in Figure 3 and Figure 5. These MTJs in Figure 12 can be implemented by replacing them with resistive RAM (RRAM), phase change memory (PCM), or ferroelectric RAM (FeRAM) elements to achieve the same data storage purpose. The Zener diode (ZD) in Figure 12 is an embodiment of the diode D in Figure 3 and the Zener diode ZD in Figure 5.

The memory cell arrays MC1-MC9 in Figure 12 are only examples of a single memory cell array consisting of nine 3x3 memory cells. The actual number of memory cells in a random access memory array can be designed according to the specific requirements of the chip.

The character line decoding driver circuit 101 in Figure 12 provides the voltage signals required for a plurality of character lines WL1~WL3. The bit line sensing circuit 102 and the bit line decoding driver circuit 103 provide the voltage signals required for a plurality of bit lines BL1~BL3, and sense and read the voltage signals of the plurality of bit lines BL1~BL3 for transmission. The timing control circuit 103 controls the circuit operation timing of the character line decoding driver circuit 101, the bit line sensing circuit 102, and the bit line decoding driver circuit 103.

Referring to Figure 13, according to at least one embodiment of this disclosure, the random access memory further includes a plurality of memory cell arrays, wherein the plurality of memory cells MC in each memory cell array (Figure 13) are connected to a plurality of word lines WL1~WL3 and a plurality of bit lines BL1~BL3 in a manner perpendicular to the substrate plane to form a memory cell array layer (one of Memory Cell Array Layers 1~3 in Figures 13 and 14); referring to Figure 14, the memory cell arrays Memory Cell Array Layers 1~3 are located on different planar layers to form a plurality of memory cell array layers Memory Cell Array above the substrate plane. Layers 1-3, the plurality of word lines (WLs) and the plurality of bit lines (BLs) of the plurality of memory cell array layers 1-3 are vertically connected downwards from the edges of the plurality of memory cell array layers 1-3 to the substrate plane, respectively connecting to the word line decoding driver circuit 101 (not shown, located in the memory control circuit layer), the bit line sensing circuit 102 (not shown, located in the memory control circuit layer), and the bit line decoding driver circuit 102 (not shown, located in the memory control circuit layer) located on the substrate plane. Layers are used to form a three-dimensional structure consisting of multiple memory cell array layers (Layers 1-3).

Referring to Figures 15, 11, and 12, according to at least one embodiment of this disclosure, the condition for storing the low-resistance state of the memory element ME of one of the plurality of memory cells MC1 to MC9—for example, MC5 (Write 1 in Figure 15) includes: the word line decoding driver circuit 101 applying a word line voltage to the word line WL2 of the memory cell MC5, and the bit line decoding driver circuit 102 applying a bit line voltage to the memory cell MC5. Bit line BL2 of memory element ME is used to provide a first voltage signal condition at the two terminals of the memory element ME. This first voltage signal condition determines the low resistance state of the memory element ME. Furthermore, the character line decoding driver circuit 101 maintains the other character lines WL1 and WL3 in a floating state by turning off the character line switches MSW1 and MSW3 connected to them. The bit line decoding driver circuit 102 applies a voltage equal to the character line voltage minus the diode D (or The forward conduction voltage (Vt) signal of ZD is applied to other bit lines BL1, BL3, or the decoding driver circuit 102 of that bit line keeps the other bit lines BL1, BL3 in a floating state. The memory element ME can be a resistive RAM (RRAM), a phase change memory (PCM), a ferroelectric RAM (FeRAM), or a magnetic tunnel junction memory (MTJ) element.

Referring to Figures 15-18, where Vap = antiparallel magnetization voltage of the magnetic tunneling junction memory element MTJ, Vp = parallel magnetization voltage of the magnetic tunneling junction memory element MTJ, Vt = forward conduction voltage of the ZN diode ZD, Vz = reverse ZN diode ZD, and Vpp = ... The voltage in the antiparallel magnetization direction of the magnetic tunneling junction memory element MTJ plus the forward conduction voltage of the Zener diode ZD plus the parallel magnetization voltage of the magnetic tunneling junction memory element MTJ plus the reverse Zener voltage of the Zener diode ZD (absolute value), Vr = the read voltage of the magnetic tunneling junction memory element MTJ.

Referring to Figures 15, 11, and 12, according to at least one embodiment of this disclosure, the condition for storing the low-resistance state of the magnetic tunneling junction memory element MTJ of one of the plurality of memory cells MC1 to MC9—for example, MC5—(Write 1 in Figure 15) includes: the word line decoding driver circuit 101 applying a word line voltage Vap + Vt to the word line WL2 (WL in Figure 15) of the memory cell MC5, and the bit line decoding driver circuit 102 applying a bit line voltage Vpp to the memory cell MC5. Bit line BL2 (BL in Figure 15) is used to provide a first voltage signal condition Vp at the two terminals of the magnetic tunneling junction memory element MTJ. This first voltage signal condition Vp determines the low resistance state of the magnetic tunneling junction memory element MTJ. Furthermore, the word line decoding driver circuit 101 maintains the other word lines WL1 and WL3 (Other WLs in Figure 15) in a floating state by turning off the word line switches MSW1 and MSW3 connected to them. Floating: The bit line decoder driver 102 applies a voltage signal Vap equal to the word line voltage Vap + Vt minus the forward conduction voltage (Vt) of the Zener diode ZD to the other bit lines BL1, BL3 (Other BLs in Figure 15), or the bit line decoder driver 102 keeps the other bit lines BL1, BL3 (Other BLs in Figure 15) in a floating state.

Referring to Figures 16, 11, and 12, according to at least one embodiment of this disclosure, the high-resistance state of the memory element ME storing one of the plurality of memory cells MC1 to MC9—for example, MC5—is described in Figure 16 (Write). 0) Includes: The character line decoding driver circuit 101 applies a character line voltage to the character line WL2 of the memory cell MC5, and the bit line decoding driver circuit 102 applies a bit line voltage to the bit line BL2 of the memory cell MC5, so that the two terminals of the memory element ME have a second voltage signal condition, the second voltage signal condition determines the high resistance state of the memory element ME, and the character line decoding driver circuit 101 keeps the other character lines WL1 and WL3 in a floating state by turning off the character line switches MSW1 and MSW3 connected to them. Floating: The bit line decoding driver circuit 102 applies a voltage signal equal to the word line voltage minus the forward conduction voltage (Vt) of the diode D (or ZD) to the other bit lines BL1, BL3, or the bit line decoding driver circuit 102 keeps the other bit lines BL1, BL3 in a floating state. The memory element ME can be a resistive RAM (RRAM), phase change memory (PCM), ferroelectric RAM (FeRAM), or magnetic tunnel junction memory (MTJ) element.

Referring to Figures 16, 11, and 12, according to at least one embodiment of this disclosure, the high-resistivity state of the magnetic tunneling junction memory element MTJ storing one of the plurality of memory cells MC1 to MC9—for example, MC5—is described in Figure 16 (Write). 0) Includes: The character line decoding driver circuit 101 applies a character line voltage Vap+Vt to the character line WL2 (WL in FIG. 16) of the memory cell MC5, and the bit line decoding driver circuit 102 applies a bit line voltage 0V to the bit line BL2 (BL in FIG. 16) of the memory cell MC5, so that the two terminals of the magnetic tunneling junction memory element MTJ have a second voltage signal condition Vap. The second voltage signal condition Vap determines the high resistance state of the magnetic tunneling junction memory element MTJ. Furthermore, the character line decoding driver circuit 101 closes other character lines WL1 and WL3 (Other in FIG. 16). The character line switches MSW1 and MSW3 connected to the WLs (other WLs in Figure 16) keep the other character lines WL1 and WL3 (other WLs in Figure 16) floating. The bit line decoder driver 102 applies a voltage signal Vap equal to the character line voltage Vap + Vt minus the forward conduction voltage (Vt) of the Zener diode ZD to the other bit lines BL1 and BL3 (other BLs in Figure 16), or the bit line decoder driver 102 keeps the other bit lines BL1 and BL3 (other BLs in Figure 16) floating.

Referring to Figures 17, 11, and 12, according to at least one embodiment of this disclosure, the condition for reading the stored data of memory element ME of one of the plurality of memory cells MC1 to MC9—for example, MC5 (Read in Figure 17)—includes: the word line decoding driver circuit 101 applies a word line voltage to the word line WL2 of the memory cell MC5, and the bit line decoding driver circuit 102 applies a bit line voltage to the memory cell MC5. Bit line BL2 of memory element ME is used to provide a third voltage signal condition at the two terminals of the memory element ME. This third voltage signal condition cannot determine whether the memory element ME is in a high-resistance or low-resistance state. The voltage value at the first terminal of the memory element ME is higher than the voltage value at the second terminal of the memory element ME. Furthermore, the character line decoding driver circuit 101 maintains the other character lines WL1 and WL3 in a floating state by turning off the character line switches MSW1 and MSW3 connected to them. Floating, then the bit line BL2 starts sensing through the bit line sensing circuit 102, and the other bit lines BL1 and BL3 start sensing through the bit line sensing circuit 102 or the bit line decoding driver circuit 102 keeps the other bit lines BL1 and BL3 in a floating state; and after a first time interval T1 after the bit line BL2 starts sensing through the bit line sensing circuit 102, the bit line decoding driver circuit 102 transmits the voltage value of the bit line BL2 after sensing. The memory element ME can be a resistive RAM (RRAM), a phase change memory (PCM), a ferroelectric RAM (FeRAM), or a magnetic tunnel junction memory (MTJ) element.

Referring to Figures 17, 11, and 12, according to at least one embodiment of this disclosure, the conditions for reading stored data from the magnetic tunneling junction memory element MTJ of one of the plurality of memory cells MC1 to MC9—for example, MC5—(Read in Figure 17) include: the character line decoding driver circuit 101 applying a character line voltage Vap+Vt+Vr to the character line WL2 (WL in Figure 17) of the memory cell MC5, and the bit line decoding driver circuit 102 applying a bit line voltage Vap to the memory cell MC5. Bit line BL2 (BL in Figure 17) is used to enable a third voltage signal condition Vr at the two terminals of the magnetic tunneling junction memory element MTJ. This third voltage signal condition Vr cannot determine whether the magnetic tunneling junction memory element MTJ is in a high-resistance or low-resistance state. The voltage at the first terminal of the magnetic tunneling junction memory element MTJ is higher than the voltage at the second terminal. Furthermore, the character line decoding driver circuit 101 maintains the other character lines WL1 and WL3 (Other WLs in Figure 17) in a floating state by turning off the character line switches MSW1 and MSW3 connected to them. The circuit initiates a floating state, allowing bit line BL2 (BL in Figure 17) to begin sensing via bit line sensing circuit 102. Other bit lines BL1 and BL3 (Other BLs in Figure 17) either begin sensing via bit line sensing circuit 102 or the bit line decoding driver circuit 102 maintains the floating state of the other bit lines BL1 and BL3 (Other BLs in Figure 17). After a first time interval T1 following the initiation of sensing by bit line BL2 (BL in Figure 17) via bit line sensing circuit 102, the bit line decoding driver circuit 102 transmits the induced voltage value of bit line BL2 (BL in Figure 17).

Referring to Figures 18, 11, and 12, according to at least one embodiment of this disclosure, the conditions for maintaining the storage of data in the memory elements ME of the plurality of memory cells MC1-MC9 in the memory cell array MC1-MC9 (No Operation in Figure 18) include: the character line decoding driver circuit 101 keeps all character lines WL1-WL3 in a floating state by turning off the character line switches MSW1-MSW3 connected to all character lines WL1-WL3. Floating: The bit line decoding driver circuit 102 applies a predetermined bit line voltage to all bit lines BL1~BL3, or the bit line decoding driver circuit 102 keeps all bit lines BL1~BL3 in a floating state.

Referring to Figures 18, 11, and 12, according to at least one embodiment of this disclosure, the conditions for maintaining the data storage of the magnetic tunneling junction memory elements MTJ of the plurality of memory cells MC1-MC9 in the memory cell array MC1-MC9 (No Operation in Figure 18) include: the character line decoding driver circuit 101 maintains all character lines WL1-WL3 (All WLs in Figure 18) in a floating state by turning off the character line switches MSW1-MSW3 connected to all character lines WL1-WL3 (All WLs in Figure 18). Floating: The bit line decoding driver circuit 102 applies a predetermined bit line voltage Vap to all bit lines BL1~BL3 (All BLs in Figure 18), or the bit line decoding driver circuit 102 keeps all bit lines BL1~BL3 (All BLs in Figure 18) in a floating state.

Referring to Figures 11 and 12, according to at least one embodiment of this disclosure, the character line decoding driver circuit 101 applies a character line voltage to a character line WL2, and the character line decoding driver circuit 101 keeps the other character lines WL1 and WL3 in a floating state by turning off the character line switches MSW1 and MSW3 connected to the other character lines WL1 and WL3, and the bit line decoding driver circuit 102 applies the same or different bit line voltages to the plurality of bit lines BL1 to BL3, so that the plurality of memory cells MC4 to MC6 connected to the character line WL2 simultaneously perform the writing and storage of a plurality of data to implement a high-bandwidth data writing operation.

Referring to Figures 11 and 12, according to at least one embodiment of this disclosure, the character line decoding driver circuit 101 applies a character line voltage to a character line WL2, and the character line decoding driver circuit 101 maintains the other character lines WL1 and WL3 in a floating state by turning off the character line switches MSW1 and MSW3 connected to them. The multiple bit lines BL1~BL3 are initiated to sense by the bit line sensing circuit 102; and after a first time interval following the initiation of sensing by the bit line sensing circuit 102, the bit line decoding driver circuit 102 transmits the sensed voltage values of the multiple bit lines BL1~BL3, so that the multiple memory cells MC4~MC6 connected to the word line WL2 can simultaneously read multiple data points to perform a high-bandwidth data reading operation.

The operations shown in Figures 15 to 18, based on the operating conditions of the memory cell arrays MC1 to MC9 of at least one embodiment of this disclosure, ensure that the written or read operation is correctly performed on the operated memory cell MC; and the data stored in other memory cells MC connected to the same character line WL, other memory cells MC connected to the same bit line BL, or several memory cells MC connected to other character lines WL are not affected.

The foregoing has revealed some features of the embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a design or modification to achieve the same purpose and/or the same advantages as the embodiments described in this disclosure. Those skilled in the art should also recognize that these equivalent designs or modifications do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

Therefore, the random access memory (RAM) disclosed herein has fewer memory cell (MC) endpoints than prior art RAM, resulting in a smaller chip substrate area for increased RAM density, cost savings, and easier three-dimensional stacking of MCs. It is indeed novel and progressive, possessing an inventive step and non-obviousness. Furthermore, compared to existing technologies, this disclosure has outstanding substantial features and significant progress; this disclosure truly proposes a practical and effective solution to the problem.

BL: Bitline

D: Diode

MC: Memory Cells

ME: Memory element

WL: Character Line

Claims (14)

A random access memory includes: at least one memory cell array, the memory cell array including: at least one memory cell having two endpoints, a first endpoint of the memory cell connected to a word line, and a second endpoint of the memory cell connected to a bit line, the memory cell including: a type of diode having an anode and a cathode, the anode of the diode being connected to the word line; and a memory element having two endpoints, the first endpoint of the memory element being connected to the cathode of the diode, and the second endpoint of the memory element being connected to the bit line. The diode has a forward conduction voltage, and the memory element stores data. The low resistance state of the memory element is the first data state, and the high resistance state of the memory element is the second data state. A random access memory includes: at least one memory cell array, the memory cell array including: at least one memory cell having two endpoints, a first endpoint of the memory cell connected to a word line, and a second endpoint of the memory cell connected to a bit line, the memory cell including: a memory element having two endpoints, the first endpoint of the memory element connected to the word line; and a diode having an anode and a cathode, the anode of the diode connected to the second endpoint of the memory element, and the cathode of the diode connected to the bit line. The diode has a forward conduction voltage, and the memory element stores data. The low resistance state of the memory element is the first data state, and the high resistance state of the memory element is the second data state. For example, the random access memory in Request 1, wherein the diode system is a Zener diode, and the Zener diode is further characterized by having a reverse Zener voltage. For example, the random access memory in claim 2, wherein the diode system is a Zener diode, and the Zener diode is further characterized by having a reverse Zener voltage. For example, random access to memory as requested in items 1, 2, 3, or 4, wherein the low resistance state of the memory element is determined by a first voltage signal condition applied to the two terminals of the memory element, the high resistance state of the memory element is determined by a second voltage signal condition applied to the two terminals of the memory element, and the reading of data stored in the memory element is performed by detecting the memory by applying a third voltage signal condition to the two terminals of the memory element. The resistance state of the element, wherein the voltage polarity of the first voltage signal condition and the second voltage signal condition is the same, and the absolute voltage value of the second voltage signal condition is greater than the absolute voltage value of the first voltage signal condition, and the absolute voltage value of the third voltage signal condition is less than the absolute voltage values of the first voltage signal condition and the second voltage signal condition; wherein the memory element is a resistive RAM (RRAM) element or a phase change memory (PCM) element. For example, in request 3 or 4, random access to memory, wherein the low resistance state of the memory element is determined by a first voltage signal condition applied to the two terminals of the memory element, the high resistance state of the memory element is determined by a second voltage signal condition applied to the two terminals of the memory element, and the reading of data stored in the memory element is performed by applying a third voltage signal condition. The two terminals of the memory element are used to detect the resistance state of the memory element, wherein the voltage polarities of the first voltage signal condition and the second voltage signal condition are opposite, and the absolute voltage value of the third voltage signal condition is less than the absolute voltage values of the first voltage signal condition and the second voltage signal condition; wherein the memory element is a resistive memory. RAM (RRAM) elements, phase change memory (PCM) elements, ferroelectric RAM (FeRAM) elements, or magnetic tunneling junction memory (MTJ) elements, wherein the magnetic tunneling junction memory element includes a fixed magnetization layer and a free magnetization layer separated by a tunneling barrier layer. Random access memory as described in claims 1, 2, 3, or 4, wherein the memory cell array includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, the plurality of memory cells being arranged in an array above a substrate plane in a first direction and a second direction perpendicular to the first direction, parallel to the substrate plane; the plurality of word lines being arranged along the first direction; and the plurality of bit lines being arranged along the second direction; and the random access memory further includes... It includes a character line decoding driver circuit, a bit line sensing circuit, and a bit line decoding driver circuit, wherein the plurality of character lines are connected to the character line decoding driver circuit, and the plurality of bit lines are connected to the bit line sensing circuit and the bit line decoding driver circuit. The character line decoding driver circuit includes a plurality of character line switches to be connected to the plurality of character lines respectively, and the plurality of character line switches are transistor switches or transmission gate switches. As in claim 7, the random access memory further includes a plurality of memory cell arrays, wherein the plurality of memory cells in each memory cell array are connected to a plurality of word lines and a plurality of bit lines in a manner perpendicular to the substrate plane to form a memory cell array layer; wherein each memory cell array is located on different planar layers to form a plurality of [missing information - likely related to the substrate plane]. A plurality of memory cell array layers, wherein the plurality of word lines and the plurality of bit lines of the plurality of memory cell array layers are vertically connected downward from the edges of the plurality of memory cell array layers to the substrate plane to respectively connect the word line decoding driver circuit, the bit line sensing circuit and the bit line decoding driver circuit located on the substrate plane, thereby forming a three-dimensional structure comprising a plurality of memory cell array layers. As in claim 7, random access to memory, wherein the conditions for the low-resistance state of the memory element storing one of the plurality of memory cells include: the word line decoding driver applies a word line voltage to the word line of the memory cell, and the bit line decoding driver applies a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a first voltage signal condition, the first voltage signal condition determining the low-resistance state of the memory element, and the word line decoding driver... The circuit keeps other word lines floating by turning off the word line switches connected to them. The bit line decoder driver applies a voltage signal equal to the word line voltage minus the forward conduction voltage of the diode to the other bit lines, or the bit line decoder driver keeps the other bit lines floating. As in claim 7, random access to memory, wherein the conditions for the high-resistance state of the memory element storing one of the plurality of memory cells include: the character line decoding driver applies a character line voltage to the character line of the memory cell, and the bit line decoding driver applies a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a second voltage signal condition, the second voltage signal condition determining the high-resistance state of the memory element, and the character line decoding driver applies a bit line voltage to the bit line of the memory cell, thereby giving the two terminals of the memory element a second voltage signal condition, the second voltage signal condition determining the high-resistance state of the memory element, and the character line decoding driver applying a bit line voltage to the bit line of the memory cell. The bit line decoding driver circuit keeps other word lines floating by turning off the word line switches connected to other word lines. The bit line decoding driver circuit applies a voltage signal that is the same as the word line voltage minus the forward conduction voltage of the diode to other bit lines or keeps other bit lines floating. For example, in the random access to memory as described in claim 7, the conditions for reading the stored data of the memory element in one of the plurality of memory cells include: the word line decoding driver applies a word line voltage to the word line of the memory cell, and the bit line decoding driver applies a bit line voltage to the bit line of the memory cell, so that the two terminals of the memory element have a third voltage signal condition, which cannot determine the high resistance state or low resistance state of the memory element, wherein the voltage value of the first terminal of the memory element is... The voltage is higher than that of the second terminal of the memory element, and the character line decoding driver circuit keeps the other character lines floating by turning off the character line switches connected to the other character lines, and then makes the character line start sensing through the character line sensing circuit, and the other character lines start sensing through the character line sensing circuit or the character line decoding driver circuit keeps the other character lines floating; and after a first time interval after the character line starts sensing through the character line sensing circuit, the character line decoding driver circuit transmits the voltage value of the character line after sensing. As in claim 7, random access to memory, wherein the conditions for maintaining the stored data of the memory elements of the plurality of memory cells in the memory cell array include: the word line decoder driver keeps all word lines in a floating state by turning off the word line switches connected to all word lines, the bit line decoder driver applies a predetermined bit line voltage to all bit lines, or the bit line decoder driver keeps all bit lines in a floating state. For example, in the random access memory of claim 7, the character line decoder applies a character line voltage to a character line, and the character line decoder keeps other character lines in a floating state by turning off the character line switches connected to other character lines, and the bit line decoder applies the same or different bit line voltages to the plurality of bit lines, so that the plurality of memory cells connected to the character lines can simultaneously write and store a plurality of data. As in claim 7, random access to memory, wherein the character line decoding driver applies a character line voltage to a character line, and the character line decoding driver keeps the other character lines in a floating state by turning off the character line switches connected to the other character lines, and then causes the plurality of character lines to start sensing through the character line sensing circuit; and after a first time interval after the plurality of character lines start sensing through the character line sensing circuit, the character line decoding driver transmits the voltage value of the plurality of character lines after sensing, so that the plurality of memory cells connected to the character line can simultaneously read a plurality of data.