TWM673290U - Paddle device - Google Patents

Abstract

A paddle device is used to transmitting high-speed signals, and the paddle device includes a main board, a first signal pair and a second signal pair. The main board includes a surface layer and a specific layer, and the specific layer and the surface layer are located in different planes. The first signal pair include a pair of first trace sections and a plurality of first ends, the first ends are respectively and correspondingly located at two ends of each of the pair of first trace sections, and the pair of first trace sections and the first ends are located in the surface layer. The second signal pair include a pair of second trace sections and a plurality of second ends, the second ends are respectively and correspondingly located at two ends of each of the pair of second trace sections, the second ends are located in the surface layer, and the pair of second trace sections are located in the specific layer.

Description

adapter

This work relates to a switching device, particularly a switching device used to transmit high-speed signals.

With the development of data centers and high-performance computing systems, the demand for riser cables within these systems is increasing. However, existing high-speed cable modules often suffer from signal loss, crosstalk, and insufficient heat dissipation when dealing with high-speed data transmission and high-density wiring. Furthermore, space limitations and assembly difficulties restrict the widespread application of existing technologies.

Furthermore, referring to Figure 1, the routing scheme for adapter 2 of the high-speed cable module uses closely parallel routing of differential pairs on the surface. However, this routing scheme introduces crosstalk into the high-speed cable module, particularly leading to poor crosstalk characteristics. In high-speed and high-frequency transmission, crosstalk significantly impacts the eye diagram, especially in PAM4 (four-level pulse amplitude modulation) signals. Crosstalk reduces the signal voltage amplitude and increases jitter, thereby narrowing the vertical and horizontal openings of the eye diagram. Because the spacing between each voltage layer in a PAM4 signal is narrower, higher signal integrity requirements are placed on it. Consequently, crosstalk can increase the bit error rate and reduce data transmission reliability.

Therefore, how to design a switching device to improve crosstalk is a major research topic that the authors of this project want to conduct.

To address the aforementioned issues, the present disclosure provides an adapter device that overcomes the problems of conventional technology. The adapter device includes a motherboard, a first signal pair, and a second signal pair. The motherboard includes a surface layer and a specific layer, and the specific layer and the surface layer are located on different planes. The first signal pair includes a pair of first trace segments and a plurality of first endpoints, wherein the first endpoints correspond to the ends of each of the pair of first trace segments, and the pair of first trace segments and the first endpoints are located on the surface layer. The second signal pair includes a pair of second trace segments and a plurality of second endpoints, wherein the second endpoints correspond to the ends of each of the pair of second trace segments, and the second endpoints are located on the surface layer, while the pair of second trace segments are located on the specific layer.

In one embodiment, the motherboard includes a ground layer. The ground layer is located on a different plane from the specific layer and the surface layer, and the ground layer does not have a first signal pair and a second signal pair.

In one embodiment, the angle at which the first signal pair and the second signal pair intersect across layers is 0 to 180 degrees.

In one embodiment, when the angle at which the first signal pair and the second signal pair intersect across layers is 0 degrees or 180 degrees, the specific layer is disposed between the ground layer and the surface layer.

In one embodiment, the ground layer is disposed between the surface layer and the specific layer.

In one embodiment, the motherboard is a six-layer board. The first and sixth layers of the motherboard are two surface layers, each of which is provided with a first signal pair and the second endpoints. The third and fifth layers of the motherboard are two special layers, each of which is provided with the pair of second trace segments. The second and fourth layers of the motherboard are ground layers. The first signal pair on the first layer and the second signal pair on the third layer have a first angle therebetween, and the first signal pair on the sixth layer and the second signal pair on the fifth layer have a second angle therebetween, and the first angle and the second angle are different.

In one embodiment, the pair of first terminals at at least one end of the pair of first trace segments extend to form a pair of first signal terminals, and the pair of second terminals on the same side of the second signal pair as the pair of first signal terminals extend to form a pair of second signal terminals. The pair of first signal terminals and the pair of second signal terminals are configured for connection to an external device.

In one embodiment, the motherboard further includes two pairs of conductive vias. The pair of conductive vias penetrate the surface layer and the specific layer, allowing the two ends of the pair of second trace segments to be electrically connected to the corresponding second endpoints.

In one embodiment, the motherboard further includes a pair of ground terminals and a grounding region. The pair of ground terminals are disposed on the surface and are arranged in parallel on either side of the second endpoints of at least one end of the pair of second trace segments. The grounding region is disposed on the surface and electrically connected to the pair of ground terminals. The pair of ground terminals and the grounding region surround the second endpoints.

In one embodiment, the motherboard further includes a ground region. The ground region is disposed on a specific layer and surrounds the pair of second trace segments.

The primary purpose and purpose of this disclosure is to significantly improve crosstalk by disposing the first signal pair and the second signal pair on different layers of the adapter, thereby reducing crosstalk caused by the first signal pair and the second signal pair.

To further understand the techniques, means, and effects employed by this disclosure to achieve its intended purpose, please refer to the following detailed description and accompanying figures. It is believed that this will provide a deeper and more detailed understanding of the purpose, features, and characteristics of this disclosure. However, the accompanying figures are provided for reference and illustration purposes only and are not intended to limit this disclosure.

100: High-speed cable module

1: Connector

2: Adapter

MB: Motherboard

20-1~20-n: Floor

2A: First side

2B: Second side

22, 22A, 22B: First signal terminal

22-1, 22A-1, 22B-1: First terminal

22-2, 22A-2, 22B-2: Second terminal

24, 24A, 24B: Second signal terminals

24-1, 24A-1, 24B-1: Third terminal

24-2, 24A-2, 24B-2: Fourth terminal

26: First signal pair

26A: First endpoint

26-1: First Route

26-2: Second Route

28: Second signal pair

28A: Second endpoint

28-1: Third Route

28-2: Fourth Route

H1: First conductive hole

H2: Second conductive hole

GND: Ground area

Pgnd: ground terminal

3: Cables

200: External device

I, II: Waveform

Figure 1 is a diagram of the surface wiring structure of a conventional adapter device; Figure 2 is a diagram of the exterior structure of a high-speed cable module for transmitting high-speed signals according to the present disclosure; Figure 3 is a diagram of the exterior structure of the adapter device for transmitting high-speed signals according to the present disclosure; Figure 4A is a diagram of the surface wiring structure of the adapter device according to the first embodiment of the present disclosure; Figure 4B is a diagram of the wiring structure of a specific layer of the adapter device according to the first embodiment of the present disclosure; Figure 4C is a schematic diagram of the cross-layer structure of the adapter device according to the first embodiment of the present disclosure; Figure 4D is a diagram of the ground layer wiring structure of the adapter device according to the first embodiment of the present disclosure; Figure 4E is a diagram of the wiring structure of the motherboard along the first conductive via to the second conductive via of the first embodiment of the present disclosure. A cross-sectional view in the direction of the electrical via; FIG5A is a comparative diagram of crosstalk of a first signal pair when a conventional adapter and the adapter of the first embodiment of the present disclosure perform signal transmission; FIG5B is a comparative diagram of crosstalk of a second signal pair when a conventional adapter and the adapter of the first embodiment of the present disclosure perform signal transmission; FIG6A is a diagram of the surface layer wiring structure of the adapter of the second embodiment of the present disclosure; FIG6B is a diagram of the wiring structure of a specific layer of the adapter of the second embodiment of the present disclosure; FIG6C is a schematic diagram of the cross-layer structure of the adapter of the second embodiment of the present disclosure; and FIG6D is a diagram of the ground layer wiring structure of the adapter of the second embodiment of the present disclosure.

The technical content and detailed description of the present disclosure are provided below with accompanying diagrams. Please refer to FIG. 2 for an external structural diagram of a high-speed cable module for transmitting high-speed signals, and refer to FIG. The high-speed cable module 100 of the present disclosure can be, for example, but not limited to, a Mini Cool Edge IO (MCIO) or similar device capable of transmitting high-speed signals. The high-speed cable module 100 is connected to a connector (not shown) of an external device 200 (for example, but not limited to, a server motherboard, storage device, or the like). High-speed cable module 100 includes components such as a connector 1, an adapter 2, and a cable 3. These components are assembled through welding and other methods to form high-speed cable module 100. Adapter 2 typically has differential pairs (i.e., closely spaced parallel traces) on the surface, but this is not limited to this. It can also have non-differential pairs, and the arrangement can be tailored to actual needs.

Furthermore, the high-speed cable module 100 is widely used in high-density connection systems to achieve high-speed data transmission and stable signal integrity. This disclosure relates to cable assembly technology in data centers and high-performance computing. Specifically, it focuses on the structural design and performance optimization of the adapter 2 to enhance its space utilization, reliability, and transmission performance. This technology is particularly suitable for high-speed interconnect scenarios such as server motherboards, storage devices, and PCIe.

Please refer to FIG3 for an external structural diagram of the adapter device disclosed herein for transmitting high-speed signals, and refer to FIG2 in conjunction therewith. The adapter device 2 is used to transmit high-speed signals, and the adapter device 2 includes a motherboard MB, a first signal pair 26, and a second signal pair 28. The motherboard MB is a multi-layer board, and the first signal pair 26 and the second signal pair 28 are located on at least one surface layer 20-1, 20-n of the adapter device 2 (shown as surface layer 20-1). Specifically, the first signal pair 26 includes a pair of first trace segments and a plurality of first endpoints 26A. The first endpoints 26A are located at the two ends of each first trace segment (i.e., two pairs of first endpoints 26A at the two ends). The first trace segments and the first endpoints 26A are located on the surface layer 20-1. The second signal pair 28 includes a pair of second trace segments (not shown) and multiple second endpoints 28A. The second endpoints 28A are located at the two ends of each second trace segment (not shown), respectively (i.e., two pairs of second endpoints 28A in total). The second endpoints 28A are also located on the surface layer 20-1. The second trace segment (not shown) is not located on the surface layer 20-1 and is electrically connected to the second endpoints 28A.

In Figure 3, the first endpoints 26A of at least one end of a first trace segment can be extended to form a first signal terminal 22 (herein, both pairs of first endpoints 26A form the first signal terminal 22. The first signal terminal 22 and first endpoints 26A described below may represent the same thing, and the distinction between them is for convenience of illustration only, and will not be further described). Similarly, the second endpoints 28A of at least one end of a second trace segment (not shown) can be extended to form a second signal terminal 24 (herein, both pairs of second endpoints 28A form the second signal terminal 24. The second signal terminal 24 and second endpoints 28A described below may represent the same thing, and the distinction between them is for convenience of illustration only, and will not be further described). If only one side of the first and second endpoints 26A and 28A form the first and second signal terminals 22 and 24, respectively, they are located on the same side of the motherboard MB. Referring to FIG. 2 , the first signal terminals 22 and the second signal terminals 24 are located on the same side of the motherboard MB and can serve as edge connectors (i.e., gold fingers) for connecting external devices 200. In another embodiment, the first terminal 26A and the second terminal 28A on the other side can similarly form a signal terminal structure to serve as a relay adapter board, or they can form a soldering pad, soldering pad, or a larger soldering area. All of these structures facilitate soldering of the cable 3. Furthermore, when the two pairs of first terminals 26A and the two pairs of second terminals 28A extend to form the first signal terminals 22 and the second signal terminals 24, respectively, the first signal terminals 22 and the second signal terminals 24 are both located on the surface layer 20-1 of the motherboard MB. A pair of first signal terminals 22 and a pair of second signal terminals 24 are disposed in parallel on a first side 2A of the surface layer 20-1 of the adapter 2. Furthermore, another pair of first signal terminals 22 and another pair of second signal terminals 24 are disposed in parallel on a second side 2B of the surface layer 20-1 of the adapter 2.

Taking differential pairs as an example, each pair of first signal terminals 22 includes a first terminal 22-1 and a second terminal 22-2, and each pair of second signal terminals 24 includes a third terminal 24-1 and a fourth terminal 24-2. The first terminal 22-1 and the second terminal 22-2 are arranged side by side, and the third terminal 24-1 and the fourth terminal 24-2 are arranged side by side. The first side 2A can be the side for connecting to the external device 200, and the second side 2B can be the side for soldering the cable 3. In one embodiment, the second side 2B is preferably substantially parallel to the first side 2A, but this is not limiting. The first side 2A and the second side 2B can be any two sides of the motherboard MB.

Please refer to Figure 4A for a diagram of the surface wiring structure of the adapter device according to the first embodiment of the present disclosure, and Figure 4B for a diagram of the wiring structure of a specific layer of the adapter device according to the first embodiment of the present disclosure, in conjunction with Figures 2-3. In Figures 4A-4B, for simplicity and convenience in illustrating the features of the present disclosure, a first signal pair 26 and a second signal pair 28 are used for illustration. The subsequent first signal pairs 26 and second signal pairs 28 have identical structures and are configured in the same manner. Furthermore, in one embodiment, the term "substantially" used in the present disclosure may be interpreted as "essentially," with a deviation of, for example, but not limited to, 5-10%. For example, "two components being substantially parallel" may be considered "substantially parallel," but with a 5-10% angular difference, and so on.

In Figure 4A, adapter device 2 includes a first signal pair 26, and first signal pair 26 is located on surface layer 20-1. First endpoint 26A at one end of first signal pair 26 can extend to form one of the pair of first signal terminals 22A, and first endpoint 26A at the other end can extend to form another pair of first signal terminals 22B. Taking a differential pair as an example, the first trace segment of first signal pair 26 can include a first trace 26-1 and a second trace 26-2. First endpoints 26A at both ends of first trace 26-1 extend to form first terminals 22A-1 and first terminals 22B-1, respectively, and first endpoints 26A at both ends of second trace 26-2 extend to form second terminals 22A-2 and second terminals 22B-2, respectively. An electrically isolated region is defined between the first trace 26-1 and the second trace 26-2. This region can be enclosed or filled with a non-conductive material (such as, but not limited to, resin). The first trace 26-1 and the second trace 26-2 can be substantially parallel, with slight bends at the electrical connection terminals 22A-1, 22A-2, 22B-1, and 22B-2. However, this does not rule out the possibility of compensatory routing features such as serpentines. The first trace 26-1 and the second trace 26-2 are preferably arranged in a mirror image along a line connecting their midpoints.

On the other hand, in FIG4A , one pair of second signal terminals 24A is located on the same side of one pair of first signal terminals 22A and is arranged in parallel with one pair of first signal terminals 22A. Another pair of second signal terminals 24B is located on the same side of another pair of first signal terminals 22B and is arranged in parallel with another pair of first signal terminals 22B. Referring to FIG4B , the adapter 2 includes a second signal pair 28 and two pairs of conductive holes, and the second signal pair 28 is located in a specific layer 20-2 (illustrated as the second layer, but not limited thereto). The two pairs of conductive holes H2 are used to connect the surface layer 20-1 and the specific layer 20-2 of the adapter 2, and the two pairs of conductive holes include a first conductive hole H1 and a second conductive hole H2. First conductive via H1 and second conductive via H2 are located at second endpoints 28A at either end of second signal pair 28. Second endpoint 28A at one end is electrically connected to one end of a second trace segment located on a specific layer 20-2 via first conductive via H1. Second endpoint 28A at the other end is electrically connected to the other end of the second trace segment located on a specific layer 20-2 via second conductive via H2. Therefore, the two pairs of conductive vias primarily serve to electrically connect the two ends of the second trace segment to their corresponding second endpoints 28A.

The second end 28A at one end of the second signal pair 28 can extend to form one of the pair of second signal terminals 24A, and the second end 28A at the other end can extend to form another pair of second signal terminals 24B. Taking a differential pair as an example, the second trace segment of the second signal pair 28 may include a third trace 28-1 and a fourth trace 28-2. The second ends 28A at both ends of the third trace 28-1 extend to form third terminals 24A-1 and third terminals 24B-1, respectively, and the second ends 28A at both ends of the fourth trace 28-2 extend to form fourth terminals 24A-2 and fourth terminals 24B-2, respectively. Similar to the first signal pair 26, the third trace 28-1 and the fourth trace 28-2 include an electrically isolated region therebetween. The third trace 28-1 and the fourth trace 28-2 may be substantially parallel to each other, and the third trace 28-1 and the fourth trace 28-2 may be mirror-imaged along a line connecting their midpoints.

Refer to FIG. 4C for a schematic diagram of the cross-layer structure of the adapter device according to the first embodiment of the present disclosure, and refer to FIG. 2 to FIG. 4B for a schematic diagram of the cross-layer structure of the adapter device. The first signal pair 26 and the second signal pair 28 are substantially parallel to each other across the layers, and the straight line connecting the first signal terminals 22A and 22B is substantially parallel to the straight line connecting the second signal terminals 24A and 24B. In other words, from a bird's eye view or a bird's-eye view of the motherboard MB, the first signal pair 26 located on the surface layer 20-1 and the second signal pair 28 located on the surface layer 20-1 or on the specific layer 20-2 are substantially parallel to each other. Taking a differential pair as an example, the first trace 26-1, the second trace 26-2, the third trace 28-1, and the fourth trace 28-2 are substantially parallel to each other across the layers. Therefore, the straight lines connecting the first terminals 22A-1, 22B-1, the third terminals 24A-1, 24B-1, and the second terminals 22A-2, 22B-2 are substantially parallel to each other, and the straight lines connecting the second terminals 22A-2, 22B-2 and the fourth terminals 24A-2, 24B-2 are substantially parallel to each other. Because the second signal pair 28 is located on the specific layer 20-2, the surface layer 20-1 of the motherboard MB can reduce crosstalk between the first signal pair 26 and the second signal pair 28 by staggering the first signal pair 26 and the ground region GND, significantly improving crosstalk.

On the other hand, two pairs of ground terminals Pgnd and a ground region GND can also be provided in surface layer 20-1 of Figure 4A. The two pairs of ground terminals Pgnd are arranged on either side of the two pairs of second signal terminals 24A and 24B (i.e., the second signal terminals 24A and 24B formed by the two pairs of second terminals 28A). This isolates the second signal terminals 24A and 24B from the first signal terminals 22A and 22B via the ground terminals Pgnd. The ground region GND is electrically connected to the ground terminals Pgnd. The ground terminals Pgnd and the ground region GND surround the second signal terminals 24A and 24B, electrically isolating the ground terminals Pgnd, the ground region GND, and the second signal terminals 24A and 24B. Specifically, in surface layer 20-1 of Figure 4A , the area outside of first signal pair 26, first signal terminals 22A and 22B, second signal terminals 24A and 24B, and second endpoint 28A can be grounded (i.e., ground terminal Pgnd and ground region GND), with ground terminals Pgnd, ground region GND, and the aforementioned components electrically isolated. Alternatively, surface layer 20-1 may include only a pair of ground terminals Pgnd, arranged parallel to second signal terminal 24A or second signal terminal 24B, electrically connected to ground terminals Pgnd via ground region GND and surrounding second signal terminal 24A or second signal terminal 24B. The electrically isolated area can be a hollow space or filled with a non-conductive material (such as, but not limited to, resin). In this way, by arranging the first signal pair 26 and the second signal pair 28 in parallel across the layers, the crosstalk caused by the first signal pair 26 and the second signal pair 28 can be further reduced, thereby significantly improving the crosstalk.

It's worth noting that, in one embodiment, the ground region GND in FIG4B is configured similarly to FIG4A , differing in that the ground region GND is located within a specific layer 20-2, outside of and surrounding the second signal pair 28, achieving similar functionality as FIG4A . Referring to FIG4A and FIG4B , the areas surrounding the first signal terminals 22A, 22B and the second signal terminals 24A, 24B can be electrically isolated without copper plating, but this is not a limitation. Furthermore, please refer to FIG4D , which illustrates the ground layer layout structure of the adapter device according to the first embodiment of this disclosure, and to FIG2-4C for further reference. In Figure 4D , one layer of adapter device 2 can be configured as a ground layer 20-3 (the third layer is shown, but not limited to this). Ground layer 20-3 is located on a different plane from the specific layer 20-2 and the surface layer 20-1. Ground layer 20-3 can be provided with a large copper surface area to serve as a large grounding area GND. Furthermore, adapter device 2 does not include the first signal pair 26 and the second signal pair 28 in ground layer 20-3 to reduce signal interference, signal loss, and instability in adapter device 2.

On the other hand, referring to Figure 4E , a cross-sectional view of the motherboard MB along the direction from the first conductive via to the second conductive via according to the first embodiment of the present disclosure, also in conjunction with Figures 2-4D , is shown. Figure 4E primarily illustrates a cross-sectional view of the motherboard MB along the direction of the third terminal 24A-1, the first conductive via H1, the second conductive via H2, and the third terminal 24B-1. The first conductive via H1 and the second conductive via H2 are primarily holes (referred to as blind vias or vias) extending from the surface layer 20-1 to the specific layer 20-2 of the motherboard MB. These holes are filled with conductive material (such as, but not limited to, copper or tin) to provide electrical conductivity. Therefore, third terminal 24A-1 (extending from second terminal 28A) located outside surface layer 20-1 can be electrically connected to one end of third trace 28-1 on specific layer 20-2 via first conductive via H1. Third terminal 24B-1 (extending from second terminal 28A) can also be electrically connected to the other end of third trace 28-1 on specific layer 20-2 via second conductive via H2. The cross-sectional structure of fourth trace 28-2 is similar and will not be further described here. Furthermore, ground layer 20-3, due to its large copper cladding area, has a large grounding area GND.

In one embodiment, when the adapter 2 has only one surface layer 20-1 provided with the first signal terminals 22A, 22B, the second signal terminals 24A, 24B, the first signal pair 26 and the second terminal 28A, the ground layer 20-3 can be provided between the surface layer 20-1 and the specific layer 20-2, or the specific layer 20-2 can be provided between the surface layer 20-1 and the ground layer 20-3. On the contrary, when the two surface layers 20-1 and 20-n of the adapter 2 are respectively provided with the first signal terminals 22A and 22B, the second signal terminals 24A and 24B, the first signal pair 26 and the second end 28A, the ground layer 20-3 must isolate the first signal terminals 22A and 22B, the second signal terminals 24A and 24B, the first signal pair 26 and the second end 28A of the two surface layers 20-1 and 20-n, as well as the second signal pair 28 located on a different layer, so as to avoid mutual interference between the signals transmitted by the first signal pair 26 and the second signal pair 28. Therefore, when the first signal terminals 22A and 22B, the second signal terminals 24A and 24B, the first signal pair 26, and the second terminal 28A are respectively provided on the two surface layers 20-1 and 20-n of the adapter 2, a second ground layer 20-3 is required to isolate high-speed signals.

Specifically, when the first signal terminals 22A and 22B, the second signal terminals 24A and 24B, the first signal pair 26, and the second terminal 28A are respectively provided on the second surface layers 20-1 and 20-n of the adapter 2, the adapter 2 requires a board with six or more layers. For example, the circuit structure shown in Figures 4A to 4D is provided on a six-layer board. The first signal terminals 22A and 22B, the second signal terminals 24A and 24B, the first signal pair 26, and the second terminal 28A are respectively provided on the first layer 20-1 and the sixth layer 20-6 of the adapter 2 (see Figure 4A for details). Furthermore, the second layer 20-2 and the fifth layer 20-5 of the adapter 2 are designated layers and each includes the second signal pair 28. The second signal pair 28 is electrically connected to the second terminal 28A via the first conductive via H1 and the second conductive via H2 extending through the second surface layers 20-1 and 20-n (see Figure 4B ). Furthermore, the third layer 20-3 and the fourth layer 20-4 of the adapter 2 serve as ground layers (see Figure 4D ), isolating the high-speed signals transmitted on the surface layer 20-1, the second layer 20-2, the surface layer 20-6, and the fifth layer 20-5. It is worth noting that, in one embodiment, the numbering of all components in the signal pair is merely for structural convenience and has no bearing on the type or waveform of the signals being transmitted. For example, the signals transmitted by the first signal terminals 22A and 22B of the first layer 20-1 can be completely different from the signals transmitted by the second signal terminals 24A and 24B of the first layer 20-1. Furthermore, the signals transmitted by the first signal terminals 22A and 22B of the first layer 20-1 can also be completely different from the signals transmitted by the first signal terminals 22A and 22B of the sixth layer 20-6. Furthermore, referring to FIG4A , the signals transmitted by the first signal terminals 22A and 22B of the same layer can also be completely different. However, this is not a limitation; they can transmit the same signal depending on the timing requirements, and so on. This is not further elaborated here.

Please refer to Figure 5A for a comparison of crosstalk between a first signal pair and a conventional adapter device and the adapter device of the first embodiment of the present disclosure, and Figure 5B for a comparison of crosstalk between a second signal pair and a conventional adapter device, and refer to Figures 1-4E for details. Waveform I (solid line) in Figures 5A and 5B primarily represents the waveform curve when transmitting Rx and Tx signals using the routing structure of the conventional adapter device 2 of Figure 1 . Waveform II (dashed line) in Figures 5A and 5B primarily represents the waveform curve when transmitting Rx and Tx signals using the first signal pair 26 and second signal pair 28 of the adapter device 2 of the present disclosure. Furthermore, as can be clearly seen from Figures 5A and 5B, the wiring structure disclosed herein can reduce the crosstalk of the Rx signal by more than 10dB when the adapter 2 transmits both Rx and Tx signals simultaneously.

Please refer to Figure 6A for a diagram of the surface layer wiring structure of the adapter device according to the second embodiment of the present disclosure, and Figure 6B for a diagram of the specific layer wiring structure of the adapter device according to the second embodiment of the present disclosure, in conjunction with Figures 2-5B. The wiring structure of Figures 6A and 6B is similar to that of Figures 4A and 4B, differing in that the first signal pair 26 and the second signal pair 28 intersect across layers. Specifically, the first endpoints 26A at the ends of the first signal pair 26 in Figures 6A and 6B are misaligned, causing the positions of the first signal terminal 22A and the second signal terminal 24A to be swapped. As a result, the straight line connecting the first signal terminal 22A and the second signal terminal 24B is substantially parallel to the straight line connecting the second signal terminal 24A and the first signal terminal 22B. Furthermore, the first end 26A of the first signal pair 26 can also be extended to form the first signal terminals 22A and 22B, respectively, and the second end 28A of the second signal pair 28 can also be extended to form the second signal terminals 24A and 24B, respectively.

Therefore, the first signal terminal 22A is electrically connected to the first signal terminal 22B after the second turn of the first signal pair 26, and the second signal terminal 24A is similarly electrically connected to the second signal terminal 24B after the second turn of the second signal pair 28. Please refer to FIG6C for a schematic diagram of the cross-layer structure of the adapter device according to the second embodiment of the present disclosure, and refer to FIG2-6B in conjunction. Because the first signal pair 26 and the second signal pair 28 are respectively turned on different layers of the adapter device 2, the first signal pair 26 and the second signal pair 28 include two pairs of intersection points Pc that intersect across the layers, and the first signal pair 26 and the second signal pair 28 form a specific angle θ with the intersection point Pc as the center. The specific angle θ can range from 0 to 180 degrees, with 90 degrees being the preferred embodiment, but is not limited thereto. It can also be 45 degrees, 120 degrees, 135 degrees, etc., and can be adjusted to the optimal angle based on actual circumstances. This will not be elaborated upon here. In other words, from a bird's-eye view or a bird's-eye view of the motherboard MB, the first signal pair 26 located on the surface layer 20-1 intersects with the second signal pair 28 located on the surface layer 20-1 or on the specific layer 20-2 across layers. In one embodiment, since signals generate magnetic fields when propagating along traces (according to the right-hand rule), if the signal propagation paths happen to intersect perpendicularly, the magnetic fields can cancel each other out, reducing crosstalk caused by the signals. Therefore, the cross-layer intersection angle θ of the first signal pair 26 and the second signal pair 28 is substantially 90 degrees, which can achieve better crosstalk prevention and is a preferred implementation method.

Another difference between FIG. 6B and FIG. 4B is that, in the specific layer 20-2 (20-5), the area corresponding to the positions of the first signal terminals 22A, 22B and the second signal terminals 24A, 24B can be paved with copper to serve as a large-scale grounding area GND. Moreover, this feature of FIG. 6B and FIG. 4B can be selected and applied according to the actual needs of the adapter 2. Furthermore, the difference between Figure 6D and Figure 4D is that the areas of ground layer 20-3 (20-4) corresponding to first signal terminals 22A, 22B, second signal terminals 24A, 24B, and second terminal 28A are not copper-plated, but serve as electrically isolated areas. This feature of Figure 6D and Figure 4D can also be used depending on the actual requirements of adapter device 2. Therefore, adapter device 2 in Figure 6D also includes a large ground area GND layer 20-3 (20-4), and similarly reduces signal interference, signal loss, and instability in adapter device 2. On the other hand, the cross-sectional structure of the mainboard MB of the second embodiment along the direction from the first conductive via H1 to the second conductive via H2 can be inferred from FIG. 4E and FIG. 6A-6D , and the cross-sectional view is not specifically shown here.

It's worth noting that the crosstalk comparison diagrams of the adapter device 2 of the second embodiment can be inferred from Figures 5A, 5B, and Figures 6A-6D, and therefore are not specifically shown here. Furthermore, because the first signal pair 26 and the second signal pair 28 intersect across layers, providing improved crosstalk suppression, the adapter device 2 of Figures 6A-6D exhibits even better crosstalk reduction (i.e., a reduction of more than 10 dB) than the adapter device 2 of Figures 4A-4D when simultaneously transmitting Rx and Tx signals.

On the other hand, in one embodiment, the circuit structures and wiring arrangements not specifically described in Figures 6A-6D are similar to those in Figures 4A-4E or can be inferred from Figures 4A-4E and will not be further described here. In another embodiment, in which the adapter 2 is a six-layer board, the arrangements of Figures 4A-4E and 6A-6D can be integrated and applied together. For example, but not limited to, the first through third layers may be provided with the layers of Figures 4A-4E, and the sixth through fourth layers may be provided with the layers of Figures 6A-6D. Thus, the first signal pair 26 and the second signal pair 28 on the first layer 20-1 and the second layer 20-2 of the motherboard MB should have a first angle (for example, but not limited to, 0 degrees), and the first signal pair 26 and the second signal pair 28 on the sixth layer 20-6 and the fifth layer 20-5 should have a second angle (for example, but not limited to, 90 degrees across the layers). Furthermore, the first and second angles are different, allowing the adapter device 2 of the present disclosure to selectively configure its transmission location based on signal accuracy requirements (for example, but not limited to, signals requiring high accuracy can be routed through layers 6 through 4), and so on, and no further explanation is given here.

Furthermore, because the intersecting angle θ between the first signal pair 26 and the second signal pair 28 provides enhanced crosstalk suppression, the ground layer in Figures 6A-6D allows for more flexible placement. Specifically, when the intersecting angle θ between the first signal pair 26 and the second signal pair 28 is similar to that shown in Figures 4A-4E (i.e., when the intersecting angle θ is 0 degrees or 180 degrees), the crosstalk suppression effect is minimal, making it preferable to place the specific layer between the ground layer and the surface layer. Conversely, when the intersecting angle θ between the first signal pair 26 and the second signal pair 28 is similar to that shown in Figures 6A-6D (i.e., when the intersecting angle θ is not 0 degrees or 180 degrees), the crosstalk suppression effect is greater, making it preferable to place the ground layer between the surface layer and the specific layer. Therefore, if the first angle and the second angle are different, and assuming that the layers 1 to 3 are provided with the layers shown in Figures 6A to 6D, and the layers 6 to 4 are provided with the layers shown in Figures 4A to 4E, then the structure of the layers 1 to 3 is such that the ground layer 20-2 is provided between the surface layer 20-1 and the special layer 20-3, and the structure of the layers 6 to 4 is such that the special layer 20-5 is provided between the ground layer 20-4 and the surface layer 20-6, and so on, and no further explanation is given here.

However, the above descriptions and drawings are merely detailed descriptions of preferred embodiments of the present disclosure. The features of the present disclosure are not limited thereto, and are not intended to limit the present disclosure. The entire scope of the present disclosure shall be subject to the following patent application. All embodiments that conform to the spirit of the present patent application and similar variations thereof shall be included within the scope of the present disclosure. Any variations or modifications that can be easily conceived by those skilled in the art within the scope of the present disclosure are also covered by the following patent application.

22A, 22B: First signal terminals

22A-1, 22B-1: First terminal

22A-2, 22B-2: Second terminal

24A, 24B: Second signal terminals

24A-1, 24B-1: Third terminal

24A-2, 24B-2: Fourth terminal

26: First signal pair

26A: First endpoint

26-1: First Route

26-2: Second Route

28A: Second endpoint

H1: First conductive hole

H2: Second conductive hole

GND: Ground area

Pgnd: ground terminal

Claims (10)

A switching device for transmitting high-speed signals comprises: a motherboard comprising a surface layer and a specific layer, wherein the specific layer and the surface layer are located on different planes; a first signal pair comprising a pair of first trace segments and a plurality of first endpoints, wherein the first endpoints are located at the ends of each of the pair of first trace segments, respectively, and the pair of first trace segments and the first endpoints are located on the surface layer; and a second signal pair comprising a pair of second trace segments and a plurality of second endpoints, wherein the second endpoints are located at the ends of each of the pair of second trace segments, respectively, and the second endpoints are located on the surface layer, and the pair of second trace segments are located on the specific layer. The adapter device of claim 1, wherein the mainboard includes: A ground layer located on a different plane from the specific layer and the surface layer, and the ground layer is free of the first signal pair and the second signal pair. The switching device as described in claim 2, wherein the angle at which the first signal pair and the second signal pair intersect across layers is 0-180 degrees. The switching device as described in claim 2 or 3, wherein when the angle at which the first signal pair and the second signal pair intersect across layers is 0 degrees or 180 degrees, the specific layer is disposed between the ground layer and the surface layer. The switching device as described in claim 2 or 3, wherein the ground layer is arranged between the surface layer and the specific layer. The adapter device as described in claim 2 or 3, wherein the main board is a six-layer board, the first layer and the sixth layer of the main board are two surface layers, and the first signal pair and the second endpoints are respectively provided, the third layer and the fifth layer of the main board are two specific layers, and the pair of second trace segments are respectively provided, the second layer and the fourth layer of the main board are the ground layers, respectively, wherein the first signal pair of the first layer and the second signal pair of the third layer have a first angle therebetween, and the first signal pair of the sixth layer and the second signal pair of the fifth layer have a second angle therebetween, and the first angle is different from the second angle. A switching device as described in claim 1, wherein the pair of first end points of at least one end of the pair of first trace segments extend to form a pair of first signal terminals, the pair of second end points of the pair of second signal segments on the same side as the pair of first signal terminals extend to form a pair of second signal terminals, and the pair of first signal terminals and the pair of second signal terminals are used for plugging in an external device. The adapter device as described in claim 1, wherein the mainboard further comprises: Two pairs of conductive vias extending through the surface layer and the specific layer, for electrically connecting the two ends of the pair of second trace segments to the corresponding second endpoints. The adapter device as described in claim 1, wherein the mainboard further comprises: a pair of ground terminals disposed on the surface and arranged in parallel on either side of the second endpoints of at least one end of the pair of second trace segments; and a ground region disposed on the surface and electrically connected to the pair of ground terminals; wherein, the pair of ground terminals and the ground region surround the second endpoints. The adapter device of claim 1, wherein the motherboard further comprises: A ground region disposed on the specific layer and surrounding the pair of second trace segments.