TWM658442U - Power stage circuit - Google Patents

Abstract

A power stage circuit includes a switch circuit, a driving circuit and a current monitor circuit. The driving circuit drives the switch circuit according to a control signal to generate an output current signal. The current monitor circuit includes a current sensing circuit, a virtual current signal generation circuit and a signal combination circuit. The current sensing circuit senses the output current signal to generate a low-side current signal. The virtual current signal generation circuit generates a low-side voltage signal according to the low-side current signal, generates a digital signal, adjusts the digital signal according to a comparison result between the low-side voltage signal and a virtual voltage signal, adjusts the virtual voltage signal according to the digital signal so that the virtual voltage signal approaches the low-side voltage signal, and generates a virtual current signal according to the virtual voltage signal. The signal combination circuit generates a current monitor signal according to the low-side current signal and the virtual current signal.

Description

Power stage circuit

The present disclosure relates to a power stage circuit, and more particularly to a power stage circuit suitable for use in a power converter circuit.

In the related applications of smart power stage modules, the smart power stage modules are often required to provide a current monitoring signal proportional to the inductor current. Some related technologies will add various electronic components to the smart power stage modules to meet the above requirements. However, the above additional electronic components cause the cost of these related technologies to increase significantly. Therefore, it is necessary to propose a new circuit to solve the above problem.

One aspect of the present disclosure is a power stage circuit. The power stage circuit includes a switching circuit, a driving circuit, and a current monitoring circuit. The switching circuit is coupled to an output end of the power stage circuit to receive an input voltage signal, and includes a high-side switch and a low-side switch, wherein the output end is coupled to a load end via an inductor element. The driving circuit is coupled to the switching circuit and is used to drive the switching circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element. The current monitoring circuit includes an inductive current sensing circuit, a virtual current signal generating circuit, and a signal combining circuit. The current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal. The virtual current signal generating circuit is coupled to the current flow sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, to generate a digital signal, to adjust the digital signal according to a comparison result between the low-side voltage signal and a virtual voltage signal in a first mode or a second mode, to adjust the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and to generate a virtual current signal according to the virtual voltage signal. The signal combining circuit is coupled to the current flow sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the first mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude, and the first adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases. In the second mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude, and the second adjustment amplitude is a constant value.

Another aspect of the present disclosure is a power stage circuit, wherein the power stage circuit includes a switching circuit, a driving circuit, and a current monitoring circuit. The switching circuit is coupled to an output end of the power stage circuit to receive an input voltage signal, and includes a high-side switch and a low-side switch, wherein the output end is coupled to a load end via an inductor element. The driving circuit is coupled to the switching circuit and is used to drive the switching circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element. The current monitoring circuit includes an inductive current sensing circuit, a virtual current signal generating circuit, and a signal combining circuit. The current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal. The virtual current signal generating circuit is coupled to the current flow sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, to generate a digital signal, to adjust the digital signal according to a comparison result between the low-side voltage signal and a virtual voltage signal, to adjust the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and to generate a virtual current signal according to the virtual voltage signal. The signal combining circuit is coupled to the current flow sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In a linear mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a first time. In the linear mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the first adjustment amplitude is a constant value.

In summary, by generating a virtual current signal in proportion to the output current signal through the virtual current signal generating circuit, the power stage circuit of the present disclosure can complete the current flow measurement during the conduction period of the low-side switch, and can combine the virtual current signal with the low-side current signal obtained by the current flow measurement to generate a current monitoring signal. In addition, the current monitoring circuit of the present disclosure significantly saves the number of components, and can digitally adjust the virtual voltage signal to correct the virtual current signal and ensure the stability of the virtual current signal. Therefore, the power stage circuit and current monitoring circuit disclosed in the present invention have the advantages of low cost, suitability for low duty cycle applications, and generation of a current monitoring signal with high stability and high accuracy.

The following is a detailed description of the embodiments with the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure reassembled by the components to produce a device with equal functions is within the scope of the present disclosure.

The terms used throughout the specification and application generally have the ordinary meanings of each term used in the art, in the context of this disclosure and in the specific context, unless otherwise specified.

As used herein, “coupled” or “connected” may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more elements operating or moving with each other.

Please refer to FIG. 1, which is a circuit block diagram of a power stage circuit 10 and a controller 20 according to some embodiments of the present disclosure. In some embodiments, the power stage circuit 10 and the controller 20 can form a power converter circuit such as a DC/DC converter. The power stage circuit 10 can be coupled to a load terminal SL via an inductor element L, and the load terminal SL can be electrically coupled to a load device such as a central processing unit (CPU) (not shown in the figure). In this way, the power converter circuit composed of the power stage circuit 10 and the controller 20 can supply power to the load device.

In some embodiments, as shown in FIG. 1, the power stage circuit 10 includes a switch circuit 11, a drive circuit 13, and a current monitoring circuit 15. In addition, the switch circuit 11 includes a high-side switch Q1 and a low-side switch Q2. The high-side switch Q1 is coupled to an input voltage signal VIN and an output terminal SW of the power stage circuit 10, and the low-side switch Q2 is coupled to the output terminal SW and a ground voltage GND. As can be seen from the above description, in some embodiments, the switch circuit 11 is coupled to the output terminal SW and is used to receive the input voltage signal VIN. In addition, the output terminal SW is coupled to the load terminal SL via the inductor element L. Specifically, the high-side switch Q1 and the low-side switch Q2 can each be implemented by a transistor (eg, a metal oxide semiconductor transistor, etc.), but the present disclosure is not limited thereto.

In some embodiments, as shown in FIG. 1 , the driver circuit 13 is coupled to the high-side switch Q1, the low-side switch Q2, and the controller 20, and is used to receive a control signal PWM output by the controller 20, and to generate a high-side drive signal GH and a low-side drive signal GL to the high-side switch Q1 and the low-side switch Q2 respectively according to the control signal PWM. Specifically, the control signal PWM can be a periodic signal such as a pulse width modulation (PWM) signal, and the driver circuit 13 can be implemented by a gate driver. That is, the high-side driving signal GH and the low-side driving signal GL may be output to the gate terminal of the transistor in the high-side switch Q1 and the gate terminal of the transistor in the low-side switch Q2, respectively.

Please refer to FIG. 2, which is a waveform diagram of some signals related to the power stage circuit 10. In some embodiments, as shown in FIG. 2, the high-side drive signal GH and the low-side drive signal GL are also periodic signals. The high-side drive signal GH and the control signal PWM are substantially in phase with each other. For example, when the high-side drive signal GH is at an enable level (such as a high voltage level shown in FIG. 2), the control signal PWM may also be at an enable level. The high-side drive signal GH and the low-side drive signal GL are substantially in opposite phases with each other. For example, when the high-side drive signal GH is at a disable level (such as a low voltage level shown in FIG. 2), the low-side drive signal GL is at an enable level. Specifically, the enable level may be a voltage level that can turn on the high-side switch Q1 or the low-side switch Q2, and the disable level may be a voltage level that can turn off the high-side switch Q1 or the low-side switch Q2. In this configuration, the enable-level high-side drive signal GH corresponds to the on-period HON of the high-side switch Q1 (i.e., the off-period of the low-side switch Q2), and the enable-level low-side drive signal GL corresponds to the on-period LON of the low-side switch Q2 (i.e., the off-period of the high-side switch Q1).

From the above description, it can be seen that through the high-side drive signal GH and the low-side drive signal GL in Figure 2, the high-side switch Q1 and the low-side switch Q2 in Figure 1 will be turned on alternately, so that a square wave voltage signal (not shown in the figure) is generated at the output terminal SW. It should be understood that the voltage level of this square wave voltage signal will switch between the voltage level of the input voltage signal VIN and the voltage level of the ground voltage GND.

In the embodiment of FIG. 1 , a capacitor element COUT is coupled between the load terminal SL and the ground voltage GND to form a circuit (e.g., a low-pass filter circuit) with the inductor element L. This circuit is used to process the aforementioned square wave voltage signal to generate an output voltage signal VOUT at the load terminal SL. It should be understood that the aforementioned power converter circuit can supply power to the load device through the output voltage signal VOUT.

As shown in FIG. 1 , when the two ends of the inductor L generate the aforementioned square wave voltage signal and the output voltage signal VOUT respectively, an output current signal IL is generated and flows through the inductor L. In some embodiments, as shown in FIG. 2 , the output current signal IL is a triangle wave or ramp signal.

As can be seen from the above description, in some embodiments, the driving circuit 13 is coupled to the switching circuit 11 and is used to drive the switching circuit 11 according to the control signal PWM to generate an output voltage signal VOUT at the load end SL and generate an output current signal IL through the inductor element L.

In addition, in the embodiment of FIG. 1 , the controller 20 is used to receive and compare an output voltage signal VOUT and a reference voltage signal VREF, and to adjust the duty ratio of the control signal PWM according to the comparison result between the output voltage signal VOUT and the reference voltage signal VREF, thereby changing the switching frequency of the high-side switch Q1 and the switching frequency of the low-side switch Q2.

In some embodiments, the current monitoring circuit 15 includes a current flow detection circuit 151, a virtual current signal generating circuit 153, and a signal combining circuit 155. As shown in FIG. 1, the current flow detection circuit 151 is coupled to the switch circuit 11, for example, between the output terminal SW and the low-side switch Q2. The virtual current signal generating circuit 153 is coupled to the current flow detection circuit 151. The signal combining circuit 155 is coupled to the current flow detection circuit 151 and the virtual current signal generating circuit 153.

In some embodiments, the current flow sensing circuit 151 is used to sense the output current signal IL (i.e., sense the current signal flowing through the low-side switch Q2) during each conduction period LON of the low-side switch Q2 to generate a low-side current signal ILS. In some further embodiments, as shown in FIG. 2, the current flow sensing circuit 151 does not sense the output current signal IL during a first period P1 in each conduction period LON of the low-side switch Q2, and senses the output current signal IL during a second period P2 in each conduction period LON of the low-side switch Q2, thereby generating the low-side current signal ILS. As can be seen from the above description, the low-side current signal ILS is substantially the same as the output current signal IL during each second period P2.

In some embodiments, the virtual current signal generating circuit 153 is used to receive the low-side current signal ILS, to generate a low-side voltage signal VLS (not shown in FIGS. 1 and 2 ) based on the low-side current signal ILS, to adjust the virtual voltage signal VVR based on a comparison result of the low-side voltage signal VLS with a virtual voltage signal VVR (not shown in FIGS. 1 and 2 ) to make the virtual voltage signal VVR close to the low-side voltage signal VLS, and to generate a virtual current signal IVR based on the virtual voltage signal VVR. By adjusting the virtual voltage signal VVR, the virtual current signal IVR can be corrected so that the virtual current signal IVR is substantially close to or equal to the output current signal IL. The generation of the low-side voltage signal VLS, the virtual voltage signal VVR, and the virtual current signal IVR will be further described in detail later with reference to Figures 3 to 6. It is worth noting that, as shown in Figure 2, the virtual current signal IVR generated by the virtual voltage signal VVR close to the low-side voltage signal VLS is substantially the same as the output current signal IL.

In some embodiments, the signal combining circuit 155 is used to receive the low-side current signal ILS and the virtual current signal IVR, and to generate a current monitoring signal IMON according to the low-side current signal ILS and the virtual current signal IVR. For example, as shown in FIG. 2 , the signal combining circuit 155 combines the virtual current signal IVR corresponding to the first period P1 of each conduction period HON of the high-side switch Q1 and each conduction period LON of the low-side switch Q2 with the low-side current signal ILS corresponding to the second period P2 of each conduction period LON of the low-side switch Q2 to generate the current monitoring signal IMON.

In the above embodiment, there are two main reasons why the current flow detection circuit 151 performs current flow detection only during the second period P2 of each conduction period LON of the low-side switch Q2. The first reason is that the conduction period HON of the high-side switch Q1 is too short, so that in some practical applications (e.g., low duty cycle applications), it is not possible to provide the current flow detection circuit 151 with sufficient time to complete the current flow detection. Compared with the conduction period HON of the high-side switch Q1, the conduction period LON of the low-side switch Q2 can provide the current flow detection circuit 151 with sufficient time to complete the current flow detection. The second reason is that the output current signal IL may not be stable during the first period P1 of each conduction period LON of the low-side switch Q2, and may become stable during the second period P2 of each conduction period LON of the low-side switch Q2. By allowing the current sensing circuit 151 to sense the stable output current signal IL during the second period P2, the reliability of the low-side current signal ILS can be further ensured. It is worth noting that the accuracy of the virtual current signal IVR and the current monitoring signal IMON generated based on the low-side current signal ILS can also be ensured.

Next, the circuit structure of the virtual current signal generating circuit 153 is described with reference to FIG. 3. Please refer to FIG. 3, which is a circuit diagram of the virtual current signal generating circuit 153 according to some embodiments of the present disclosure. In some embodiments, the virtual current signal generating circuit 153 includes a current-to-voltage conversion circuit 31, a comparison circuit 33, a digital circuit 35, and a signal conversion circuit 37.

In some embodiments, the current-to-voltage conversion circuit 31 is coupled to the current sensing circuit 151 in FIG. 1 to receive the low-side current signal ILS. The current-to-voltage conversion circuit 31 is also used to convert the low-side current signal ILS into a low-side voltage signal VLS. As shown in FIG. 3, the current-to-voltage conversion circuit 31 can be implemented by a resistor element R1. Specifically, one end of the resistor element R1 can be coupled to the ground voltage GND, and the other end of the resistor element R1 can be used for the low-side current signal ILS to flow into. In other words, the low-side current signal ILS can flow through the resistor element R1 and flow into the ground voltage GND, thereby generating a low-side voltage signal VLS at the other end of the resistor element R1.

In some embodiments, the comparison circuit 33 is coupled to the current-to-voltage circuit 31, the digital circuit 35, and the signal conversion circuit 37, and is used to compare the low-side voltage signal VLS with the virtual voltage signal VVR. Specifically, a first input terminal (e.g., non-inverting input terminal) of the comparison circuit 33 is coupled to the other end of the aforementioned resistor element R1 to receive the low-side voltage signal VLS. A second input terminal (e.g., inverting input terminal) of the comparison circuit 33 is coupled to the signal conversion circuit 37 to receive the virtual voltage signal VVR. An output terminal of the comparison circuit 33 is coupled to the digital circuit 35 to provide the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR to the digital circuit 35 .

In some embodiments, the digital circuit 35 is coupled to the comparison circuit 33 and the signal conversion circuit 37, and is used to generate a digital signal DOUT to the signal conversion circuit 37. As shown in FIG. 3, the digital signal DOUT can be an N-bit signal. In some further embodiments, the digital circuit 35 includes a clock control circuit 351 and a digital control circuit 353, and the digital control circuit 353 includes a sampling and holding circuit 531 and a logic control circuit 533. The clock control circuit 351 is coupled to the sampling and holding circuit 531 and the logic control circuit 533. The sampling and holding circuit 531 is also coupled to the comparison circuit 33 and the logic control circuit 533, and the logic control circuit 533 is also coupled to the signal conversion circuit 37.

Following the description of the above embodiment, the clock control circuit 351 is used to receive the control signal PWM, a power-on reset voltage signal POR and a reload signal RL, and to generate a clock signal CLK, a latch signal LATCH, a binary mode signal MBIN and a linear mode signal MLIN according to the control signal PWM, the power-on reset voltage signal POR and the reload signal RL. In addition, the digital control circuit 353 is used to receive the clock signal CLK, the latch signal LATCH, the binary mode signal MBIN, the linear mode signal MLIN and the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR to adjust and output the digital signal DOUT, which will be described in detail with reference to FIGS. 4 to 6 later.

In some embodiments, the signal conversion circuit 37 is coupled to the digital circuit 35 and the comparison circuit 33 to receive the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT, and to generate a virtual voltage signal VVR according to the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT to generate a virtual current signal IVR.

In some further embodiments, as shown in FIG. 3 , the signal conversion circuit 37 includes a virtual voltage signal generating circuit 371, a voltage-to-current circuit 373, and a capacitor element C37. The virtual voltage signal generating circuit 371 includes a first digital-to-analog conversion circuit DAC1, a second digital-to-analog conversion circuit DAC2, a first switch S1, and a second switch S2. The first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can be coupled to an output terminal N1 of the virtual voltage signal generating circuit 371 through the first switch S1 and the second switch S2, respectively. The virtual voltage signal generating circuit 371 is coupled to the second input terminal of the comparison circuit 33, an input terminal of the voltage-to-current circuit 373, and one terminal of the capacitor C37 via the output terminal N1. The other terminal of the capacitor C37 is coupled to the ground voltage GND, and an output terminal of the voltage-to-current circuit 373 is coupled to the signal combining circuit 155 in FIG. 1. However, the present disclosure is not limited thereto. For example, in some embodiments, the capacitor C37 may be included in the virtual voltage signal generating circuit 371.

Following the description of the above embodiment, the first digital-to-analog conversion circuit DAC1 is used to receive the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT, and to perform voltage-to-current conversion on the input voltage signal VIN minus the output voltage signal VOUT according to the digital signal DOUT to generate a first current signal SA. Specifically, the first current signal SA can be the input voltage signal VIN minus the output voltage signal VOUT multiplied by a first parameter. The second digital-to-analog conversion circuit DAC2 is used to receive the digital signal DOUT and the output voltage signal VOUT, and to perform voltage-to-current conversion on the negative number of the output voltage signal VOUT according to the digital signal DOUT to generate a second current signal SB. Specifically, the second current signal SB may be a negative of the output voltage signal VOUT multiplied by a second parameter.

In the above-mentioned embodiments, the first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can each be implemented by a transconductance amplifier, wherein the digital signal DOUT is used to adjust the gain of the transconductance amplifier to control the first parameter and the second parameter. However, the present disclosure is not limited thereto. In some embodiments, the first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can each be implemented using a circuit composed of a current source, a resistor and a buffer, wherein the digital signal DOUT is used to adjust the resistance value of the resistor to control the first parameter and the second parameter.

Please refer to FIGS. 2 and 3 together. In some embodiments, the first switch S1 is switched to the on state when the high-side driving signal GH is at the enable level, and the second switch S2 is switched to the on state when the low-side driving signal GL is at the enable level. In other words, the first switch S1 and the second switch S2 are switched to the on state alternately. Under this configuration, the capacitor element C37 can be charged by the first current signal SA generated by the first digital-to-analog conversion circuit DAC1 when the first switch S1 is at the on state, and can be charged by the second current signal SB generated by the second digital-to-analog conversion circuit DAC2 when the second switch S2 is at the on state, thereby generating a virtual voltage signal VVR at the output terminal N1.

As can be seen from the above description, in some embodiments, the virtual voltage signal generating circuit 371 is used to convert the input voltage signal VIN minus the output voltage signal VOUT into the first current signal SA according to the digital signal DOUT during each conduction period HON of the high-side switch Q1, and is used to convert the negative of the output voltage signal VOUT into the second current signal SB according to the digital signal DOUT during each conduction period LON of the low-side switch Q2 to generate the virtual voltage signal VVR.

In some embodiments, the voltage-to-current circuit 373 is used to convert the virtual voltage signal VVR into a virtual current signal IVR. For example, the voltage-to-current circuit 373 can be implemented by a resistor and a current mirror. The resistor can be coupled between the output terminal N1 and the ground voltage GND to generate a current signal flowing through the resistor. In addition, the current mirror can generate the virtual current signal IVR by replicating the current signal.

Please refer to FIG. 4, which is a flow chart of a method 400 for adjusting a digital signal DOUT that can be executed by a digital circuit 35 according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 4, the adjustment method 400 includes a plurality of operations S401-S410. The adjustment method 400 will be described in detail with reference to FIGS. 5 and 6. FIG. 5 is a timing diagram of some signals related to a virtual current signal generating circuit 153 in a binary mode according to some embodiments of the present disclosure. FIG. 6 is a timing diagram of some signals related to a virtual current signal generating circuit 153 in a linear mode according to some embodiments of the present disclosure.

In some embodiments, the digital circuit 35 performs the adjustment method 400 after the power stage circuit 10 is turned on. Specifically, after the power stage circuit 10 is turned on, the power-on reset voltage signal POR switches from a disable level to an enable level to trigger the clock control circuit 351 to correspondingly generate the clock signal CLK, the latch signal LATCH, the binary mode signal MBIN, and the linear mode signal MLIN.

For example, as shown in FIG. 4, the clock control circuit 351 can switch the binary mode signal MBIN and the linear mode signal MLIN to an enable level and a disable level, respectively. The clock control circuit 351 can invert the control signal PWM and perform a delay operation on the inverted control signal PWM to generate the clock signal CLK as shown in FIG. 5. Furthermore, the clock control circuit 351 can perform a second delay operation on the inverted control signal PWM to generate the latch signal LATCH as shown in FIG. 5. Accordingly, operation S401 is performed.

In operation S401, the digital circuit 35 switches between two different modes according to the binary mode signal MBIN and the linear mode signal MLIN, that is, operates in the binary mode or the linear mode. For example, as shown in FIG. 5, the digital control circuit 353 in the digital circuit 35 controls the virtual current signal generating circuit 153 to operate in the binary mode according to the binary mode signal MBIN of the enable level and the linear mode signal MLIN of the disable level. In some embodiments, the binary mode is referred to as the first mode, the linear mode is referred to as the second mode, and the first mode is different from the second mode. The binary mode signal MBIN is referred to as the first mode signal, and the linear mode signal MLIN is referred to as the second mode signal.

In some embodiments, the comparison circuit 33 in FIG. 3 compares the low-side voltage signal VLS with the virtual voltage signal VVR N times in binary mode. In the embodiment of FIG. 5 , the digital signal DOUT is an 8-bit signal, that is, N is 8. In other words, the digital signal DOUT includes 8 bits DOUT[0]~DOUT[7]. In addition, the multiple time points T1~T8 in FIG. 5 respectively represent the execution time of 8 comparisons. Before the N comparisons are performed, operation S402 is performed.

In operation S402, the logic control circuit 533 sets each of the bits of the digital signal DOUT to "0". In an embodiment where the digital signal DOUT is an 8-bit signal, the digital signal DOUT will be set to "00000000".

In operation S403, before performing the i-th comparison, the logic control circuit 533 sets the bit value of the bit corresponding to the i-th comparison among the multiple bits of the digital signal DOUT to "1" to generate a virtual voltage signal VVR for the i-th comparison. It should be understood that, corresponding to the embodiment of FIG. 5, i can be any integer from 1 to 8.

For example, before the first comparison (corresponding to a time point T1 in FIG. 5 ), the bit value of the first bit DOUT[7] (e.g., the highest bit) of the digital signal DOUT is set or switched to “1”. At this time, the digital signal DOUT is “10000000”. As described in the embodiment of FIG. 3 , the virtual voltage signal generating circuit 371 then performs voltage-to-current conversion based on the digital signal DOUT, the input voltage signal VIN, and the output voltage signal VOUT to output the virtual voltage signal VVR for the first comparison.

In operation S404, the digital control circuit 353 obtains the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR. In some embodiments, as shown in FIG. 3, the sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP1 of the clock signal CLK (corresponding to the time point T1) to sample and hold the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR, and outputs a comparison signal CMP representing the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR to the logic control circuit 533. As shown in FIG5 , the disable level comparison signal CMP indicates that the voltage level of the virtual voltage signal VVR is greater than the voltage level of the low-side voltage signal VLS. In this case, operation S406 is performed.

In operation S406, the logic control circuit 533 determines that the bit value of the first bit of the digital signal DOUT (i.e., the bit corresponding to the first comparison among the plurality of bits) is "0". In some embodiments, the logic control circuit 533 is triggered by the rising edge of a pulse LP1 located after the time point T1 in the latch signal LATCH and sets the bit value of the first bit of the digital signal DOUT to "0" according to the comparison signal CMP of the disable level. Accordingly, operation S407 is performed.

In operation S407, the digital circuit 35 determines whether N judgments have been made. For example, the digital circuit 35 can count the number of pulses generated by the control signal PWM, the clock signal CLK, or the latch signal LATCH through a pulse counter (not shown) inside the clock control circuit 351, and can determine whether N judgments have been made according to the number of pulses generated. After the first comparison, the number of generated counts by the clock control circuit 351 should be 1 (that is, still not 8), so operations S403 and S404 are executed again.

As shown in FIG. 5 , before the second comparison, the bit value of the second bit DOUT[6] in the digital signal DOUT is set or switched to “1”. At this time, the digital signal DOUT is “01000000”. It should be understood that the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the second comparison. The sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP2 of the clock signal CLK (corresponding to the time point T2) to output the comparison signal CMP of the disable level to the logic control circuit 533. In this case, operation S406 is executed again. Similarly, the logic control circuit 533 determines that the bit value of the second bit in the digital signal DOUT (i.e., the bit corresponding to the second comparison among the multiple bits) is "0", and is triggered by the rising edge of a pulse LP2 located after the time point T2 in the latch signal LATCH, and sets the bit value of the second bit in the digital signal DOUT to "0" according to the comparison signal CMP of the disable level. Accordingly, operation S407 is executed again. It should be understood that since the generated number counted by the clock control circuit 351 after the second comparison should be 2 (i.e., still not 8), operations S403 and S404 are executed again.

As shown in FIG. 5 , before the third comparison, the bit value of the third bit DOUT[5] in the digital signal DOUT is set or switched to “1”. At this time, the digital signal DOUT is “00100000”. It should be understood that the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the third comparison. The sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP3 of the clock signal CLK (corresponding to the time point T3) to output the comparison signal CMP of the enable level to the logic control circuit 533. As shown in FIG5 , the enable level comparison signal CMP indicates that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS. In this case, operation S405 is performed.

In operation S405, the logic control circuit 533 determines that the bit value of the third bit of the digital signal DOUT (i.e., the bit corresponding to the third comparison among the multiple bits) is "1", and is triggered by the rising edge of a pulse LP3 located after the time point T3 in the latch signal LATCH, and sets the bit value of the third bit of the digital signal DOUT to "1" according to the comparison signal CMP of the enable level. Accordingly, operation S407 is executed again. Similarly, after the third comparison, the generated number counted by the clock control circuit 351 should be 3 (i.e., still not 8), so operations S403 and S404 are executed again. Note that the digital signal DOUT is adjusted from "00000000" set in the second comparison to "00100000". Therefore, the adjustment amplitude is "00100000", which is "32" in decimal.

The 4th to 8th comparisons can be analogized based on the description of the 1st to 3rd comparisons, so they are only briefly described here. In the 4th comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated based on the digital signal DOUT set to "00110000") is less than the voltage level of the low-side voltage signal VLS at time point T4 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the fourth bit DOUT[4] in the digital signal DOUT to "1" (corresponding to operation S405). Note that the digital signal DOUT is adjusted from "00100000" set in the 3rd comparison to "00110000". Therefore, the adjustment amplitude is "00010000", which is "16" in decimal.

In the fifth comparison, the digital control circuit 353 obtains at time point T5 that the voltage level of the virtual voltage signal VVR (generated based on the digital signal DOUT set to "00111000") is greater than the voltage level of the low-side voltage signal VLS (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the fifth bit DOUT[3] in the digital signal DOUT to "0" (corresponding to operation S406).

In the sixth comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated according to the digital signal DOUT set to "00110100") is less than the voltage level of the low-side voltage signal VLS at time point T6 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the sixth bit DOUT[2] in the digital signal DOUT to "1" (corresponding to operation S405). Note that the digital signal DOUT is adjusted from "00110000" set in the fifth comparison to "00110100". Therefore, it can be seen that the adjustment amplitude is "00000100", which is "4" in decimal.

In the 7th comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated according to the digital signal DOUT set to "00110110") is greater than the voltage level of the low-side voltage signal VLS at time point T7 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the seventh bit DOUT[1] in the digital signal DOUT to "0" (corresponding to operation S406).

In the 8th comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated according to the digital signal DOUT set to "00110101") is less than the voltage level of the low-side voltage signal VLS at time point T8 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the eighth bit DOUT[0] in the digital signal DOUT to "1" (corresponding to operation S405). Therefore, the digital signal DOUT is finally set to "00110101". It is noted that the digital signal DOUT is adjusted from "00110100" set in the 7th comparison to "00110101". Therefore, the adjustment amplitude is "00000001", which is "1" in decimal.

From the above, we can know that in binary mode, the digital signal DOUT is adjusted 4 times in total, and the adjustment amplitude of the digital signal DOUT is a non-constant value. For example, as the number of times the digital signal DOUT is adjusted increases, the adjustment amplitude changes from "32" to "16", from "16" to "4", and then from "4" to "1", that is, the adjustment amplitude gradually decreases.

According to the embodiment of the present case, the adjustment amplitude used by the digital circuit 35 to adjust or approximate the value of the digital signal DOUT in the binary mode gradually changes as the number of times the digital signal DOUT is adjusted increases. Specifically, in the binary mode, the adjustment amplitude used by the digital circuit 35 to adjust or approximate the digital signal DOUT can gradually decrease as the number of times the digital signal DOUT is adjusted increases.

In addition, after the 8th comparison, the digital circuit 35 determines that N comparisons have been performed (corresponding to operation S407). Therefore, as shown in FIG. 4, the clock control circuit 351 can switch the binary mode signal MBIN and the linear mode signal MLIN to the disable level and the enable level respectively, and operation S401 is executed again.

In some embodiments of operation S401, as shown in FIG. 6 , the digital control circuit 353 in the digital circuit 35 controls the virtual current signal generating circuit 153 to operate in the linear mode according to the binary mode signal MBIN of the disable level and the linear mode signal MLIN of the enable level. In some embodiments, when the DC/DC converter of the present case is started, when the DC/DC converter of the present case wants to change the output voltage signal VOUT, or when the power stage circuit 10 is one of the phase circuits in the multi-phase DC voltage converter and is started, the digital control circuit 353 controls the virtual current signal generating circuit 153 to enter the linear mode and operate in the linear mode.

Following the above description, in some embodiments, the clock control circuit 351 can count the number of pulses generated by the control signal PWM through another internal pulse counter (not shown), and judge whether the number of pulses generated reaches M (which is equivalent to judging whether M cycles CYC of the control signal PWM have passed). Specifically, M can be an integer greater than or equal to 2. Based on the above, as shown in FIG. 6 , the clock control circuit 351 can control one of two adjacent pulses among the multiple pulses of the clock signal CLK to be delayed by M cycles CYC compared to the other, and can control one of two adjacent pulses among the multiple pulses of the latch signal LATCH to be delayed by M cycles CYC compared to the other.

Before continuing to explain operation S408 to operation S410 in FIG. 4, it should be noted that the multiple time points T9 to T12 in FIG. 6 respectively represent the execution time of comparing the low-side voltage signal VLS and the virtual voltage signal VVR. In addition, the digital signal DOUT set to "00110101" in the linear mode is represented as "53" in decimal in FIG. 6.

In some embodiments, operation S408 is performed in response to a rising edge of a pulse in the clock signal CLK in FIG. 6 (corresponding to time point T9). In operation S408, the digital control circuit 353 in FIG. 3 obtains a comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR. For example, the digital control circuit 353 generates an enable level comparison signal CMP (i.e., indicating that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS) at time point T9 in FIG. 6 through the sampling and holding circuit 531. In this case, operation S409 is performed in response to a rising edge of a pulse of the latch signal LATCH immediately following the time point T9 in FIG. 6 .

In operation S409, the logic control circuit 533 adds "1" to the bit value of the lowest bit (i.e., the eighth bit) of the digital signal DOUT. It should be understood that adding "1" to the bit value of the lowest bit of the digital signal DOUT will change the digital signal DOUT from "00110101" to "00110110", where "00110110" is "54" in decimal. Therefore, it can be seen that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is upward increase (+). Then, as described above, the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison.

After M cycles CYC, operation S408 is executed again in response to the rising edge of a pulse in the clock signal CLK in FIG. 6 (corresponding to time point T10). This time, the digital control circuit 353 still obtains the comparison result that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS (corresponding to the comparison signal CMP of the enable level). Therefore, operation S409 is executed again. Accordingly, the digital signal DOUT changes from "00110110" to "00110111", where "00110111" is "55" in decimal. Therefore, it can be known that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is upward increase (+). Then, the virtual voltage signal generating circuit 371 uses this digital signal DOUT again to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison.

After another M cycles CYC, operation S408 is executed again in response to the rising edge of a pulse in the clock signal CLK in FIG. 6 (corresponding to time point T11). This time, the digital control circuit 353 obtains a comparison result that the voltage level of the virtual voltage signal VVR is greater than the voltage level of the low-side voltage signal VLS (corresponding to the comparison signal CMP of the disable level). Therefore, operation S410 is executed.

In operation S410, the logic control circuit 533 subtracts "1" from the bit value of the least significant bit of the digital signal DOUT, which changes the digital signal DOUT from "00110111" to "00110110", where "00110110" is "54" in decimal. Therefore, it can be seen that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is downward decreasing (-). Then, the virtual voltage signal generating circuit 371 uses this digital signal DOUT again to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison. The operation of the virtual current signal generating circuit 153 after the time point T11 can be deduced from the description of the aforementioned operation S408 to the operation S410, and thus will not be elaborated here.

According to the above, in the linear mode, the digital control circuit 353 adjusts the digital signal DOUT multiple times according to the comparison signal CMP, and the adjustment amplitude of the digital signal DOUT is a certain value, that is, "1", which does not change with the increase in the number of times the digital signal DOUT is adjusted.

In FIG. 5 , a trend line C1 is drawn by connecting multiple voltage levels of the low-side voltage signal VLS at multiple time points T1 to T8, and a trend line C2 is drawn by connecting multiple voltage levels of the virtual voltage signal VVR at multiple time points T1 to T8. From the trends of trend lines C1 and C2, it can be seen that in the binary mode, the digital circuit 35 sets the bit value of each bit of the digital signal DOUT through N comparisons of the virtual voltage signal VVR and the low-side voltage signal VLS (corresponding to N cycles CYC of the control signal PWM), so that the virtual voltage signal VVR quickly approaches the low-side voltage signal VLS. Based on this, as shown in FIG. 6 , in the linear mode, the comparison between the virtual voltage signal VVR and the low-side voltage signal VLS is performed only after each M cycles CYC of the control signal PWM, so that the digital circuit 35 can fine-tune the digital signal DOUT according to the comparison result of the virtual voltage signal VVR and the low-side voltage signal VLS (that is, only adjust the bit value of the lowest bit of the digital signal DOUT). This approach allows the virtual voltage signal VVR to remain close to the low-side voltage signal VLS in the linear mode, but it will not change all the time (thereby saving energy). It can be seen that, no matter in the binary mode or the linear mode, the digital circuit 35 is used to adjust the digital signal DOUT according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR.

In some embodiments, the clock control circuit 351 of FIG. 3 can determine whether to perform a reload operation according to the voltage level of the reload signal RL. For example, when the reload signal RL is at an enable level, the clock control circuit 351 will immediately switch the binary mode signal MBIN and the linear mode signal MLIN to an enable level and a disable level, respectively, so that the virtual current signal generating circuit 153 re-enters the binary mode to operate (i.e., operations S402 to S407). When the reload signal RL is at a disable level, the clock control circuit 351 does not change (or maintain) the current voltage levels of the binary mode signal MBIN and the linear mode signal MLIN, so that the virtual current signal generating circuit 153 maintains operating in the current mode.

In the above embodiment, since M is an integer greater than or equal to 2, the comparison circuit 33 is equivalent to comparing the low-side voltage signal VLS with the virtual voltage signal VVR at intervals according to the time of at least two cycles CYC of the control signal PWM (also referred to as the first time) in the linear mode. Similarly, in the binary mode, the comparison circuit 33 compares the low-side voltage signal VLS with the virtual voltage signal VVR at intervals according to the time of at least one cycle CYC of the control signal PWM (also referred to as the second time). It can be seen that the first time is longer than the second time.

In the above embodiment, it can also be understood that the digital control circuit 353 is used to sample and hold the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR by being triggered by the clock signal CLK of the enable level, and is used to set the bit value of one of the multiple bits of the digital signal DOUT according to the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR by being triggered by the latch signal LATCH of the enable level.

In the above embodiments, as shown in FIGS. 5 and 6, each cycle CYC of the control signal PWM includes an enable period PON and a disable period POFF. Accordingly, in some embodiments, as shown in FIG. 5, when the binary mode signal MBIN and the linear mode signal MLIN are at the enable level and the disable level respectively, the clock signal CLK and the latch signal LATCH are sequentially switched to the enable level during each disable period POFF of the control signal PWM.

In addition, in some embodiments, as shown in FIG. 6 , when the binary mode signal MBIN and the linear mode signal MLIN are at the disable level and the enable level, respectively, the clock signal CLK and the latch signal LATCH are sequentially switched to the enable level for the first time, and then they are sequentially switched to the enable level again every at least two cycles CYC of the control signal PWM.

As can be seen from the description of the embodiments of FIGS. 4 to 6 above, the present disclosure further provides a method for generating a virtual current signal IVR. Please refer to FIG. 7, which is a flow chart of a method 700 for generating a virtual current signal according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 7, the method 700 for generating a virtual current signal includes a plurality of operations S701 to S705. It should be understood that the number of operations and/or the order of operations of the method 700 for generating a virtual current signal can also be increased, decreased and/or adjusted according to the description of the embodiments of FIGS. 1 to 6 above.

In some embodiments, as shown in FIG. 7 , operation S701 is performed after the power stage circuit 10 is turned on. In operation S701 , the driving circuit 13 drives the switch circuit 11 according to the control signal PWM. The description of operation S701 is similar to that of the embodiment of FIG. 1 , and is therefore omitted here.

In operation S702, the virtual current signal generating circuit 153 determines whether the power stage circuit 10 enters the binary mode or the linear mode according to the binary mode signal MBIN and the linear mode signal MLIN. The description of operation S701 is similar to the description of operation S401 in FIG. 4 and is therefore omitted here.

In some embodiments, the power stage circuit 10 enters the binary mode and thus the operation S703 is executed. In the operation S703, the digital circuit 35 in the virtual current signal generating circuit 153 adjusts the digital signal DOUT multiple times with the first adjustment amplitude according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. The description of the operation S703 is similar to the description of the embodiment of FIG. 5 and is therefore omitted here. In one embodiment, the first adjustment amplitude is variable (i.e., non-constant), and in detail, the first adjustment amplitude gradually changes as the number of times the digital signal DOUT is adjusted increases, for example, gradually decreases.

In some embodiments, the power stage circuit 10 enters the linear mode, and thus operation S704 is performed. In operation S704, the digital circuit 35 in the virtual current signal generating circuit 153 adjusts the digital signal DOUT multiple times with the second adjustment amplitude according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. The description of operation S704 is similar to the description of the embodiment of FIG. 6, and is therefore omitted here. In one embodiment, the second adjustment amplitude is a constant value.

In operation S705, the signal conversion circuit 37 in the virtual current signal generating circuit 153 adjusts the virtual voltage signal VVR according to the adjusted digital signal DOUT, and generates a virtual current signal IVR according to the adjusted virtual voltage signal VVR. By adjusting the digital signal DOUT, the virtual voltage signal VVR is adjusted to gradually approach the low-side voltage signal VLS. In this way, based on the adjustment of the virtual voltage signal VVR, the virtual current signal IVR can be corrected to gradually approach the output current signal IL. The description of operation S705 is similar to the description of the fifth and sixth embodiments, so it is omitted here.

After operation S705, the virtual current signal generating method 700 returns to operation S702 to continue adjusting the digital signal DOUT in the binary mode or the linear mode.

According to the above-mentioned virtual current signal generating method 700, by adjusting the digital signal DOUT and the virtual voltage signal VVR in the binary mode and/or the linear mode, the virtual current signal IVR can be further calibrated so that the virtual current signal IVR is substantially close to the output current signal IL, or substantially the same as the output current signal IL.

From the above implementation of the present disclosure, it can be seen that the virtual current signal IVR which is proportional to the output current signal IL is generated by the virtual current signal generating circuit 153, the power stage circuit 10 of the present disclosure can complete the current flow measurement during the conduction period LON of the low-side switch Q2, and can combine the virtual current signal IVR with the low-side current signal ILS obtained by the current flow measurement to generate the current monitoring signal IMON. It is worth noting that the current monitoring signal IMON generated by this method can be applied to applications with low working cycles.

In addition, compared with some related technologies, the current monitoring circuit 15 of the present disclosure significantly saves the number of components and can digitally adjust the virtual voltage signal VVR to correct the virtual current signal IVR and ensure the stability of the virtual current signal IVR. Therefore, the power stage circuit 10 and the current monitoring circuit 15 of the present disclosure have the advantages of low cost, application in low duty cycle applications, and generation of a current monitoring signal with high stability and high accuracy.

Although the contents of this disclosure have been disclosed as above in the form of implementation, it is not intended to limit the contents of this disclosure. A person with ordinary knowledge in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the contents of this disclosure. Therefore, the protection scope of the contents of this disclosure shall be subject to the scope defined by the attached patent application.

10: Power stage circuit 11: Switching circuit 13: Driving circuit 15: Current monitoring circuit 20: Controller 31: Current-to-voltage circuit 33: Comparison circuit 35: Digital circuit 37: Signal conversion circuit 151: Current flow detection circuit 153: Virtual current signal generation circuit 155: Signal combination circuit 351: Clock control circuit 353: Digital control circuit 371: Virtual voltage signal generation circuit 373: Voltage-to-current circuit 400: Adjustment method 531: Sample and hold circuit 533: Logic control circuit 700: Virtual current signal generation method C37, COUT: Capacitor element CLK: Clock signal CMP: Comparison signal CP1, CP2, CP3, LP1, LP2, LP3: Pulse CYC: Cycle DAC1: First digital-to-analog converter circuit DAC2: Second digital-to-analog converter circuit DOUT: Digital signal DOUT[0]~DOUT[7]: Bit GH: High-side drive signal GL: Low-side drive signal GND: Ground voltage HON, LON: On-time IL: Output current signal ILS: Low-side current signal IMON: Current monitoring signal IVR: Virtual current signal L: Inductor element LATCH: latch signal MBIN: binary mode signal MLIN: linear mode signal N1, SW: output terminal P1: first period P2: second period POFF: disable period PON: enable period POR: power-on reset voltage signal PWM: control signal Q1: high-side switch Q2: low-side switch R1: resistor element RL: reload signal S1: first switch S2: second switch S401~S410, S701~S705: operation SA: first current signal SB: second current signal SL: load terminal T1~T12: time point VIN: input voltage signal VLS: low-side voltage signal VOUT: output voltage signal VREF: reference voltage signal VVR: virtual voltage signal

FIG. 1 is a circuit block diagram of a power stage circuit and a controller according to some embodiments of the present disclosure. FIG. 2 is a waveform diagram of some signals related to the power stage circuit according to some embodiments of the present disclosure. FIG. 3 is a circuit diagram of a virtual current signal generating circuit according to some embodiments of the present disclosure. FIG. 4 is a flow chart of a digital signal adjustment method according to some embodiments of the present disclosure. FIG. 5 is a timing diagram of some signals related to the virtual current signal generating circuit in a binary mode according to some embodiments of the present disclosure. FIG. 6 is a timing diagram of some signals related to the virtual current signal generating circuit in a linear mode according to some embodiments of the present disclosure. Figure 7 is a flow chart of a method for generating a virtual current signal according to some embodiments of the present disclosure.

10: Power stage circuit

11: Switching circuit

13: Driving circuit

15: Current monitoring circuit

20: Controller

151: Current flow measurement circuit

153: Virtual current signal generating circuit

155:Signal combining circuit

COUT: Capacitor component

GH: High side drive signal

GL: low side drive signal

GND: Ground voltage

IL: Output current signal

ILS: Low-side current signal

IMON: Current monitoring signal

IVR: Virtual Current Signal

L: Inductor component

PWM: control signal

Q1: High side switch

Q2: Low side switch

SL: Load side

SW: output terminal

VIN: Input voltage signal

VOUT: output voltage signal

VREF: reference voltage signal

Claims (10)

A power stage circuit comprises: A switch circuit coupled to an output terminal of the power stage circuit for receiving an input voltage signal, and comprising a high-side switch and a low-side switch, wherein the output terminal is coupled to a load terminal via an inductor; A drive circuit coupled to the switch circuit and used to drive the switch circuit according to a control signal to generate an output voltage signal at the load terminal and an output current signal via the inductor; and A current monitoring circuit comprises: An electric current sensing circuit coupled to the switch circuit and used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal; A virtual current signal generating circuit is coupled to the current sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, to generate a digital signal, to adjust the digital signal according to a comparison result between the low-side voltage signal and a virtual voltage signal, to adjust the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and to generate a virtual current signal according to the virtual voltage signal; and A signal combining circuit is coupled to the current flow sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In a linear mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a first time. In the linear mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the first adjustment amplitude is a constant value. A power stage circuit as described in claim 1, wherein the virtual current signal generating circuit is used to adjust the bit value of a lowest bit of the digital signal with the first adjustment amplitude according to a comparison result between the low-side voltage signal and the virtual voltage signal, and the change in the bit value of the lowest bit of the digital signal corresponds to the first adjustment amplitude. A power stage circuit as described in claim 2, wherein when the voltage level of the virtual voltage signal is less than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to add the bit value of the lowest bit to the first adjustment amplitude, wherein when the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to subtract the bit value of the lowest bit from the first adjustment amplitude. A power stage circuit as described in claim 1, wherein in a binary mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a second time, wherein in the binary mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the second adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases. A power stage circuit as described in claim 4, wherein the first time is longer than the second time. A power stage circuit as described in claim 4, wherein the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal N times in the binary mode, wherein N is the number of bits of the digital signal, wherein before performing one of the N comparisons, the virtual current signal generating circuit is used to switch a corresponding one of the N bits of the digital signal from a first value to a second value to generate the virtual voltage signal for the one of the N comparisons, and to determine the bit value of the corresponding one of the N bits according to the comparison result of the one of the N comparisons. A power stage circuit as described in claim 6, wherein when the voltage level of the virtual voltage signal is less than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the second value, wherein when the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the first value. A power stage circuit as described in claim 1, wherein the first time is at least two cycles of the control signal. A power stage circuit comprises: A switch circuit coupled to an output terminal of the power stage circuit for receiving an input voltage signal, and comprising a high-side switch and a low-side switch, wherein the output terminal is coupled to a load terminal via an inductor; A drive circuit coupled to the switch circuit and used to drive the switch circuit according to a control signal to generate an output voltage signal at the load terminal and an output current signal via the inductor; and A current monitoring circuit comprises: An electric current sensing circuit coupled to the switch circuit and used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal; A virtual current signal generating circuit is coupled to the current flow sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, to generate a digital signal, to adjust the digital signal according to a comparison result between the low-side voltage signal and a virtual voltage signal in a first mode or a second mode, to adjust the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and to generate a virtual current signal according to the virtual voltage signal; and A signal combining circuit is coupled to the current flow sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the first mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude, and the first adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases. In the second mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude, and the second adjustment amplitude is a constant value. A power stage circuit as described in claim 9, wherein the virtual current signal generating circuit comprises: a current-to-voltage circuit coupled to the current sensing circuit and used to convert the low-side current signal into the low-side voltage signal; a comparison circuit coupled to the current-to-voltage circuit and used to compare the low-side voltage signal with the virtual voltage signal; a digital circuit coupled to the comparison circuit and used to generate the digital signal and to adjust the digital signal according to the comparison result between the low-side voltage signal and the virtual voltage signal in the first mode or the second mode; and A signal conversion circuit is coupled to the digital circuit and the comparison circuit, and is used to receive the digital signal, the input voltage signal, and the output voltage signal, and to generate the virtual voltage signal according to the digital signal, the input voltage signal, and the output voltage signal to generate the virtual current signal.

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