TWM643423U - GaN HIGH ELECTRON MOBILITY TRANSISTOR SWITCH CHIP - Google Patents

Abstract

A GaN high electron mobility transistor switch chip is provided. Its regulator receives an input voltage through a first pin and outputs a working voltage through a third pin. Its delay circuit is coupled to the second, third, and fourth pin and the regulator and receives a pulse width modulation signal through a second pin. Its GaN HEMT switch circuit has a gate coupled to the fourth pin and the delay circuit and a drain coupled to the fifth pin. Its Si-MOSFET has a source coupled to the fourth pin, the delay circuit and the gate of the GaN HEMT switch circuit and a drain coupled to the source of the GaN HEMT switch circuit. Its driving circuit is coupled to the delay circuit and the gate of the Si-MOSFET, receives the delayed pulse width modulation signal from the delay circuit, and determines an on/off status of the GaN HEMT switch circuit according to the voltage level of the delayed pulse width modulation signal.

Description

Gallium Nitride High Electron Mobility Transistor Switch Chip

The present invention relates to a gallium nitride (GaN) high electron mobility transistor (HIGH ELECTRON MOBILITY TRANSISTOR; HEMT) switch chip. Specifically, the present invention relates to a GaN HEMT switch chip that integrates a driving circuit, a silicon-based metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor; MOSFET) and a GaN HEMT switch circuit on the same chip.

At present, there are power switching elements made of GaN on the market, for example: 650V GaN-on-Si HEMT switching element, which is in depletion mode (Depletion mode; D mode). Since Gallium Nitride is a wide energy gap material, GaN HEMT switching elements are superior to switching elements made of silicon wafers in terms of switching efficiency and power density. GaN HEMT switching elements can maintain a high level of efficiency under high-speed switching conditions, enabling them to be applied to smaller components. At the same time, due to the high efficiency, less heat is generated. In some power products and equipment applications, the size of products and components can be reduced.

Since the GaN HEMT switching element is in depletion mode (that is, the gate of the GaN HEMT switching element is driven by a negative voltage), it is necessary to control the switching of the GaN HEMT switching element through a silicon-based MOSFET combined with other components, and this silicon-based MOSFET is used To form a normal closure. Currently, there are two ways to control the switching of GaN HEMT switching elements, namely cascode amplifier and direct drive.

Since the new system is related to the "direct drive" control method, only a brief description of the "direct drive" operation method is given here. In the "direct drive" control method as shown in FIG. 1, the negative voltage driving of the gate G0 of the GaN HEMT switching device 11 controls it to be turned off during normal operation. When no bias voltage is detected on the drain D0 of the GaN HEMT switch element 11, the silicon-based MOSFET 13 connected in series will turn off the circuit, and provide a current detection mechanism (eg, under voltage lockout (UVLO) circuit 15) for protection.

As mentioned above, the GaN HEMT switching element is depletion-type, and its gate is driven by a negative voltage, so an external silicon-based MOSFET is required to form a normal off state. However, GaN HEMT switching elements and these related control elements are composed of multiple chips. These elements are independent chips before they are integrated into the printed circuit board, and parasitic inductance will be generated during the manufacturing process, which will degrade the performance of the elements. Although GaN HEMT switching devices have ultra-high-speed switching capabilities, if the parasitic inductance is not suppressed, it will cause ringing, that is, undesirable oscillation of interference signals.

In view of this, there is an urgent need in the art to integrate GaN HEMT switching elements and their drivers (including the aforementioned silicon-based MOSFETs) on the same chip, so as to avoid the above-mentioned problems derived from multiple chips.

One object of the present invention is to provide a GaN HEMT switch chip. The gallium nitride HEMT switch chip includes a pin group, a voltage regulator, a delay circuit, a gallium nitride HEMT switch circuit, a silicon-based MOSFET and a driving circuit. The pin group includes a first pin, a second pin, a third pin, a fourth pin and a fifth pin. The regulator Coupled to the first pin and the third pin for receiving an input voltage through the first pin, generating an operating voltage in response to the input voltage, and outputting the operating voltage through the third pin. The delay circuit is coupled to the second pin, the third pin, the fourth pin and the regulator, and is used for receiving a pulse width modulation signal through the second pin. The GaN HEMT switch circuit has a gate, a source and a drain, wherein the gate of the GaN HEMT switch circuit is coupled to the fourth pin and the delay circuit, and the drain of the GaN HEMT switch circuit is coupled to the fifth pin. The silicon-based MOSFET has a gate, a source and a drain, wherein the source of the silicon-based MOSFET is coupled to the fourth pin, the delay circuit and the gate of the GaN HEMT switch circuit, and the drain of the silicon-based MOSFET is coupled to the source of the GaN HEMT switch circuit. The driving circuit is coupled to the delay circuit and the gate of the silicon-based MOSFET for receiving the PWM signal delayed by the delay circuit, and determines a switch state of the GaN HEMT switch circuit based on a voltage level of the delayed PWM signal.

In some implementation aspects, the pin group further includes a sixth pin, and the driving circuit is further coupled to the sixth pin.

In some implementation aspects, the driving circuit is also coupled to the voltage regulator and the third pin.

In some embodiments, the driving circuit is further coupled to the fourth pin, the gate of the GaN HEMT switch circuit, and the source of the silicon-based MOSFET.

In some embodiments, the GaN HEMT switch chip is packaged in a DFN 5x6 package structure.

In some implementations, the voltage regulator, the delay circuit, the silicon-based MOSFET and the driver circuit are included in a first die, and the GaN HEMT switch circuit is included in a second die.

In some implementations, the chipset further includes a sixth pin, a seventh pin, an eighth pin, and a ninth pin. A first bonding pad of the first die is coupled to an input terminal of the voltage regulator and coupled to the first pin through a first lead. A second bonding pad of the first die is coupled to an input terminal of the delay circuit and coupled to the second pin through a second lead. A third bonding pad of the first die is coupled to the voltage regulator and the delay circuit and coupled to the third pin through a third lead. A fourth bonding pad of the first die is coupled to the delay circuit and coupled to the fourth pin through a fourth lead. A fifth bonding pad of the first die is coupled to the driving circuit and coupled to one of the third pin and the sixth pin through a fifth lead. A sixth pad of the first die is coupled to a first pad of the second die. At least one seventh bonding pad of the first die is coupled to the driving circuit and the source of the silicon-based MOSFET. At least an eighth pad of the first die is coupled to a second pad of the second die. The second pad of the second die is coupled to the source of the GaN HEMT switch circuit. The third pad of the second die is coupled to the drain of the GaN HEMT switch circuit and coupled to the fifth pin, the seventh pin, the eighth pin and the ninth pin through a plurality of sixth leads.

In some embodiments, when the third pin is grounded through a first resistor and a capacitor connected in series, a fall time of a drain-to-source voltage of the GaN HEMT switch circuit is determined by the first resistor.

In some implementation aspects, when the sixth pin is grounded through a second external resistor connected in series, a rise time of the drain-to-source voltage of the GaN HEMT switch circuit is determined by the second resistor.

In some implementation aspects, the second pin can be externally connected with an RC filter to prevent a high frequency noise.

The gallium nitride HEMT switch chip provided by the present invention integrates the driving circuit, the silicon-based MOSFET and the gallium nitride HEMT switch circuit into the same chip, and uses a direct drive method to control the switch of the gallium nitride HEMT switch circuit. Since these circuits are integrated into a single chip, the effect of parasitic capacitance is greatly reduced, and the volume of packaged components is also reduced. Therefore, the use of the GaN HEMT switch chip provided by the present invention can reduce the ringing phenomenon and reduce the influence of electromagnetic interference signals.

The detailed technology and implementation methods of the present invention are described below in conjunction with the drawings, so that those who have ordinary knowledge in the technical field of the present invention can understand the technical characteristics of the claimed novelty.

11: GaN HEMT switching element

13: Silicon-based MOSFET

15: Undervoltage lockout circuit

2: GaN HEMT switch chip

21: Regulator

23: Delay circuit

25: GaN HEMT switch circuit

27: Silicon-based MOSFET

29: Drive circuit

3: GaN HEMT switch chip

CH: cooling channel

C1, C _PWM , C _VCC , C _VDD : capacitance

D: Fifth pin

D': the seventh pin

D”: the eighth pin

D''': the ninth pin

DE1: First Die

DE2: Second Die

D0, D1, D2: drain

G0, G1, G2: gate

PG: the sixth pin

PVdd: the sixth pin

PWM: the second pin

P11, P21: The first pad

P12, P22: Second pad

P13, P23: The third pad

P14: Fourth pad

P15: Fifth pad

P16: Sixth pad

P17: The seventh pad

P18: Eighth pad

R1, R2, R _CS , R _PG , R _PWM , R _VDD : Resistors

S: the fourth pin

S1, S2: source

Vcc: the first pin

Vdd: the third pin

Vin: the first pin

Figure 1 depicts a schematic circuit diagram for controlling the switching of GaN HEMT switching elements by "direct drive".

FIG. 2 illustrates a circuit architecture diagram of a GaN HEMT switch chip 2 in some embodiments of the present invention.

FIG. 3 illustrates a circuit structure diagram of a GaN HEMT switch chip 3 in other embodiments of the present invention.

FIG. 4 illustrates the circuit coupling method for setting the slew rate of the GaN HEMT switch circuit 25 .

FIG. 5 shows a schematic bottom view of a GaN HEMT switch chip 3 adopting a DFN 5x6 package structure.

Figure 6 illustrates the possible soldering methods when packaged in a DFN 5x6 package architecture.

FIG. 7 shows a partial circuit wiring diagram of the GaN HEMT switch chip 3 in an actual application.

FIG. 8 is a schematic diagram of a printed circuit board layout of a GaN HEMT switch chip 3 .

The following will explain the GaN HEMT switch chip provided by the present invention through the implementation. However, these embodiments are not intended to limit the present invention to be implemented in any environment, application or manner as described in these embodiments. Therefore, the description of the following embodiments is only to illustrate the purpose of the present invention, but not to limit the scope of rights of the present invention. It should be understood that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not shown. In addition, the dimensions of the components in the drawings and the proportional relationship between the components are only for illustration and description, and are not intended to limit the scope of the present invention. Furthermore, unless otherwise stated, "a", "the" and similar terms used in this specification and scope of patent application shall be understood as including singular and plural forms.

FIG. 2 illustrates a circuit architecture diagram of a GaN HEMT switch chip 2 in some embodiments of the present invention. The GaN HEMT switch chip 2 includes a pin group, a voltage regulator 21 , a delay circuit 23 , a GaN HEMT switch circuit 25 , a silicon-based MOSFET 27 and a drive circuit 29 . The pin group at least includes a first pin Vin, a second pin PWM, a third pin Vdd, a fourth pin S and a fifth pin D.

The coupling relationship among the various circuit elements of the GaN HEMT switch chip 2 will now be described. The regulator 21 is coupled to the first pin Vin and the third pin Vdd. The delay circuit 23 is coupled to the second pin PWM, the third pin Vdd, the fourth pin S and the regulator 21 . The GaN HEMT switch circuit 25 has a gate G1 , a source S1 and a drain D1 , wherein the gate G1 is coupled to the fourth pin S and the delay circuit 23 , and the drain D1 is coupled to the fifth pin D. The silicon-based MOSFET 27 has a gate G2, a source S2 and a drain D2, wherein the source S2 is coupled to the fourth pin S, the delay circuit 23 and the gate G1 of the GaN HEMT switch circuit 25, and the drain D2 is coupled to the source S1 of the GaN HEMT switch circuit 25. The driving circuit 29 is coupled to the delay circuit 23 , the gate G2 of the silicon-based MOSFET 27 , the fourth pin S, the gate G1 of the GaN HEMT switch circuit 25 , and the source S2 of the silicon-based MOSFET 27 . In some embodiments, the pin group of the HEMT switch chip 2 may further include a sixth pin PVdd, and the driving circuit 29 is coupled to the sixth pin PVdd.

FIG. 3 illustrates a circuit architecture diagram of a GaN HEMT switch chip 3 in some other embodiments of the present invention. The GaN HEMT switch chip 3 includes a pin group, a voltage regulator 21 , a delay circuit 23 , a GaN HEMT switch circuit 25 , a silicon-based MOSFET 27 and a driving circuit 29 . The pin group at least includes a first pin Vcc, a second pin PWM, a third pin Vdd, a fourth pin S and a fifth pin D.

The coupling relationship among the various circuit elements of the GaN HEMT switch chip 3 will now be described. The regulator 21 is coupled to the first pin Vcc and the third pin Vdd. The delay circuit 23 is coupled to the second pin PWM, the third pin Vdd, the fourth pin S and the regulator 21 . The GaN HEMT switch circuit 25 has a gate G1 , a source S1 and a drain D1 , wherein the gate G1 is coupled to the fourth pin S and the delay circuit 23 , and the drain D1 is coupled to the fifth pin D. The silicon-based MOSFET 27 has a gate G2, a source S2 and a drain D2, wherein the source S2 is coupled to the fourth pin S, the delay circuit 23 and The gate G1 and the drain D2 of the GaN HEMT switch circuit 25 are coupled to the source S1 of the GaN HEMT switch circuit 25 . The driving circuit 29 is coupled to the delay circuit 23 , the gate G2 of the silicon-based MOSFET 27 , the voltage regulator 21 and the third pin Vdd.

The GaN HEMT switch chip 3 and the GaN HEMT switch chip 2 can be coupled and operated in the same manner, so only the GaN HEMT switch chip 3 will be described in detail below. Those with ordinary knowledge in the technical field of the present invention can understand how to realize the related coupling and operation on the GaN HEMT switch chip 2 according to the related description of the GaN HEMT switch chip 3 , so no further details are given.

The voltage regulator 21 is configured to receive an input voltage (not shown) through the first pin Vcc. For example, the voltage level of the input voltage may be 10V to 24V, but it should be understood that it is not limited thereto. When the input voltage is supplied to the first pin Vcc, each circuit element of the GaN HEMT switch chip 3 is in an active and operable state. The voltage regulator 21 generates an operating voltage (not shown) in response to the input voltage, and can output the operating voltage through the third pin Vdd. For example, the voltage level of the working voltage may be 5.2 volts, but it should be understood that it is not limited thereto. The delay circuit 23 is configured to receive a pulse width modulation signal (not shown) through the second pin PWM. The driving circuit 29 is configured to receive the PWM signal delayed by the delay circuit 23 , and determine a switching state of the GaN HEMT switch circuit 25 based on a voltage level of the delayed PWM signal.

In some implementations, the pin group of the GaN HEMT switch chip 3 may further include a sixth pin PG, and the driving circuit 29 is further coupled to the sixth pin PG.

In some implementations, as shown in FIG. 4, a GaN HEMT switch circuit can be set by connecting a resistor R1 to the third pin Vdd or connecting a resistor R2 to the sixth pin PG. 25 slew rate (slew rate). By setting the slew rate, the overall performance of the GaN HEMT switch chip 3 can be optimized and electromagnetic interference can be reduced.

The control of the slew rate is further described here. If the third pin Vdd is grounded through the external resistor R1 and capacitor C1 connected in series, a falling time (falling time) of the voltage V _DS from the drain D1 to the source S1 of the GaN HEMT switch circuit 25 is determined by the resistor R1 . As shown in FIG. 4 , as the resistance R1 increases, the falling edge of the voltage V _DS from the drain D1 to the source S1 of the GaN HEMT switch circuit 25 decreases. In addition, if the sixth pin PG is connected to the ground through the external resistor R2, a rising time (rising time) of the voltage V _DS from the drain D1 to the source S1 of the GaN HEMT switch circuit 25 is determined by the resistor R2. As shown in FIG. 4 , as the resistance R2 increases, the rising edge of the voltage V _DS from the drain D1 to the source S1 of the GaN HEMT switch circuit 25 decreases.

In some embodiments, in order to make the GaN HEMT switch chip 3 and the device using the GaN HEMT switch chip 3 operate robustly, the resistor R1 can be set to at least 10 ohms.

In some implementations, in order to avoid erroneous driving, an RC filter (not shown) can be connected externally to the second pin PWM to prevent a high-frequency noise.

In some implementations, the GaN HEMT switch chip 3 can be packaged in a DFN 5x6 package structure. If the DFN 5x6 package structure is adopted, in some embodiments, the GaN HEMT switch chip 3 may further include a sixth pin PG, a seventh pin D', an eighth pin D" and a ninth pin D'''. Please refer to FIG.

In some embodiments, the voltage regulator 21 , the delay circuit 23 , the silicon-based MOSFET 27 and the driving circuit 29 are included in a first die DE1 , and the GaN HEMT switch circuit 25 is included in a second die DE2 .

In some embodiments, the first die DE1 and the second die DE2 are packaged in a DFN 5x6 package structure. In addition, if packaged in a DFN 5x6 package structure, in some embodiments, the soldering method depicted in FIG. 6 can be used.

The first die DE1 includes a first bonding pad P11, a second bonding pad P12, a third bonding pad P13, a fourth bonding pad P14, a fifth bonding pad P15, a sixth bonding pad P16, at least one seventh bonding pad P17 and at least one eighth bonding pad P18. The second die DE2 includes a first pad P21 , a second pad (source pad) P22 and a third pad (drain pad) P23 .

The first pad P11 of the first die DE1 is coupled to an input terminal of the voltage regulator 21 and coupled to the first pin Vcc through a first lead. The second pad P12 of the first die DE1 is coupled to an input end of the delay circuit 23 and is coupled to the second pin PWM through a second lead. The third pad P13 of the first die DE1 is coupled to the voltage regulator 21 and the delay circuit 23 and is coupled to the third pin Vdd through a third lead. The fourth pad P14 of the first die DE1 is coupled to the delay circuit 23 and coupled to the fourth pin S through a fourth lead. The fifth pad P15 of the first die DE1 is coupled to the driving circuit 29 and coupled to the third pin Vdd through a fifth lead. In some implementation aspects, the fifth pad P15 may not be coupled to the third pin Vdd, but instead be coupled to the sixth pin PG. The sixth pad P16 of the first die DE1 is coupled to the first pad P21 of the second die DE2. At least one seventh pad P17 of the first die DE1 is coupled to the driving circuit 29 and the source S2 of the silicon-based MOSFET 27 . At least one eighth pad P18 of the first die DE1 is coupled to the second pad P22 of the second die DE2.

The second pad P22 of the second die DE2 is coupled to the source S1 of the GaN HEMT switch circuit 25 . The third pad P23 of the second die DE2 is coupled to the drain D1 of the GaN HEMT switch circuit 25 and coupled to the fifth pin D, the seventh pin D', the eighth pin D" and the ninth pin D''' through a plurality of sixth leads.

FIG. 7 shows a partial circuit connection diagram of the GaN HEMT switch chip 3 in an actual application, but it should be understood that the circuit connection diagram is not intended to limit the scope of the present invention. Many practical applications need to sense the current flowing through the GaN HEMT switch chip 3. A typical connection method is to configure a current sensing resistor between the fourth pin S and the fifth pin D, the seventh pin D', the eighth pin D" or/and the ninth pin D'''. In this configuration, all components around the GaN HEMT switch chip 3 (for example: capacitor C _VCC , capacitor C _VDD , capacitor C _PWM , resistor R _VDD , resistor R _PG , resistor R _PWM ) need to be grounded to The fourth pin S, as shown in Figure 7.

In some embodiments, the capacitor C _VCC may have a value of 0.1 microfarads (μF), the capacitor C _VDD may have a value of 0.01 microfarads, the resistor R _VDD may have a value of 25 ohms, the resistor R _PG may have a value of 4.7 ohms, the resistor R _PWM may have a value of 100 ohms, and the capacitor C _PWM may have a value of 100 pico farads (pF). It should be noted that the values of the above-mentioned capacitors and resistors are only for illustration and not for limiting the scope of the present invention, and may be other values in other embodiments. In addition, the minimum value of the resistor R _VDD is 10 ohms, and the minimum value of the resistor R _PG is 0 ohms.

In some embodiments, the practical printed circuit board layout of the GaN HEMT switch chip 3 shown in FIG. 7 may be as shown in FIG. 8 , where the left side is a top view and the right side is a bottom view. For switching power supplies that require high frequency and large peak currents, printed circuit board layout bureau is extremely important. A good printed circuit board layout will reduce the electromagnetic interference on the current path and reduce the temperature of the power device.

As shown in FIG. 8, all components around the GaN HEMT switch chip 3 (including: capacitor C _VCC , resistor R _PWM , capacitor C _PWM , resistor R _VDD , capacitor C _VDD , resistor R _PG ) are arranged as close as possible. In addition, heat dissipation channels CH are placed on the source pads to conduct heat away from the bottom of the packaged chip and the printed circuit board. For high power density design, use a large thermal plane as much as possible to connect the heat dissipation channel CH to the source pad and other printed circuit board layers, thereby reducing the temperature of the GaN HEMT switch chip 3 .

To sum up, the GaN HEMT switch chip provided by the present invention integrates the driving circuit, the silicon-based MOSFET and the GaN HEMT switch circuit into the same chip, and uses a direct drive method to control the switching of the GaN HEMT switch circuit. Since these circuits are integrated into a single chip, the effect of parasitic capacitance is greatly reduced, and the volume of packaged components is also reduced. Therefore, the use of the GaN HEMT switch chip provided by the present invention can reduce the ringing phenomenon and reduce the influence of electromagnetic interference signals. In addition, the slew rate can be set by externally connecting a resistor or/and capacitor to a specific pin of the GaN HEMT switch chip, and an RC filter can be externally connected to a specific pin of the GaN HEMT switch chip to prevent high-frequency noise, thereby further improving the performance of the GaN HEMT switch chip provided by the present model. Furthermore, the temperature of the GaN HEMT switch chip provided by the present invention can be greatly reduced through proper layout of the printed circuit board (ie, placing the heat dissipation channel CH on the source pad).

It should be noted that some terms (such as: pins, bare crystals, pads) used in this patent specification and scope of application are preceded by "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth" or "ninth" used to distinguish these terms. If there is no special indication that there is an order among these terms, or the order between these terms cannot be seen from the context, the order between these terms is not limited by the words "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth" or "ninth".

The above-mentioned embodiments are used to illustrate some implementation aspects of the present invention and explain the technical features of the present invention, but are not used to limit the scope and scope of the present invention. Any change or equivalence arrangement that can be easily accomplished by a person with ordinary knowledge in the technical field of the present model belongs to the scope claimed by the present model, and the scope of protection of the rights of the present model is subject to the scope of the patent application.

21: Regulator

23: Delay circuit

25: GaN HEMT switch circuit

27: Silicon-based MOSFET

29: Drive circuit

3: GaN HEMT switch chip

D: Fifth pin

DE1: First Die

DE2: Second Die

D1, D2: drain

G1, G2: gate

PG: the sixth pin

PWM: the second pin

S: the fourth pin

S1, S2: source

Vcc: the first pin

Vdd: the third pin

Claims (10)

A gallium nitride (GaN) high electron mobility transistor (High Electron Mobility Transistor; HEMT) switch chip, comprising: A pin group, including a first pin, a second pin, a third pin, a fourth pin and a fifth pin; a voltage regulator, coupled to the first pin and the third pin, for receiving an input voltage through the first pin, generating an operating voltage in response to the input voltage, and outputting the operating voltage through the third pin; a delay circuit, coupled to the second pin, the third pin, the fourth pin and the voltage regulator, and used for receiving a pulse width modulation signal through the second pin; A gallium nitride HEMT switch circuit having a gate, a source and a drain, wherein the gate of the gallium nitride HEMT switch circuit is coupled to the fourth pin and the delay circuit, and the drain of the gallium nitride HEMT switch circuit is coupled to the fifth pin; a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) having a gate, a source and a drain, wherein the source of the silicon-based MOSFET is coupled to the fourth pin, the delay circuit and the gate of the GaN HEMT switch circuit, and the drain of the silicon-based MOSFET is coupled to the source of the GaN HEMT switch circuit; and A drive circuit, coupled to the delay circuit and the gate of the silicon-based MOSFET, is used to receive the pulse width modulation signal delayed by the delay circuit, and determine a switching state of the GaN HEMT switch circuit based on a voltage level of the delayed pulse width modulation signal. The GaN HEMT switch chip as claimed in claim 1, wherein the pin group further includes a sixth pin, and the driving circuit is further coupled to the sixth pin. The GaN HEMT switch chip as claimed in claim 1 or 2, wherein the driving circuit is further coupled to the voltage regulator and the third pin. The GaN HEMT switch chip as claimed in claim 1 or 2, wherein the driving circuit is further coupled to the fourth pin, the gate of the GaN HEMT switch circuit, and the source of the silicon-based MOSFET. The GaN HEMT switch chip as claimed in Claim 1, wherein the GaN HEMT switch chip is packaged in a DFN 5x6 package structure. The GaN HEMT switch chip as described in Claim 5, wherein the voltage regulator, the delay circuit, the silicon-based MOSFET and the driving circuit are included in a first die, and the GaN HEMT switch circuit is included in a second die. The gallium nitride HEMT switch chip as described in claim 6, wherein the chip group further includes a sixth pin, a seventh pin, an eighth pin, and a ninth pin, Wherein, a first bonding pad of the first die is coupled to an input terminal of the voltage regulator and coupled to the first pin through a first lead, Wherein, a second bonding pad of the first die is coupled to an input terminal of the delay circuit and coupled to the second pin through a second lead, Wherein, a third bonding pad of the first die is coupled to the voltage regulator and the delay circuit and coupled to the third pin through a third lead, Wherein, a fourth bonding pad of the first die is coupled to the delay circuit and coupled to the fourth pin through a fourth lead, Wherein, a fifth bonding pad of the first die is coupled to the driving circuit and coupled to one of the third pin and the sixth pin through a fifth lead, wherein a sixth pad of the first die is coupled to a first pad of the second die, wherein at least one seventh bonding pad of the first die is coupled to the driving circuit and the source of the silicon-based MOSFET, wherein at least one eighth pad of the first die is coupled to a second pad of the second die, Wherein, the second bonding pad of the second die is coupled to the source of the GaN HEMT switch circuit, and Wherein, the third pad of the second die is coupled to the drain of the GaN HEMT switch circuit and coupled to the fifth pin, the seventh pin, the eighth pin and the ninth pin through a plurality of sixth leads. The gallium nitride HEMT switch chip as described in claim 2, wherein when the third pin is grounded through a first resistor and a capacitor connected in series externally, a fall time (fall time) of a drain-to-source voltage of the gallium nitride HEMT switch circuit is determined by the first resistor. The GaN HEMT switch chip as claimed in claim 2, wherein when the sixth pin is grounded through a second resistor connected in series externally, a rise time (rise time) of the drain-to-source voltage of the GaN HEMT switch circuit is determined by the second resistor. The GaN HEMT switch chip according to claim 1, wherein the second pin can be connected with an RC filter to prevent high frequency noise.