TWM643038U - Microcontroller authority management execution system - Google Patents

Abstract

A microcontroller authority management execution system includes a microcontroller and a computer device. The computer device sets a user mode and an administrator mode corresponding to memory resources of the microcontroller by using a development software kit through an authority management interface. The computer device indicates available peripheral device sets and function sets for the user mode through the memory resources when the administrator mode is performed. When the peripheral device sets and the function sets are used under the user mode, the peripheral device sets and the function sets are unchangeable.

Description

Authorization Management Execution System of Microcontroller

This creation discloses a microcontroller authority management execution system, especially a microcontroller authority management implementation system with a manager mode and a user mode.

With the rapid development of science and technology, various microcontrollers (Microcontroller) are gradually used in daily life. A microcontroller can integrate a processor, memory, timer/counter, and various input/output interfaces on an integrated circuit chip, so it is also called a microcomputer. Current microcontrollers support 32-bit and 64-bit Trusted Execution Environment (TEE). A Trusted Execution Environment is an environment dedicated to operating security-critical missions, in which programs and data can be guaranteed to be protected in terms of confidentiality and integrity.

The Trusted Execution Environment provides corresponding resource usage for users at different levels according to the hardware manufacturer's factory setting plan. However, the current TEE mechanism of microcontrollers lacks the flexibility to be applied in various scenarios. For example, if an application developer wants to protect his own design resources, calling and returning various security fields will be very complicated.

An embodiment of the present invention proposes a microcontroller authority management execution system. The authority management execution system of the microcontroller includes a microcontroller and a computer device. The microcontroller includes a user mode area and a supervisor mode area. The user mode area includes a user mode application module, a user mode memory module, a user mode interrupt request module and a user mode input/output module. The user mode memory module is coupled to the user mode application module. The user mode interrupt request module is coupled to the user mode memory module. The user mode input/output module is coupled to the user mode interrupt request module. The supervisor mode area includes a supervisor mode application module, a supervisor mode memory module, a supervisor mode interrupt request module and a supervisor mode input/output module. The supervisor mode memory module is coupled to the supervisor mode application module. The supervisor mode interrupt request module is coupled to the supervisor mode memory module. The supervisor mode I/O module is coupled to the supervisor mode interrupt request module. The computer device is coupled to the microcontroller for setting the microcontroller. Through the authority management interface, the computer device uses the development software kit to set the memory resources of the microcontroller to correspond to the administrator mode in the administrator mode area and the user mode in the user mode area. The computer device is set in the manager mode, and the set of peripheral devices and function sets in the set manager mode application module are pointed to for use in the user mode through the memory resource. When using peripheral set and function set in user mode, peripheral set and function set cannot be changed.

FIG. 1 is a block diagram of an embodiment of the authority management execution system 100 of the microcontroller of the present invention. The microcontroller authority management execution system 100 includes a microcontroller 10 and a computer device PC. Various software, hardware and even peripheral devices of the microcontroller 100 can be divided into two areas. For example, in FIG. 1 , the microcontroller 10 can be divided into a user mode area 10U and an administrator mode area 10A. The user mode area 10U corresponds to the user mode described later, and has relatively low management authority. The administrator mode area 10A corresponds to the administrator mode described later, and has higher management authority. The user mode area 10U includes a user mode application module 10U1 , a user mode memory module 10U2 , a user mode interrupt request (Interrupt Request, IRQ) module 10U3 and a user mode I/O module 10U4. The user-mode application module 10U1 includes user-operable objects, application functions or attributes. The user mode memory module 10U2 may be a Static Random Access Memory (SRAM) configured exclusively for the user. The user mode memory module 10U2 is coupled to the user mode application module 10U1. The user mode interrupt request module 10U3 is coupled to the user mode memory module 10U2. As explained here, an interrupt request can temporarily stop a running program and allow a special program (such as an interrupt handler) to run. In practice, an interrupt request can be identified by an index with an IRQ format. The user mode input/output module 10U4 is coupled to the user mode interrupt request module 10U3. The user mode input/output module 10U4 can be used to control users such as asynchronous transceiver transmitter (Universal Asynchronous Receiver/Transmitter, UART), general-purpose input and output (General-Purpose Input/output, GPIO) or peripheral Peripherals and more. The supervisor mode area 10A includes a supervisor mode application module 10A1 , a supervisor mode memory module 10A2 , a supervisor mode interrupt request module 10A3 and a supervisor mode input/output module 10A4 . The administrator mode application module 10A1 includes objects, application functions or attributes operable by the administrator. The supervisor mode memory module 10A2 can be a static random access memory configured exclusively for the user. The administrator mode memory module 10A2 is coupled to the administrator mode application module 10A1. The supervisor mode interrupt request module 10A3 is coupled to the supervisor mode memory module 10A2. The supervisor mode I/O module 10A4 is coupled to the supervisor mode interrupt request module 10A3. The administrator mode I/O module 10A4 can be used to control administrators, such as asynchronous transceivers, general-purpose input/output or peripheral devices, and the like. The computer device PC is coupled to the microcontroller 10 for setting the microcontroller 10 . In the authority management execution system 100 of the microcontroller, the computer device PC can set the memory resources of the microcontroller 10 to correspond to the administrator mode and the user mode under the administrator mode area 10A through the authority management interface and using the development software kit User mode under area 10U. The computer device 10 can be set to be in the manager mode, and the set of peripheral devices and function sets in the set manager mode application module can be pointed to for use in the user mode through the memory resource. Since the authority in the administrator mode is greater than that in the user mode, some resources such as peripheral devices and libraries can be "configured" in the administrator mode for use in the user mode. However, due to the low user authority, when using the peripheral device set and function set configured by the administrator in the user mode, the peripheral device set and the function set cannot be changed, and the source code content cannot be browsed. The microcontroller 10 may also include a specific file register 10B. The specific file register 10B is used to store specific files or special files, and can be designated to be used in the user mode and/or the administrator mode.

FIG. 2 is a schematic diagram of the configuration of the administrator mode and the user mode in memory resources in the authority management execution system 100 of the microcontroller. As mentioned above, the microcontroller 10 includes a supervisor mode memory module 10A2 and a user mode memory module 10U2. The memory addresses corresponding to the supervisor mode memory module 10A2 and the user mode memory module 10U2 are separated, and the details are as follows. The general data of the supervisor mode can be allocated in the first memory area SRAM_NA1 of the memory resource. Therefore, the first memory section SRAM_NA1 can also be called the general memory section SRAM_NA1 of the manager. The general data of the user mode can be allocated in the second memory area SRAM_NU1 of the memory resource. Therefore, the second memory section SRAM_NU1 can also be called the user's general memory section SRAM_NU1. The security data of the supervisor mode can be allocated in the third memory section SRAM_SECA1 of the memory resource. Therefore, the third memory section SRAM_SECA1 can also be called the administrator's secure memory section SRAM_SECA1. The security data of the user mode can be allocated in the fourth memory section SRAM_SECU1 of the memory resource. Therefore, the fourth memory section SRAM_SECU1 can also be called the user's secure memory section SRAM_SECU1. Therefore, the general memory area SRAM_NA1 of the administrator and the general memory area SRAM_NU1 of the user belong to the general memory area SRAM_N. The general memory area SRAM_N can access data of general security level. The administrator's secure memory section SRAM_SECA1 and the user's secure memory section SRAM_SECU1 belong to the secure memory section SRAM_SEC. In practice, the secure memory section SRAM_SEC can be stored in the physical random access memory by hardware in a data scrambled manner (such as scramble), so it has a higher security level and can access more confidential data. Alternatively, a mapping table (Mapping Table) can be generated to correspond to the output address and the input address in the memory resource according to the mapping table, which can enhance security. The mapping table can be generated by a plurality of random random numbers. For example, the random random numbers can be generated by a Physical Unclonable Function (PUF) random number source. Moreover, the administrator's normal memory section SRAM_NA1 , the user's normal memory section SRAM_NU1 , the administrator's secure memory section SRAM_SECA1 , and the user's secure memory section SRAM_SECU1 do not overlap.

FIG. 3 is a schematic diagram of the authority management interface UI in the authority management execution system 100 of the microcontroller. The rights management interface UI can be in the mode shown in Figure 3, but it is not limited thereto, and any reasonable interface changes belong to the category disclosed in this creation. The authority management interface UI can be generated by a development software kit for configuring the microcontroller 10 on the PC side of the computer device. The rights management interface UI may include multiple windows, such as windows W1 to W5. The administrator can open the authority management interface UI to set various parameters. For example, the administrator can allocate the SRAM size available to the administrator through the window W1, which includes the above-mentioned general memory interval (eg 6KB) and secure memory interval (eg 2KB). The rest of the general memory area and the security memory area will be allocated to the user. The administrator can allocate the flash memory (Flash) and the electronically erasable rewritable read-only memory (Electrically-Erasable Programmable Read-Only Memory, EEPROM) size available to the administrator through the window W2, such as setting the flash memory is 64KB and EEPROM is 7.5KB. The administrator can set the Peripheral Privilege authority through the window W3, such as selecting the available peripheral devices in the administrator mode by using check boxes and drop-down menus. The administrator can set the authority of each pin privilege (GPIO Privilege) of the general-purpose input and output (GPIO) through the window W4, such as using the check box and the drop-down menu to select the general-purpose input and output pins available in the administrator mode bit. The administrator can set the authority to control the parameter privileges of the system through the window W5, such as selecting the parameters that can be controlled in the administrator mode by using the check box and the drop-down menu. However, the window positions, interface adjustment modes, interface parameter setting methods and templates shown in Figure 3 are not limited to this creation.

FIG. 4 is a flow chart of executing the boot program in the authority management execution system 100 of the microcontroller. FIG. 5 is a schematic diagram of the match between the boot ROM 11 and the summary viewer 12 in the authorization management execution system 100 of the microcontroller. The process of executing the boot program by the authority management execution system 100 of the microcontroller includes step S401 to step S411. Any reasonable step change or technical replacement belongs to the category disclosed in this creation. Step S401 to step S411 is described as follows: Step S401: microcontroller 10 initialization; Step S402: The microcontroller 10 is synchronized with the computer device PC through the development software kit; Step S403: enter write mode; Step S404: Judging whether to leave the writing mode, if so, enter step S405; if not, return to step S403; Step S405: Execute the secure boot procedure; Step S406: Check manager summary data; Step S407: Whether the summary information of the manager passes the inspection, if yes, go to step S408; if not, go to step S411; Step S408: Check user summary data; Step S409: Whether the user summary information is checked, if yes, go to step S410; if not, go to step S411; Step S410: Enter the standby state. Step S411: A boot failure message is generated.

After the computer device PC is connected to the microcontroller 10 through the development software kit, in step S401, the microcontroller 10 can be initialized. Then, the microcontroller 10 is synchronized with the computer device PC through the development software kit. In step S403, the microcontroller 10 enters the write mode. In step S404, the computer device PC determines whether the microcontroller 10 is out of the writing mode. If leaving the writing mode, enter step S405 to execute a secure boot procedure. If the writing mode has not been left, return to step S403. Please refer to Figure 5 for the secure boot procedure. In practice, the first hardware and the second hardware can be used to check whether they match. If the first hardware and the second hardware match, then the verification of safe boot is passed. For example, the first hardware can be a Boot Read-Only Memory, and the second hardware can be a Digest Checker. The content of the boot ROM 11 and the summary viewer 12 can use a predetermined bit length string to check for a match. For example, the contents of the boot ROM 11 and the summary viewer 12 can be compared using a 256-bit hash code to determine whether they match. Subsequent steps are all completed according to the secure boot matching method shown in FIG. 5 . In step S406, the manager's summary information is checked. Next, the manager summary data in the summary viewer 12 will be compared with the boot ROM 11. In step S407, if the manager summary data passes the check, then go to step S408. If the administrator's summary information does not pass the check, it means that the matching fails, and then proceed to step S411 to generate a boot failure message. In step S408, the user summary data in the summary viewer 12 will be compared with the boot ROM 11, and in step S409, if the user summary data pass the check, then go to step S410. If the user summary data does not pass the check, it means that the matching fails, and the process proceeds to step S411 to generate a boot failure message. In other words, since the permission management execution system 100 of the microcontroller can check the string between different hardware to determine whether to boot, it has a high degree of security.

Any reasonable permission setting or function calling of the permission management execution system 100 of the microcontroller belongs to the category disclosed in this invention. For example, the microcontroller 10 can be a 16-bit microcontroller. The permission management execution system 100 of the microcontroller can obtain a set of interrupt vector resources, and use the development software kit to direct the set of interrupt vector resources to the supervisor mode and the user mode. As mentioned above, the supervisor mode has higher authority, so in the supervisor mode, all the interrupt vector resources of the microcontroller can be used. Moreover, in the manager mode, it is also possible to plan the interrupt vector resources that can be called in the user mode in the group of interrupt vector resources. In another embodiment, the permission management execution system 100 of the microcontroller can obtain a special interrupt vector. The manager mode uses a special interrupt vector to enter the user mode after executing the function. Then, enter the manager mode again from the user mode, and use the special character string to write the special memory location. Here, if the subroutine call of the user mode is reserved in advance in the manager mode, the user mode can return to the user mode after entering the manager mode and executing the subroutine call. The authority management execution system 100 of the microcontroller can also introduce a password mechanism to increase security. For example, the authority management execution system 100 of the microcontroller can set the administrator mode password. Therefore, when entering the administrator mode, the development software package can authenticate the administrator mode password to protect the parameters and function sets of the set of peripheral devices set in the administrator mode.

FIG. 6 is a flow chart of the microcontroller authority management execution system 100 operating the microcontroller authority management method. The flow of the permission management method of the microcontroller includes step S601 to step S604. Any reasonable technical changes belong to the category disclosed in this creation. Step S601 to step S604 are described as follows: Step S601: providing a microcontroller 10; Step S602: Generate the rights management interface UI; Step S603: Through the authority management interface UI, use the development software kit to set the administrator mode and user mode corresponding to the memory resources of the microcontroller 10; Step S604: In the manager mode, the set peripheral device set and function set are pointed to by the memory resource for use in the user mode.

The details of step S601 to step S604 have been described above in detail, so they will not be repeated here. The permission management execution system 100 of the microcontroller can independently set the permissions of the functions, functions and peripheral devices used by the microcontroller, so it is suitable for various scenarios and applications. In addition to having high data protection capabilities, it also has high operating flexibility.

To sum up, this creation describes a microcontroller rights management execution method and a microcontroller rights management execution system. The authority management execution system of the microcontroller can independently set the authority of the functions, functions and peripheral devices used by the microcontroller through the authority management interface. For example, a higher authority will be set in the administrator mode, and a lower authority will be set in the user mode. Therefore, since the functions, functions and peripheral devices used by the microcontroller can independently set their permissions, the permission management execution system of this creation is suitable for various scenarios and applications. In addition to having high data protection capabilities, it also has a high degree of Operational flexibility.

100: Authority Management Execution System of Microcontroller 10: Microcontroller 11:Boot read-only memory 12:Summary Viewer PC: computer device 10U: User Mode Area 10A: Manager mode area 10U1: User Mode Application Module 10U2: User Mode Memory Module 10U3: User mode interrupt request module 10U4: User mode input/output module 10A1: Manager mode application module 10A2: Supervisor Mode Memory Module 10A3: Supervisor mode interrupt request module 10A4: Supervisor mode input/output module 10B: Specific file temporary register UI: permission management interface SRAM_N: general memory area SRAM_SEC: Secure memory interval SRAM_NA1: general memory area of the manager SRAM_NU1: User's general memory area SRAM_SECA1: Secure memory area of the manager SRAM_SECU1: user's security memory area W1 to W5: Windows S401 to S411: Steps S601 to S604: Steps

Fig. 1 is a block diagram of an embodiment of the authority management execution system of the microcontroller of the present invention. FIG. 2 is a schematic diagram of the configuration of the administrator mode and the user mode in the memory resources in the authority management execution system of the microcontroller in FIG. 1 . Figure 3 is a schematic diagram of the authority management interface in the authority management execution system of the microcontroller in Figure 1. Fig. 4 is a flow chart of executing the boot program in the authority management execution system of the microcontroller in Fig. 1. Fig. 5 is a schematic diagram of the matching between the boot ROM and the summary viewer in the authority management execution system of the microcontroller in Fig. 1. Fig. 6 is a flow chart of the authorization management method for operating the microcontroller in the authorization management execution system of the microcontroller in Fig. 1.

100: Authority Management Execution System of Microcontroller

10: Microcontroller

PC: computer device

10U: User Mode Area

10A: Manager mode area

10U1: User Mode Application Module

10U2: User Mode Memory Module

10U3: User mode interrupt request module

10U4: User mode input/output module

10A1: Manager mode application module

10A2: Supervisor Mode Memory Module

10A3: Supervisor mode interrupt request module

10A4: Supervisor mode input/output module

10B: Specific file temporary register

UI: permission management interface

Claims (10)

A permission management execution system for a microcontroller, comprising: A microcontroller, comprising: a user mode area, including: a user mode application module; a user mode memory module coupled to the user mode application module; a user mode interrupt request module coupled to the user mode memory module; and a user mode input/output module coupled to the user mode interrupt request module; and A manager mode area, including: A manager mode application module; a manager mode memory module coupled to the manager mode application module; a supervisor mode interrupt request module coupled to the supervisor mode memory module; and a supervisor mode input/output module coupled to the supervisor mode interrupt request module; and a computer device coupled to the microcontroller for setting the microcontroller; Wherein the computer device uses a development software kit to set the memory resources of the micro-controller to correspond to an administrator mode under the administrator mode area and a user mode under the user mode area through an authority management interface, the The computer device is set in the manager mode, and the set of peripheral devices and function sets in the manager mode application module are pointed to for use in the user mode through the memory resource, and in the user mode When using the set of peripheral devices and the set of functions, the set of peripheral devices and the set of functions cannot be changed. The system as described in claim 1, wherein the microcontroller is a sixteen-bit microcontroller, the computer device sets the microcontroller to obtain a group of interrupt vector resources, and the computer device uses the development software kit to obtain the set The interrupt vector resource points to the manager mode and the user mode, the computer device is authorized to use all the interrupt vector resources of the microcontroller in the manager mode, and the computer device plans the set of interrupts in the manager mode Among the vector resources, the interrupt vector resources that are authorized to be called in the user mode. The system as described in claim 1, wherein the computer device sets the microcontroller to obtain a special interrupt vector, and the computer device uses the special interrupt vector in the supervisor mode to enter the user after executing a function mode, and then enter the administrator mode from the user mode, use a special character string to write a special memory location, and if a subprogram call of the user mode is reserved in advance in the administrator mode, the use After the manager mode enters the manager mode and executes the subroutine call, it returns to the user mode. The system as described in Claim 1, wherein the computer device generates a mapping table, and according to the mapping table, corresponds to the output address and the input address in the memory resource, and the mapping table is generated by a plurality of random random numbers . The system as claimed in claim 4, wherein the random numbers are generated by a physical unclonable function (Physical Unclonable Function, PUF) source of random numbers. The system as described in claim 1, wherein the computer device is set with an administrator mode password, and when entering the administrator mode, the development software kit authenticates the administrator mode password to protect the set of peripheral devices set in the administrator mode The parameters and collection of the function. The system as described in claim 1, wherein the computer device allocates the general data of the administrator mode in a first memory section of the memory resource, and allocates the general data of the user mode in the memory resource In a second memory section of the memory resource, the security data of the administrator mode is allocated in a third memory section of the memory resource, and the security data of the user mode is allocated in a fourth memory section of the memory resource In the memory section, the first memory section, the second memory section, the third memory section and the fourth memory section do not overlap. The system as described in claim 1, wherein the computer device starts a secure boot, and checks whether a first hardware and a second hardware in the microcontroller match, if the first hardware and the second If the hardware matches, a verification of the secure boot is passed. The first hardware includes a boot read-only memory (Boot Read-Only Memory), and the second hardware includes a digest check (Digest Check) device. The system of claim 8, wherein the boot ROM and the digest detector use a string of predetermined bit length to check for a match. The system according to claim 1, wherein the administrator mode has higher management authority, and the user mode has lower management authority.

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