TWI833533B - Key management device, processor chip and method for avoid using incomplete keys - Google Patents

Abstract

A key management device for avoiding using incomplete keys is provided. The key management device comprises a static random access memory (SRAM), a register and a control circuit. The control circuit arranges a key lookup table in the SRAM or the register, wherein the key database stores one or more keys; wherein the control circuit executes: receiving a key creation instruction sent by a processor, wherein the key creation instruction includes a new key and corresponding metadata; when the new key has been stored in the key database, and the corresponding metadata of the new key has been added in the key lookup table, setting the activation bit corresponding to the new key is ON in the key lookup table; and reporting a key number corresponding to the new key.

Description

Key management devices, processor chips and methods that avoid using incomplete keys

The present disclosure relates to a key management device, a processor chip and a method, and in particular to a key management device, a processor chip and a method that avoid using incomplete keys.

In today's computer systems or control systems, it is often necessary to encrypt and decrypt data. However, the process of data decryption often requires gold keys or private keys. When the number of gold keys or private keys increases, key management and storage will also cause considerable trouble to users.

In addition, during the key creation process, if a system reset or other unknown reasons are encountered, the key creation process will be interrupted. This situation will prevent the key from being completely written. When the system needs to use this key, the encryption and decryption operations will fail because the system may be operating an incompletely created key, resulting in less than expected results and security risks and problems.

Therefore, there is a need for a key management device, a processor chip and a method that avoid using incomplete keys to ensure that all keys whose key creation process is interrupted cannot be used.

The following disclosure is illustrative only and is not intended to be limiting in any way. In addition to the illustrated aspects, embodiments, and features, other aspects, embodiments, and features will become apparent by reference to the accompanying drawings and the following detailed description. That is, the following disclosure is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected, but not all, embodiments are described in further detail below. Accordingly, the following disclosure is not intended to be essential features of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

Therefore, the main purpose of the present disclosure is to provide a key management device, a processor chip and a method that avoid using incomplete keys.

The present disclosure proposes a key management device that avoids the use of incomplete keys, including: a static random access memory; a temporary register; and a control circuit for storing in the static random access memory or the temporary storage The device is provided with a key lookup table and manages a key database, wherein the above-mentioned key database stores one or more keys; wherein, the above-mentioned control circuit performs the following steps: receiving a key sent by a processor. Key creation instruction, wherein the above-mentioned key creation instruction includes a new key and corresponding metadata; when the above-mentioned new key has been stored in the above-mentioned key database, and the corresponding metadata of the above-mentioned new key has been stored in the above-mentioned key After being added to the lookup table, set the activation bit corresponding to the new key in the key lookup table to an on state; and report a key number corresponding to the new key to the processor.

In some embodiments, the activation bit corresponding to the new key is in a closed state by default.

In some embodiments, the above-mentioned control circuit further executes: receiving a key read instruction, wherein the above-mentioned key read instruction is used to request to read a first key; when the above-mentioned first key is found in the above-mentioned key lookup table, After a first key number corresponding to the key is determined, whether a first activation bit corresponding to the first key is in an on state; when the first activation bit is in an on state, read from the key database Obtain the first key and send the first key to the processor; and when the first activation bit is in a closed state, report a read failure message to the processor.

In some embodiments, the above-mentioned control circuit further executes: receiving a key deletion instruction from the above-mentioned processor, wherein the above-mentioned key deletion instruction is used to delete a second key; according to the above-mentioned key deletion instruction from the above-mentioned key deletion instruction A second key number corresponding to the second key is deleted from the above-mentioned key database; and the second key corresponding to the above-mentioned second key number is set in the above-mentioned key lookup table. A second activation bit is in an off state.

In some embodiments, when the metadata corresponding to the new key or the key number cannot be added in the key lookup table, or the new key cannot be stored in the key database, an error occurs. 1. Interruption information, wherein the above-mentioned interruption information records the storage information of the above-mentioned new key.

The disclosure proposes a processor chip, including: a processor; a one-time programmable (OTP) memory; a flash memory; and a key management device electrically connected to the above-mentioned The processor, the above-mentioned OTP memory and the above-mentioned flash memory, the above-mentioned key management device includes: a static random access memory; a temporary register; and a control circuit for controlling the above-mentioned static random access memory or The above-mentioned temporary register sets a key lookup table and manages a key database, wherein the above-mentioned key database stores one or more keys; wherein, the above-mentioned control circuit receives a key transmitted by a processor Creation instruction, wherein the above-mentioned key creation instruction includes a new key and corresponding metadata; wherein, when the above-mentioned new key has been stored in the above-mentioned key database, and the corresponding metadata of the above-mentioned new key has been stored in the above-mentioned key database, After the key lookup table is added, the above-mentioned control circuit sets the corresponding activation bit of the above-mentioned new key in the above-mentioned key lookup table to an open state; and wherein the above-mentioned control circuit reports a key number corresponding to the above-mentioned new key. to the above processor.

The present disclosure proposes a method for avoiding the use of incomplete keys, which is used in a key management device, including: a control circuit setting a key lookup table in a static random access memory or a temporary register, and managing A key database, wherein the above-mentioned key database stores one or more keys; the above-mentioned control circuit receives a key creation instruction transmitted by a processor, wherein the above-mentioned key creation instruction includes a new key and corresponding metadata; when the above-mentioned new key has been stored in the above-mentioned key database, and the corresponding metadata of the above-mentioned new key has been added in the above-mentioned key lookup table, the above-mentioned control circuit will The activation bit corresponding to the new key is set to an on state in the key lookup table; and the control circuit reports a key number corresponding to the new key to the processor.

Aspects of the present disclosure will be described more fully below with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or functionality presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will appreciate that the scope of the disclosure is intended to encompass any aspect disclosed herein, whether implemented alone or in combination with any other aspect of the disclosure. For example, it can be implemented using any number of devices or execution methods proposed herein. In addition, in addition to the various aspects of the present disclosure set forth herein, the scope of the present disclosure is intended to include devices or methods implemented using other structures, functions, or structures and functions. It is understood that any aspect disclosed herein may be embodied by one or more elements of the claimed scope.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect of the disclosure or design described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects of the disclosure or design. Furthermore, like numbers refer to like elements throughout the several figures, and the articles "a", "an" and "the above" include plural references unless otherwise specified in the description.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

Figure 1 is a block diagram showing a control system 10 in an embodiment of the present disclosure.

As shown in FIG. 1 , the control system 10 includes a processor chip 110 , a dynamic random access memory (DRAM) 130 , a storage device 140 , a transmission interface 150 , and at least one peripheral device 160 . The processor chip 110 and the DRAM 130 are electrically connected to each other through the bus 21 . In some embodiments, the bus 21 is, for example, an Advanced High-Performance Bus (AHB). The transmission interface 150 and the peripheral device 160 can be electrically connected to the bus 22, for example, and the buses 21 and 22 communicate through a bridge 23, where the bus 22 can be, for example, an advanced system bus ( Advanced System Bus (ASB) or an Advanced Peripheral Bus (APB), but the disclosure is not limited thereto.

The processor chip 110 includes a central processing unit (or microprocessor) 111, volatile memory 112, flash memory 113, one-time programmable (OTP) Memory 114, a graphics The processing unit 120, a key management device 170 and an encryption and decryption device 180. The volatile memory 112 may be, for example, a static random access memory (Static Random Access Memory, SRAM). The flash memory 113 may be a NAND flash memory, for example. The one-time programmable memory 114, for example, can be called a programmable read-only memory (PROM), which can utilize a non-volatile memory with a lock bit (Lock Bit) register. , such as: flash memory, Erasable Programmable Read-only Memory (EPROM), or Electronically Erasable Programmable Read-only Memory (Electrically Erasable Programmable Read-only Memory, EEPROM).

For example, when the CPU 111 programs or writes data to the one-time programmable memory 114, the lock bit register of the one-time programmable memory 114 will be modified. For example, modifying the lock bit from 1 (indicating the unlocked state) to 0 (indicating the locked state) indicates that the data stored in the one-time programmable memory 114 cannot be modified, and the lock bit cannot be modified from 0 to 1. .

The graphics processing unit 120 may be, for example, a separate graphics processor or may be integrated into the central processing unit 111 . The memory unit 130 is a volatile memory, such as a dynamic random access memory (DRAM), but the disclosure is not limited thereto. The storage device 140 is a non-volatile memory (Non-volatile Memory). For example, it can be a Hard Disk Drive, a Solid-state Disk, a Flash Memory, or a Read-only Memory. However, the present invention It is not limited to this. In some embodiments, the storage device 140 may be electrically connected to the bus 22 , for example.

The storage device 140 can store one or more applications 141 and an operating system 142 (for example, it can be Windows, Linux, MacOS, or an embedded operating system (Embedded OS), etc.), and the processing unit 110 converts the operating system 142 and the application program 141 is read into the memory unit 130 and executed.

The transmission interface 150 may include one or more data transmission interfaces, such as a Universal Serial Bus (USB) interface, USB Type-C interface, Thunderbolt interface, general-purpose input and output (General-purpose Input) /Output, GPIO) interface, Universal Asynchronous Receiver/Transmitter (UART) interface, Serial Peripheral Interface (SPI) interface, Integrated Circuit Bus (inter-integrated circuit, I2C) interface , or combinations thereof, but the present disclosure is not limited thereto. The peripheral device 160 includes, for example, input devices such as a keyboard, a mouse, and a trackpad, but the disclosure is not limited thereto.

The key management device 170 may be, for example, a hardware circuit of an Intelligent Key Storage Device, which may be an application-specific integrated circuit (ASIC) or a programmable logic gate array. (Field Programmable Gate Array, FPGA) implemented. For example, the key management device 170 can perform related operations on different keys according to the control instructions of the processor chip 110, such as adding a key, reading a key, erasing (or revoking) one of the keys, erasing ( or abolish) all keys, etc., but the disclosure is not limited thereto.

In one embodiment, the key management device 170 includes a control circuit 171 , a bus wrapper 172 , a register 174 and a static random access memory (SRAM) 175 . The control circuit 171 is used to control various operations of the key, such as creating a key, reading a key, deleting a single key, deleting all keys, etc. For example, the bus envelope 172 may provide a conversion interface between signals of internal components of the key management device 170 and signals of the bus 21 . The temporary register 174 is a field used to record the key number of each key and the corresponding other metadata. The key information recorded in the temporary register 174 can also be called a key lookup table (Key Lookup Table). . In another embodiment, the control circuit 171 may set the key lookup table in the static random access memory 175 . The static random access memory 175 can be, for example, one of the storage spaces of the key database, which is used to store one or more keys. In some embodiments, the control circuit 171 backs up the key lookup table in the static random access memory 175 or flash memory (for example, the flash memory 113 in the processor chip 110 or the storage device 140 flash memory). The detailed operation of the key management device 170 will be described in the following embodiments.

The encryption and decryption device 180 is, for example, a hardware circuit that supports multiple encryption and decryption algorithms, and various encryption and decryption algorithms have corresponding hardware circuits in the encryption and decryption device 180 , such as Advanced Encryption Standard (AES) encryption. Decryption circuit 181, Keyed-hash Message Authentication Code (HMAC) encryption and decryption circuit 182, Elliptic Curve Cryptography (ECC) encryption and decryption circuit 183, RSA encryption and decryption circuit 184, random number generation (Random Number Generator) circuit 185, or a combination thereof, and can perform hardware acceleration for corresponding encryption and decryption algorithms respectively. The random number generation circuit 185 may be, for example, a pseudo-random number (Pseudorandom Number) generation circuit or a true random number generation circuit. In some embodiments, the key management device 170 and the encryption and decryption device 180 may be independent hardware circuits and may be disposed outside the processor chip 110 and electrically connected to the processor chip 110 through the bus 21 .

For example, in one embodiment, when the control system 10 is operating, different applications 141 may use different encryption and decryption algorithms to encrypt content to be encrypted (eg, user passwords). For example, various encryption and decryption circuits 181 to 185 provided in the encryption and decryption device 180 can be used. Different encryption and decryption algorithms use different key sizes, for example, from 64 bits to 4096 bits. After the encryption and decryption device 180 completes encrypting the content to be encrypted, the corresponding key (key) will be sent to the key management device 170 for key management.

The key management of the key management device 170 can be divided into several different operations, such as writing (adding) a key, reading a key, erasing (deleting) a single key, and erasing (deleting) all keys. For the operation of writing a key, the key management device 170 may, for example, receive the key and corresponding metadata (Metadata) from the processor chip 110 (or the encryption and decryption device 180), wherein the attributes of the metadata (Attribute) Fields may include, for example: Key Size, Owner, Security Level, Privilege Level, Readable attribute, Revoke attribute, Booting State, etc., but this The revelations don’t stop there. The contents of the various fields of metadata will be explained one by one below.

"Key size" can be represented by the number of bits used by the key, such as 80 bits, 128 bits, 256 bits, etc. Depending on the encryption and decryption algorithms used, the encryption and decryption device 180 may support a key size ranging from 64 bits to 4096 bits, for example. "Owner" means, for example, the owner of this key. Non-owners of this key cannot read this key. The owner of the key can be set according to requirements, and may include, for example: CPU (ie, processor chip 110), AES, HMAC, ECC, RSA, etc. For example, if the key owner field in the metadata of the key is AES, it means that the AES encryption and decryption circuit in the encryption and decryption device 180 can read this key.

"Security level" indicates the security level of the key, which can be divided into security (Secure) level and non-security (Non-secure) level, for example. Keys with a security level can only be used by owners with the same security level, while keys with a non-security level do not need to confirm the owner's security level. It should be noted that whether the security level attribute in the key metadata is effective depends on the design of the processor chip 110 . For example, the processor chip 110 can be classified as a secure processor or a non-secure processor, and when the processor chip 110 is a secure processor, the field setting of the security level in the metadata of the key can take effect. When the processor chip 110 is a non-secure processor, the security level field setting in the key's metadata does not take effect.

"Privilege level" indicates the privilege level of the key, which can be divided into privileged (Privilege) level and non-privilege (Non-privilege) level, for example. Keys with a privileged level can only be used by owners with the same privileged level, while keys with a non-privileged level do not need to confirm the owner's privileged level. For example, different users may have different permissions. Administrators or super users have the highest privilege level. For example, they can access keys that are set with a privilege level but do not have a privilege level. General users cannot access keys with a privileged level.

The "read attribute" indicates whether the key can be read by the processor chip 110. For example, if the owner field of this key is CPU, it means that this key must be readable by the processor chip 110. If the owner field of the key is another encryption and decryption circuit, the key management device 170 will determine whether the processor chip 110 can read the key based on the read attribute field of the key.

"Revocation attribute", this field is recorded in the internal register in the key management device 170, and the corresponding revocation attribute cannot be set when the key is created. For example, under normal usage conditions, the key management device 170 will set the value of the field of the key's revocation attribute to 0, indicating that the key is used normally. When the user performs a key deletion operation, the key management device 170 may delete the key stored in the flash memory or one-time programmable memory. However, the key stored in the flash memory or one-time programmable memory may not be truly deleted because the lock bit is set. Therefore, when the key management device 170 performs a key deletion operation, it will set the revocation attribute corresponding to the key to be deleted in its internal register. Once the corresponding revocation attribute of a key is set in the key management device 170, it cannot be modified, which means that the corresponding key cannot be restored to a usable state. At this time, no matter whether the conditions of other attributes are met or not, the key management device 170 cannot read or use the key that has been set with the revocation attribute, which means that the revocation attribute of the key has priority over other attributes.

The "power-on state" attribute indicates the power-on state in which the key can be used. For example, it can be divided into power-on state 1 (BL1) and power-on state 2 (BL2). For example, when the power-on state of the control system 10 is power-on state 1 (BL1), the key management device 170 may use a key with power-on state attributes of BL1 and BL2. When the power-on state of the control system 10 is power-on state 2 (BL2), the key management device 170 can only use keys with the power-on state attribute of BL2.

Figures 2A-2B are schematic diagrams of key creation operations to avoid using incomplete keys according to an embodiment of the present invention.

In one embodiment, when the user wants to create a new key in the key management device 170, the user can first fill in the contents of each field of the metadata of the key to be created, such as the key size, ownership user, security level, privilege level, read attributes, cancel attributes, power-on status, etc., and then fill in the content of the key. After filling in the above content required for the key, the user can start the key storage process (for example, by pressing a software button), and the key management device 170 will first determine the size of the key and the remaining space in the internal storage space. to determine whether the current key can be stored. If the internal storage space in the key management device 170 is smaller than the key size, the key management device 170 will report a read failure message to the processor 111 to notify the user. If the internal storage space in the key management device 170 is greater than or equal to the key size, the key management device 170 starts to create the key, and when the key is successfully created and stored, the key management device 170 will set the key corresponding The activation bit is in the on state, for example, set the activation bit from 0 to 1 (indicating the on state). Then, the key management device 170 will report a completion status to notify the user of the key number of the created key, as shown in Figure 2A. In one implementation, before the key is created and stored, the corresponding activation bit of the key is preset to the off state, for example, the activation bit is preset to 0 (indicating the off state).

In one embodiment, the key database of the key management device 170 can be divided into several storage spaces, such as flash memory, OTP memory and SRAM 175, where the flash memory can be in the processor chip 110. The flash memory 113 or the flash memory in the storage device 140 , the OTP memory can be the OTP memory 114 in the processor chip 110 or the OTP memory electrically connected to the bus 21 or 22 . A person with ordinary knowledge in the technical field of the present invention will understand that the flash memory and OTP memory in appropriate locations may be used depending on the actual design requirements to form a key database together with the SRAM 175, and this disclosure does not take this as an example. limit.

Following the above embodiment, when a system reset or other unknown reasons cause the key creation process to be interrupted, the key management device 170 will generate interruption information to record the storage information of the new key. In other words, when the corresponding metadata or the corresponding key number of the key to be created cannot be added in the key lookup table, or the key to be created cannot be stored in the key database, the key management device 170 can generate an interrupt message, wherein the interrupt message records the storage information of the key to be created. For example, the content of each field of the metadata of the key to be created that the user fills in, and the stage to which the key to be created is stored. To give another example, when an interruption occurs after the metadata corresponding to the key to be created has been added to the key lookup table, the key management device 170 will record the metadata of the key to be created filled in by the user. The contents of each field and the metadata corresponding to the key to be created have been stored in the key lookup table.

The user can view the above records through the key management device 170 to know which keys to be created have not been successfully created. When the user finds that a key has not been successfully created based on the above records, the user can restart the key storage process to re-save the key that has not been successfully created. In one embodiment, when the key management device 170 adds a key that has not been successfully created to the SRAM 175 last time, during the process of restarting the key storage process, the key management device 170 can add the key to the SRAM 175 . The key is re-added to the same location in SRAM 175 as the key that was not successfully created last time. In another embodiment, when the key management device 170 adds a key that has not been successfully created to the flash memory last time, during the process of restarting the key storage process, the key management device 170 This key is re-added to a different location in the flash memory than the key that was not successfully created last time.

As shown in Figure 2B, if two keys, such as key 00 and key 01, have been originally created in the key management device 170, and key 00 and key 01 are keys stored in the key management device 170, The key database 210 is stored in an OTP memory and a flash memory respectively, for example. The key numbers, corresponding metadata and corresponding activation bits of key 00 and key 01 are recorded in the register 174 of the key management device 170 . For ease of explanation, the meta-information takes the key size and owner as an example. It should be noted that the key database 210 is a collective system that includes a plurality of storage spaces for storing keys. For example, the key database 210 may include OTP memory, flash memory and SRAM 175, where the above-mentioned flash memory The memory can be the flash memory 113 in the processor chip 110 or the flash memory in the storage device 140. The OTP memory can be the OTP memory 114 in the processor chip 110 or be electrically connected to the bus. 21 or 22 OTP memory.

When the key management device 170 receives a key creation command and the corresponding key and meta-information (for example, the owner is AES and the key size is 512 bits) from the processor chip 110, the key management device 170, for example The key can be set to key 02, and key 02 is stored in the SRAM 175 in the key database. Then, the key management device 170 may update the plurality of fields and storage locations of the key lookup table in the register 174 regarding the key 02. After the above update operation is completed, the key management device 170 sets the corresponding activation bit of key 02 in the key lookup table to the on state, for example, sets the activation bit from 0 to 1 (indicating the on state). After the above-mentioned activation bit setting is completed, the key management device 170 can report a key creation completion information and a key number (ie, key number 02) to the processor chip 110 . For the user, he can only know the key number corresponding to the stored key, but he cannot know the storage location of the stored key. If the corresponding key needs to be read, the user only needs to transmit the key number of the key to be obtained to the key management device 170 through the processor chip 110 or the encryption and decryption circuits 181-185, and the key management device 170 After verifying the information of the read key and determining that the corresponding activation bit of the key to be obtained is in the on state, the read key can be reported to the processor chip 110 or the encryption and decryption circuits 181-185.

Figures 2C to 2D are schematic diagrams of key reading operations to avoid using incomplete keys according to an embodiment of the present invention.

In one embodiment, when the processor chip 110 or one of the encryption and decryption circuits 181 to 185 in the encryption and decryption device 180 wants to read one of the keys saved by the key management device 170, the key The management device 170 receives a key number of the key to be read from the encryption and decryption device 180 or the processor chip 110 . After the key management device 170 receives the key number from the encryption and decryption device 180 or the processor chip 110, the key management device 170 not only searches for the corresponding key from its key database, but also determines whether to read the key. Whether the corresponding activation bit of the key is on, for example, determine whether the activation bit is 1.

For example, if the activation bit of the key is not set to be on (that is, the activation bit is off or the activation bit is 0), the key management device 170 will determine that the key to be read has not been completely updated. Add to the key database and report read failure information to the component that wants to read the key. If the activation bit of the key has been set to the on state, the key management device 170 will perform subsequent steps of reading the key. For example, the key management device 170 further determines whether the component or user who wants to read the key meets the permissions or privileges recorded in the metadata of the key based on the metadata of the key, confirms whether the revoke attribute is set, and confirms the current Control whether the power-on state of the system 10 conforms to the power-on state attribute of the metadata of the key.

For example, please refer to Figure 2D. When the processor chip 110 wants to read the key with key number 00, the processor chip 110 sends the key number of the key to be read (ie, key number 00) to Key management device 170. The key management device 170 first searches for the corresponding activation bit of the key number 00 in the key lookup table in the temporary register 174, and confirms whether the corresponding activation bit of the key number 00 is in the on state. When the key management device 170 determines that the corresponding activation bit of key number 00 is in the on state, the key management device 170 continues to search for relevant meta-information about key number 00 in the key lookup table in the temporary register 174 , and confirm whether the processor chip 110 is the owner of key number 00. When the key management device 170 determines that the processor chip 110 is indeed the owner of key number 00, the key management device 170 will report the read completion information and the content of the key number 00 to the processor chip 110 .

Figures 2E to 2F are schematic diagrams of key deletion operations to avoid using incomplete keys according to an embodiment of the present invention.

In one embodiment, when the user believes that a specific key stored in the key management device 170 is no longer used, the user can issue an instruction to erase (or delete) a single key operation through the processor chip 110 and The key number to be erased is sent to the key management device 170 . When the key management device 170 determines that the delete key command is a qualified command issued by the processor chip 110, the key management device 170 can delete the key to be deleted from the corresponding storage space in the key database. , and sets the activation bit corresponding to the deleted key to the off state, and reports the successful deletion information to the processor chip 110, as shown in Figure 2E.

In detail, it is assumed that the key management device 170 has stored key 00, key 01 and key 02. When the key management device receives an instruction to erase (or delete) a single key operation from the processor chip 110 and After the key number 01 is to be erased, the key management device 170 will obtain the key number 01, the key size and the storage location of the key to be erased based on the key lookup table in the temporary register 174, and This is used to calculate the storage space and range occupied by the key. The control circuit 171 of the key management device 170 deletes all data in the above storage space, updates the key lookup table in the temporary register 174 and recalculates the remaining space of each storage space in the key database, and The activation bit corresponding to the deleted key number 01 is set to the off state (for example, the activation bit is set from 1 to 0), as shown in Figure 2F.

It should be noted that the maximum number of keys that the key management device 170 can store corresponds to the number of activated bits. Although the number of keys is taken as an example of three keys in Figures 2A to 2F, the present disclosure should not be limited thereto.

FIG. 3 is a schematic diagram of a new key creation process 300 for the key management device to avoid using incomplete keys according to an embodiment of the present invention.

In step S302, the key management device 170 enters the preparation state. For example, the key management device 170 will first be initialized after being powered on or reset. After the initialization is completed, it will enter the Ready Status to receive instructions for different key operations.

In step S304, the key management device 170 receives a key creation instruction, where the key creation instruction comes from, for example, the central processor 111.

In step S306, the key management device 170 checks the remaining space of the key database. For example, the key management device 170 can check the remaining space of different storage spaces in the key database, such as the remaining space of the SRAM 175, the flash memory 113, and the OTP memory 114.

In step S308, the key management device 170 determines whether the remaining space is greater than or equal to the key size. If yes, execute step S310. If not, execute step S318. In another embodiment, in step S308, the key management device 170 determines whether the remaining space is greater than or equal to the key size and determines whether the key database has reached the upper limit of the number of key storage. If the remaining space is greater than or equal to the key size and the key database does not reach the upper limit of key storage quantity, step S310 is executed. If the remaining space is less than the key size or the key database has reached the upper limit of key storage quantity, step S320 is executed.

In step S310, the key management device 170 writes the metadata of the key into the key lookup table. The attributes of the metadata of the new key written by the key management device 170 into the key lookup table include: key size, owner, security level, privilege level, read attribute, power-on status and storage location.

In step S312, the key management device 170 adds the key number of the new key to the key lookup table. For example, the control circuit 171 of the key management device 170 can search for an unused key number incrementally from number 0, and can use the smallest unused key number as the key number of the new key.

In step S314, the key management device 170 writes the new key into the key database. For example, the key management device 170 may store the new key in the OTP memory in the key database according to the security level or privilege level that has been set in the metadata of the new key. If the security level or privilege level in the metadata of the new key is not set, the key management device 170 can store the new key in the SRAM 175 or flash memory 113 in the key database.

In step S316, the key management device 170 sets the corresponding activation bit of the new key in the key lookup table to an on state, indicating that the new key has been completely stored in the key database. In one embodiment, the corresponding activation bit of the new key is in the off state and can be represented by the value 0; and the corresponding activation bit of the new key is in the on state and can be represented by the value 1.

In step S318, the key management device 170 reports the key number and writing completion information to the central processor 111.

In step S320, the key management device 170 reports a writing failure message to the central processor 111.

In step S322, the key creation instruction is completed, and the process returns to step S302.

Figure 4 is a schematic diagram of a new key reading process 400 for the key management device to avoid using incomplete keys according to an embodiment of the present invention.

In step S402, the key management device 170 enters the preparation state. For example, the key management device 170 will first be initialized after being powered on or reset. After the initialization is completed, it will enter the Ready Status to receive instructions for different key operations.

In step S404, the key management device 170 receives a key read instruction, where the key read instruction comes from, for example, the processor chip 110 or one of the encryption and decryption circuits 181 to 185 in the encryption and decryption device 180. , and used to request reading of a first key.

In step S406, the key management device 170 determines whether a first key number corresponding to the first key in the key read instruction can be found in the key lookup table. If yes, execute step S408. If not, execute step S418.

In step S408, the key management device 170 determines whether a first activation bit corresponding to the first key is in an open state. If yes, execute step S410. If not, execute step S418.

In step S410, the key management device 170 further determines whether the component or user who wants to read the first key meets the permissions or privileges recorded in the metadata of the first key based on the metadata of the first key. If yes, execute step S412. If not, execute step S418.

In step S412, the key management device 170 reads the first key from the key database.

In step S414, the key management device 170 sends the first key to the component that wants to read the key.

In step S416, the key management device 170 reports a reading completion message to the central processor 111.

In step S418, the key management device 170 reports a writing failure message to the central processor 111.

In step S420, the key reading instruction is completed, and the process returns to step S402.

In one embodiment, when the key management device 170 is interrupted in reading the first key from the key database in step S412, the key management device 170 will record the first key corresponding to the first key. The key number allows the user to check which key the key management device 170 was interrupted in the process of reading.

In summary, the present disclosure provides a key management device, a processor chip and a method to avoid using incomplete keys, which add a new set of activation bits. It is in the open state when the key is created and stored successfully, and returns to the closed state when the key is deleted. Thereby, the key management device can determine whether the key is complete and has been activated by reading the activation bit status. Therefore, even if an interruption occurs during the key creation process, as long as the key creation is not successful, the activation bits of the key can be ensured to be in a closed state. This can also avoid the risk of using incomplete keys and increase the financial risk. Security of key management.

Any specific sequence or layering of steps in the process disclosed herein is provided by way of example only. Based on design preferences, it is understood that any specific order or hierarchy of steps in the process may be rearranged within the scope disclosed in this document. The accompanying method claims present elements of the various steps in a sample order and therefore should not be limited to the specific order or hierarchy presented.

The use of "first", "second", "third" and other ordinal numbers used to modify elements in the scope of the patent application itself does not imply any priority, priority, sequence between elements, or method execution. The order of the steps is only used as an identifier to distinguish different components with the same name (with different ordinal numbers).

Although this disclosure has been disclosed above with implementation examples, it is not intended to limit this case. Anyone familiar with this technology can make some changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this case should be The scope of the patent application shall be determined by the attached patent application.

10:Control system 21:Bus 22:Bus 23:Bridge 110: Processor chip 111:CPU 112: Volatile memory 113: Flash memory 114:OTP memory 120: Graphics processor 130:Dynamic Random Access Memory 140:Storage device 141:Application 142:Operating system 150:Transmission interface 160:Peripheral devices 170:Key management device 171:Control circuit 172:Bus Envelope 174: Temporary register 175: Static random access memory 180: Encryption and decryption device 181:AES encryption and decryption circuit 182:HMAC encryption and decryption circuit 183:ECC encryption and decryption circuit 184:RSA encryption and decryption circuit 185: Random number generation circuit 186:Bus Envelope 188: Internal bus 210:Key database 300:Process S302, S304, S306, S308, S310, S312, S314, S316, S318, S320, S322: Steps 400:Process S402, S404, S406, S408, S410, S412, S414, S416, S418, S420: Steps

Figure 1 is a block diagram showing a control system in an embodiment of the present disclosure. Figures 2A-2B are schematic diagrams of key creation operations to avoid using incomplete keys according to an embodiment of the present invention. Figures 2C to 2D are schematic diagrams of key reading operations to avoid using incomplete keys according to an embodiment of the present invention. Figures 2E to 2F are schematic diagrams of key deletion operations to avoid using incomplete keys according to an embodiment of the present invention. Figure 3 is a schematic diagram of a process of creating a new key by the key management device to avoid using incomplete keys according to an embodiment of the present invention. Figure 4 is a schematic diagram of the process of reading a new key by the key management device to avoid using incomplete keys according to an embodiment of the present invention.

300:Process

S302, S304, S306, S308, S310, S312, S314, S316, S318, S320, S322: Steps

Claims (10)

A key management device that avoids the use of incomplete keys, including: a static random access memory; a scratchpad; and A control circuit for setting a key lookup table in the above-mentioned static random access memory or the above-mentioned temporary register, and managing a key database, wherein the above-mentioned key database stores one or more keys; Among them, the above control circuit performs the following steps: Receive a key creation instruction sent by a processor, wherein the key creation instruction includes a new key and corresponding metadata; When the above-mentioned new key has been stored in the above-mentioned key database, and the metadata corresponding to the above-mentioned new key has been added in the above-mentioned key lookup table, the above-mentioned new key corresponding to the above-mentioned key lookup table is set. The activation bit is on; and Return a key number corresponding to the above-mentioned new key to the above-mentioned processor. A key management device for avoiding the use of incomplete keys as claimed in claim 1, wherein the activation bit corresponding to the new key is in a closed state by default. As claimed in claim 1, the key management device avoids using incomplete keys, wherein the above control circuit further executes: Receive a key read command, wherein the key read command is used to request to read a first key; After finding a first key number corresponding to the above-mentioned first key in the above-mentioned key lookup table, determine whether a first activation bit corresponding to the above-mentioned first key is in an open state; When the first activation bit is in the on state, read the first key from the key database and transmit the first key to the processor; and When the first activation bit is in the off state, a read failure message is reported to the processor. As claimed in claim 1, the key management device avoids using incomplete keys, wherein the above control circuit further executes: Receive a key deletion instruction from the above-mentioned processor, wherein the above-mentioned key deletion instruction is used to delete a second key; Delete the second key with the second key number from the key database based on a second key number corresponding to the second key from the key deletion command; and A second activation bit corresponding to the second key in the key lookup table is set to an off state. A processor chip including: a processor; One-time Programmable (OTP) Memory; a flash memory; and A key management device electrically connected to the above-mentioned processor, the above-mentioned OTP memory and the above-mentioned flash memory. The above-mentioned key management device includes: a static random access memory; a scratchpad; and A control circuit for setting a key lookup table in the above-mentioned static random access memory or the above-mentioned temporary register, and managing a key database, wherein the above-mentioned key database stores one or more keys; Wherein, the above-mentioned control circuit receives a key creation instruction sent by a processor, wherein the above-mentioned key creation instruction includes a new key and corresponding metadata; Among them, when the above-mentioned new key has been stored in the above-mentioned key database, and the metadata corresponding to the above-mentioned new key has been added in the above-mentioned key lookup table, the above-mentioned control circuit is set in the above-mentioned key lookup table. The corresponding activation bit of the above new key is turned on; and The control circuit reports a key number corresponding to the new key to the processor. Such as the processor chip of claim 5, wherein the above control circuit further executes: Receive a key read command, wherein the key read command is used to request to read a first key; After finding a first key number corresponding to the above-mentioned first key in the above-mentioned key lookup table, determine whether a first activation bit corresponding to the above-mentioned first key is in an open state; When the first activation bit is in the on state, read the first key from the key database and transmit the first key to the processor; and When the first activation bit is in the off state, a read failure message is reported to the processor. For example, the processor chip of request item 5, wherein the metadata corresponding to the above-mentioned new key or the above-mentioned key number cannot be added in the above-mentioned key lookup table, or the above-mentioned new key cannot be stored in the above-mentioned key data. When accessing the database, an interrupt message is generated, wherein the interrupt message records the storage information of the new key. A method to avoid using incomplete keys, used in a key management device, including: A control circuit sets a key lookup table in a static random access memory or a temporary register, and manages a key database, wherein the above-mentioned key database stores one or more keys; The control circuit receives a key creation instruction sent by a processor, wherein the key creation instruction includes a new key and corresponding metadata; When the above new key has been stored in the above key database and the metadata corresponding to the above new key has been added in the above key lookup table, the above control circuit sets the above in the above key lookup table. The corresponding activation bit of the new key is turned on; and The control circuit reports a key number corresponding to the new key to the processor. For example, in Request 8, methods to avoid using incomplete keys, the above methods include: The control circuit receives a key deletion instruction from the processor, wherein the key deletion instruction is used to delete a second key; The control circuit deletes the second key with the second key number from the key database based on a second key number corresponding to the second key from the key deletion command; and The control circuit sets a second activation bit corresponding to the second key in the key lookup table to a closed state. Such as the method of avoiding the use of incomplete keys in request item 8, when the metadata corresponding to the above-mentioned new key or the above-mentioned key number cannot be added in the above-mentioned key lookup table, or the above-mentioned new key cannot be stored When reaching the above-mentioned key database, the above-mentioned control circuit generates an interrupt information, wherein the above-mentioned interrupt information records the storage information of the above-mentioned new key.

Images