TWM634692U - Junction substrate - Google Patents
Junction substrate Download PDFInfo
- Publication number
- TWM634692U TWM634692U TW111209381U TW111209381U TWM634692U TW M634692 U TWM634692 U TW M634692U TW 111209381 U TW111209381 U TW 111209381U TW 111209381 U TW111209381 U TW 111209381U TW M634692 U TWM634692 U TW M634692U
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- single crystal
- substrate
- bonding
- crystal template
- Prior art date
Links
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
本創作公開一種接合基板。接合基板包括一支撐基板與一單晶層。支撐基板包括基底、磊晶層以及界面反應層。磊晶層位於基底與界面反應層之間,且界面反應層與磊晶層相互鍵結接合。單晶層連接於支撐基板。單晶層的材料與磊晶層的材料相同,且單晶層通過界面反應層連接於磊晶層。The invention discloses a bonded substrate. The bonding substrate includes a supporting substrate and a single crystal layer. The supporting substrate includes a base, an epitaxial layer and an interface reaction layer. The epitaxial layer is located between the substrate and the interface reaction layer, and the interface reaction layer and the epitaxial layer are bonded to each other. The single crystal layer is connected to the support substrate. The material of the single crystal layer is the same as that of the epitaxial layer, and the single crystal layer is connected to the epitaxial layer through the interface reaction layer.
Description
本創作涉及一種接合基板,特別是涉及一種用於製作元件的接合基板。The invention relates to a bonding substrate, in particular to a bonding substrate for making components.
目前在製作高功率元件、高射頻元件或發光二極體等元件時,常使用氮化鎵、碳化矽等半導體材料。為了能夠大量生產以降低製造成本,需要將元件成長在大尺寸(如:8吋或12吋)的基板上。相較於矽晶圓來說,目前製作大尺寸的氮化鎵基板或是碳化矽基板仍有相當高的難度,且成本高昂。以成長氮化鎵為例,目前是通過有機金屬化學氣相沉積(MOCVD)將氮化鎵磊晶層成長在大尺寸的矽晶圓上,再於氮化鎵磊晶層上製作元件。At present, semiconductor materials such as gallium nitride and silicon carbide are often used in the production of components such as high-power components, high-frequency components, or light-emitting diodes. In order to be able to mass-produce and reduce manufacturing costs, devices need to be grown on large-size (eg, 8-inch or 12-inch) substrates. Compared with silicon wafers, it is still quite difficult and expensive to manufacture large-sized GaN substrates or SiC substrates. Taking the growth of gallium nitride as an example, currently the gallium nitride epitaxial layer is grown on a large-sized silicon wafer by metal organic chemical vapor deposition (MOCVD), and then components are fabricated on the gallium nitride epitaxial layer.
由於氮化鎵與矽兩者的晶格不匹配,因此在沉積氮化鎵磊晶層之前,需要先在矽晶圓上形成緩衝層。然而,在形成緩衝層的初始階段,在矽晶圓表面很容易會形成非晶氧化矽或是非晶氮化矽。在初始階段所形成的緩衝層因成長在非晶材料上,而具有較差的結晶品質。據此,緩衝層通常需要被成長到具有特定的厚度,才能確保其結晶品質足以用來成長氮化鎵磊晶層。通過前述方式所形成的氮化鎵與緩衝層的總厚度通常較厚(約8至10微米),這會增加矽晶圓與氮化鎵之間的內應力。Due to the lattice mismatch between GaN and Si, it is necessary to form a buffer layer on the Si wafer before depositing the GaN epitaxial layer. However, in the initial stage of forming the buffer layer, amorphous silicon oxide or amorphous silicon nitride is easily formed on the surface of the silicon wafer. The buffer layer formed in the initial stage has poor crystalline quality due to growth on the amorphous material. Accordingly, the buffer layer usually needs to be grown to a specific thickness to ensure that its crystalline quality is sufficient for growing the GaN epitaxial layer. The total thickness of the GaN and the buffer layer formed by the aforementioned method is generally thick (about 8 to 10 microns), which will increase the internal stress between the silicon wafer and the GaN.
另外,利用有機金屬化學氣相沉積來成長氮化鎵的製程溫度很高,約1100 oC,且矽晶圓與緩衝層以及與氮化鎵之間因熱膨脹係數差異而產生內應力,導致矽晶圓變形或翹曲(warpage)。在後續形成元件製程中,可用的面積會縮減,且導致元件的良率降低。 In addition, the process temperature for growing gallium nitride by metalorganic chemical vapor deposition is very high, about 1100 o C, and the internal stress is generated between the silicon wafer and the buffer layer and the gallium nitride due to the difference in thermal expansion coefficient, resulting in silicon Wafer deformation or warpage. In the subsequent process of forming devices, the available area will be reduced, and the yield rate of devices will be reduced.
本創作所要解決的技術問題在於,針對現有技術的不足提供一種接合基板,其被應用於製作元件,且可降低製造成本。The technical problem to be solved by the invention is to provide a bonding substrate which is applied to manufacture components and can reduce the manufacturing cost.
為了解決上述的技術問題,本創作所採用的另外一技術方案是提供一種接合基板,其包括:提供多個單晶模板;提供一支撐基板,其中,所述支撐基板包括一基底、一接合層以及一磊晶層,所述磊晶層位於所述基底與所述接合層之間,所述磊晶層與多個所述單晶模板的材料相同;以及接合多個所述單晶模板與所述支撐基板,其中,每一所述單晶模板連接於所述接合層,且多個所述單晶模板相互拼接而共同形成一拼接式單晶模板,所述接合層與所述拼接式單晶模板以及所述磊晶層產生合金反應,而形成一界面反應層,且所述界面反應層與所述拼接式單晶模板以及所述磊晶層相互鍵結。In order to solve the above technical problems, another technical solution adopted in this creation is to provide a bonding substrate, which includes: providing a plurality of single crystal templates; providing a supporting substrate, wherein the supporting substrate includes a base, a bonding layer and an epitaxial layer, the epitaxial layer is located between the substrate and the bonding layer, the epitaxial layer is made of the same material as the plurality of single crystal templates; and bonding the plurality of single crystal templates with The supporting substrate, wherein each of the single crystal templates is connected to the bonding layer, and a plurality of the single crystal templates are spliced together to form a spliced single crystal template, and the bonding layer and the spliced The single crystal template and the epitaxial layer generate an alloy reaction to form an interface reaction layer, and the interface reaction layer is bonded to the spliced single crystal template and the epitaxial layer.
為了解決上述的技術問題,本創作所採用的另外一技術方案是提供一種接合基板,其包括:支撐基板以及單晶層。支撐基板包括基底、磊晶層以及界面反應層。磊晶層位於基底與界面反應層之間,界面反應層與磊晶層相互鍵結接合。單晶層連接於支撐基板,其中,單晶層的材料與磊晶層的材料相同,且單晶層通過界面反應層連接於磊晶層。In order to solve the above technical problems, another technical solution adopted in the present invention is to provide a bonding substrate, which includes: a supporting substrate and a single crystal layer. The supporting substrate includes a base, an epitaxial layer and an interface reaction layer. The epitaxial layer is located between the substrate and the interface reaction layer, and the interface reaction layer and the epitaxial layer are bonded to each other. The single crystal layer is connected to the supporting substrate, wherein the material of the single crystal layer is the same as that of the epitaxial layer, and the single crystal layer is connected to the epitaxial layer through the interface reaction layer.
本創作的其中一有益效果在於,本創作所提供的接合基板,其能通過“支撐基板包括基底、接合層以及磊晶層,磊晶層位於基底與接合層之間,且磊晶層與單晶模板的材料相同”的技術方案,來降低製造成本,並可在製作大尺寸的接合基板時,避免接合基板翹曲變形。One of the beneficial effects of this creation is that the joint substrate provided by this creation can pass through "the support substrate includes a base, a joint layer and an epitaxial layer, the epitaxial layer is located between the base and the joint layer, and the epitaxial layer and the single The technical solution of using the same material as the crystal template can reduce the manufacturing cost, and can avoid warping and deformation of the bonding substrate when making a large-sized bonding substrate.
為使能更進一步瞭解本創作的特徵及技術內容,請參閱以下有關本創作的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本創作加以限制。In order to further understand the characteristics and technical content of this creation, please refer to the following detailed description and drawings about this creation. However, the provided drawings are only for reference and explanation, and are not used to limit this creation.
以下是通過特定的具體實施例來說明本創作所公開有關“接合基板”的實施方式,本領域技術人員可由本說明書所公開的內容瞭解本創作的優點與效果。本創作可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不背離本創作的構思下進行各種修改與變更。另外,本創作的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本創作的相關技術內容,但所公開的內容並非用以限制本創作的保護範圍。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。The following is an illustration of the implementation of the "bonded substrate" disclosed in this creation through specific specific examples. Those skilled in the art can understand the advantages and effects of this creation from the content disclosed in this specification. This creation can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the idea of this creation. In addition, the drawings of this creation are only for simple illustration, not according to the actual size of the depiction, prior statement. The following embodiments will further describe the relevant technical content of this creation in detail, but the disclosed content is not intended to limit the protection scope of this creation. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.
[第一實施例][first embodiment]
參閱圖1,其為本創作第一實施例的接合基板的製造方法的流程圖。請參照圖1的步驟S10,在步驟S10中,提供單晶模板。請參照圖2至圖4,進一步說明提供單晶模板的詳細流程。Referring to FIG. 1 , it is a flowchart of a method for manufacturing a bonded substrate according to a first embodiment of the present invention. Please refer to step S10 in FIG. 1 , in step S10 , a single crystal template is provided. Please refer to FIG. 2 to FIG. 4 to further illustrate the detailed process of providing a single crystal template.
如圖2所示,將單晶模板10形成於成長基板GS上。成長基板GS可以選擇與所要形成的單晶模板10具有較高晶格匹配度的材料。進一步而言,成長基板GS的材料與單晶模板10之間晶格失配度小於0.2%,可使單晶模板10有較好的磊晶品質。在本創作實施例中,單晶模板10的材料為氮化鎵,成長基板GS可以是藍寶石基板或是碳化矽基板。As shown in FIG. 2 , a
在一實施例中,可以通過氫化物氣相磊晶法(Hydride vapor phase epitaxy, HVPE)將單晶模板10形成於成長基板GS上。利用氫化物氣相磊晶法可形成厚度較厚的單晶模板10。在本實施例中,單晶模板10的厚度範圍可由50 μm至1 mm。另外,利用氫化物氣相磊晶法來製作氮化鎵單晶模板10的製程溫度約800
oC至900
oC。也就是說,相較於有機金屬化學氣相沉積法,利用氫化物氣相磊晶法來製作氮化鎵單晶模板10的製程溫度較低。
In one embodiment, the
請參照圖3以及圖4,將成長基板GS與單晶模板10分離。在本實施例中,可執行雷射剝離製程(laser lift-off process),使單晶模板10與成長基板GS分離。如圖3與圖4所示,通過將雷射光L聚焦在單晶模板10與成長基板GS的界面,使單晶模板10可由成長基板GS被剝離(debonded)。在一實施例中,可以利用氟氪(KrF)準分子雷射所產生的雷射光(波長約248 nm),來執行雷射剝離製程。由於單晶模板10的厚度較大而具有足夠的機械強度,在分離單晶模板10與成長基板GS之後,單晶模板10可以作為獨立式基板(freestanding substrate)。Referring to FIG. 3 and FIG. 4 , the growth substrate GS is separated from the
請再參照圖1的步驟S11,在步驟S11中,提供支撐基板。須說明的是,在本實施例的製造方法中,步驟S10與步驟S11可以個別執行。請參照圖5至圖7,進一步說明提供支撐基板的詳細流程。Please refer to step S11 of FIG. 1 again. In step S11 , a supporting substrate is provided. It should be noted that, in the manufacturing method of this embodiment, step S10 and step S11 can be performed separately. Please refer to FIG. 5 to FIG. 7 to further illustrate the detailed process of providing the supporting substrate.
如圖5所示,將緩衝層21形成於一基底20上。基底20的材料可以選擇容易製作成大尺寸、成本較低的材料。由於支撐基板2在後續製程中也可能需要被加熱到高溫,因此基底20較佳是選擇可耐高溫的材料,可以是化合物半導體或者陶瓷,例如:碳化矽(SiC)、矽(Si)、氮化鋁(AlN)、氧化鋁(Al
2O
3)或氧化鎵(Ga
2O
3)。在本實施例中,基底20的磊晶面的面積會與成長基板GS的磊晶面的面積相同,但本創作不以此為限。在另一實施例中,基底20的尺寸也可以大於成長基板GS的尺寸。舉例而言,基底20可以選擇8吋或12吋的晶圓,而成長基板GS可選擇4吋或6吋的晶圓。
As shown in FIG. 5 , the
緩衝層21的材料可以根據後續要在基底20上磊晶成長的材料來決定。在一實施例中,後續要在基底20上形成氮化鎵磊晶層,因此緩衝層21的材料可以選擇與基底20的晶格常數以及與氮化鎵的晶格常數匹配的材料,如:氮化鋁。在本創作實施例中,緩衝層21的厚度至少500nm。當基底20與緩衝層21的晶格常數差異較大時,也可以增加緩衝層21的厚度。The material of the
如圖6所示,形成磊晶層22於緩衝層21上,且磊晶層22的材料與單晶模板10的材料相同。在一實施例中,磊晶層22的材料與單晶模板10的材料都是氮化鎵。需說明的是,在現有的磊晶製程中,通常採用有機金屬氣相沉積來形成高結晶品質的磊晶層,但因製程溫度(約1100
oC)較高以及磊晶層與基底之間的熱膨脹係數差異,很容易翹曲變形。特別是在大尺寸的基底20上於高溫製程形成磊晶層時,翹曲變形的問題會越嚴重。
As shown in FIG. 6 , an
相較之下,在本創作實施例中,克服並不要求磊晶層22需要具有良好的結晶品質。也就是說,磊晶層22可以是非晶或是多晶,且可以利用相對較低溫的製程來製作,以盡可能降低翹曲或變形的程度。舉例而言,磊晶層22可以通過濺鍍製程而形成在緩衝層21上,其製程溫度只有500
oC~700
oC。
In contrast, in the inventive embodiment, overcoming does not require the
請繼續參照圖7,在磊晶層22上形成一接合層23A。在一實施例中,磊晶層22的材料所含的元素中的其中一者與接合層23A的材料的元素為同族元素。進一步而言,當磊晶層22的材料為IIIA族元素的氮化物時,接合層23A的材料可為IIIA族金屬或含有IIIA族金屬的合金。舉例而言,磊晶層22的材料為氮化鎵,接合層23A的材料可以是鋁金屬、銦金屬、鉈金屬或含有前述金屬的合金。需說明的是,接合層23A的厚度範圍可由5 nm至10 nm,以在後續步驟中被完全反應成另一種材料。接合層23A與磊晶層22之間形成一接合界面231。通過執行圖5至圖7的流程之後,可以形成支撐基板2。Please continue to refer to FIG. 7 , a
請參照圖1的步驟S12,在步驟S12中,接合單晶模板與支撐基板。請配合參照圖8與圖9,單晶模板10可設置在接合層23A的接合表面232上。在本實施例中,單晶模板10的尺寸與基底20的尺寸大致相同。據此,當單晶模板10設置在接合層23A上時,單晶模板10完全覆蓋接合層23A的接合表面232。此時,單晶模板10並沒有與接合層23A之間產生鍵結。Please refer to step S12 of FIG. 1 , in step S12 , the single crystal template and the supporting substrate are bonded. Please refer to FIG. 8 and FIG. 9 together, the
請參照圖10,在接合單晶模板10與支撐基板2的步驟中,可通過加熱單晶模板10與支撐基板2,使接合層23A與單晶模板10以及與磊晶層22產生合金反應,從而使單晶模板10可被固著在支撐基板2上。Referring to FIG. 10 , in the step of bonding the
在一實施例中,壓合單晶模板10與支撐基板2,並將單晶模板10連同支撐基板2一起加熱到一預定反應溫度並持溫一預定反應時間,直至接合層23A完全被反應。可以利用加熱器3,在氮氣氛或者氧氣氛下,對單晶模板10與支撐基板2加熱。前述的預定反應溫度可根據接合層23A的材料而決定,但不超過1200
oC,較佳是600
oC至1000
oC,以減少翹曲變形。當單晶模板10與磊晶層22的材料都為氮化鎵,且接合層23A的材料為鋁層時,預定反應溫度至少800
oC,且至少持溫1小時,但本創作不以此例為限。
In one embodiment, the
請配合參照圖11,接合層23A被完全反應之後,形成一界面反應層23。界面反應層23會與單晶模板10以及與磊晶層22都產生鍵結,從而使單晶模板10可被接合在支撐基板2上。Please refer to FIG. 11 , after the
在一實施例中,以單晶模板10與磊晶層22的材料都為氮化鎵,且接合層23A的材料為鋁舉例說明。在氮氣氛下進行加熱後,單晶模板10或者磊晶層22中的鎵原子擴散到接合層23A內,且接合層23A內的鋁原子與鎵原子與氮原子反應。另一方面,接合層23A內的鋁原子也可擴散到磊晶層22或單晶模板10內,而取代鎵原子,而與磊晶層22或單晶模板10的氮原子產生穩定的化學鍵結。因此在接合層23A產生合金反應後所形成的界面反應層23的材料為氮化鋁鎵。In one embodiment, the material of the
在另一實施例中,當接合層23A的材料為銦時,界面反應層23的材料為氮化銦鎵。在又一實施例中,當接合層23A的材料為銦鋁合金時,界面反應層23的材料為氮化鋁銦鎵。也就是說,在執行接合步驟(S12)之後,連接於磊晶層22與單晶模板10之間的材料會由金屬(接合層23A)轉變為III-V化合物半導體(界面反應層23)。因此,界面反應層23與磊晶層22之間或是與單晶模板10的之間的晶格常數差異較小,可以增加界面反應層23與磊晶層22之間的結合力,以及界面反應層23與單晶模板10之間的結合力。另外,界面反應層23與磊晶層22以及與單晶模板10之間的熱膨脹係數的差異都較小,也可以減少內應力。In another embodiment, when the
在將單晶模板10與支撐基板2接合之後,即可形成接合基板,並可利用單晶模板10來成長元件層。然而,請再參照圖1,為了可重複使用單晶模板10,本創作實施例的製造方法還可進一步包括步驟S13與步驟S14。After the
在步驟S13中,切割單晶模板,以將單晶模板分離成第一部分與第二部分,第一部分在支撐基板上形成單晶層。在步驟S14中,拋光單晶層的表面。請參照圖12,在本實施例中,單晶模板10被橫向切割,以被分離成兩個部分。在一實施例中,可執行雷射剝離製程(laser lift-off process),來橫向切割單晶模板10。In step S13 , the single crystal template is cut to separate the single crystal template into a first part and a second part, and the first part forms a single crystal layer on the supporting substrate. In step S14, the surface of the single crystal layer is polished. Referring to FIG. 12 , in this embodiment, the
請參照圖13,將單晶模板10的第二部分10B剝離,而在支撐基板2上留下第一部分,而形成單晶層10A。值得注意的是,第一部分 (單晶層10A)的厚度小於第二部分10B的厚度。在一實施例中,第一部分 (單晶層10A)的厚度與單晶模板10的總厚度之間的比值為1至1000。舉例而言,當單晶模板10的總厚度為1 mm時,單晶層10A約只有1μm。在拋光單晶層10A的表面10s之後,接合基板Z1的單晶層10A的表面10s就可用於磊晶成長元件,如:發光二極體、高功率元件或是射頻元件。在一實施例中,可以通過化學機械研磨,將單晶層10A的表面10s拋光到具有極低表面粗糙度。Referring to FIG. 13 , the
值得一提的是,本創作實施例的製造方法還可進一步包括:接合單晶模板10的第二部分10B與另一支撐基板2。須說明的是,在第二部分10B與另一支撐基板2接合之前,第二部分10B的表面可以先被拋光,以增加第二部分10B與另一支撐基板2之間的結合力。It is worth mentioning that the manufacturing method of the present invention may further include: bonding the
換句話說,單晶模板10的第二部分10B在被剝離之後,還可以再用來與另一個支撐基板2接合,以製造另一個接合基板Z1。據此,本創作實施例的製造方法所製作的單晶模板10可被重複地使用,以大量製造用來成長元件的接合基板Z1,可以降低元件的製造成本。In other words, after being peeled off, the
如圖13所示,通過本創作第一實施例所提供的製造方法,可以製作用來成長元件的接合基板Z1。接合基板Z1包括支撐基板2以及單晶層10A。支撐基板2可包括基底20、緩衝層21、磊晶層22以及界面反應層23。As shown in FIG. 13 , through the manufacturing method provided by the first embodiment of the present invention, a bonding substrate Z1 for growing components can be manufactured. The bonding substrate Z1 includes the supporting
基底20的材料為矽、碳化矽、氮化鋁、氧化鎵或氧化鋁。緩衝層21位於基底20與磊晶層22之間,可減少基底20與磊晶層22之間因晶格常數與熱膨脹係數差異而產生的內應力。在本實施例中,磊晶層22可通過相對低溫且成本較低的濺鍍製程來製作。因此,磊晶層22可以是非晶或是多晶的濺鍍磊晶層。The material of the
界面反應層23與磊晶層22以及單晶層10A之間都會形成化學鍵結,使單晶層10A可連接於磊晶層22。單晶層10A與磊晶層22的材料可以是第一元素的氮化物,而界面反應層23的材料可包含第一元素的氮化物或氧化物與第二元素的氮化物或氧化物,且第二元素是第一元素的同族元素。A chemical bond is formed between the
舉例而言,若第一元素為鎵,第二元素可以是鋁、銦或鉈。也就是說,磊晶層22與單晶層10A的材料可以分別是多晶氮化鎵與單晶氮化鎵,而界面反應層23的材料可以是氮化鋁鎵、氮化銦鎵、或是氮化鋁銦鎵。如此,界面反應層23、磊晶層22及單晶層10A的材料都是III-V族化合物半導體,且晶格常數可相互匹配,可使單晶層10A與磊晶層22之間有很強的結合力。For example, if the first element is gallium, the second element may be aluminum, indium or thallium. That is to say, the material of the
在另一實施例中,界面反應層23的材料除了包含氮化鋁鎵、氮化銦鎵或氮化鋁銦鎵之外,可選擇性地包括氮化鋁、氮化銦、氮化鋁銦、氧化鋁、氧化銦或是氧化鋁銦中的其中一種或其任意組合。In another embodiment, the material of the
在本實施例中,單晶層10A是完全覆蓋界面反應層23,但本創作不以此為限。單晶層10A的表面10s經過拋光,而具有很低的表面粗糙度,而可作為後續磊晶成長元件的成長面。詳細而言,單晶層10A的表面10s的平均表面粗糙度可低於5nm,甚至低於1 nm。In this embodiment, the
[第二實施例][Second embodiment]
請參照圖14,圖14為本創作第二實施例的接合基板的製造方法的流程圖。在步驟S20中,提供多個單晶模板,以及在步驟S21中,提供一支撐基板。須說明的是,製作支撐基板2的詳細流程可參照圖5至圖7,以及相對應的說明,在此並不贅述。另外,製作每個單晶模板10的詳細流程可參照圖2至圖4,以及相對應的說明。Please refer to FIG. 14 . FIG. 14 is a flowchart of a method for manufacturing a bonded substrate according to a second embodiment of the present invention. In step S20, a plurality of single crystal templates are provided, and in step S21, a supporting substrate is provided. It should be noted that the detailed process of manufacturing the supporting
值得一提的是,在本實施例中,每個單晶模板10的尺寸都小於支撐基板2。在本實施例的製造方法中,在將每個單晶模板10由成長基板GS剝離後,可以切割每個單晶模板10,以使單晶模板10的形狀與另一單晶模板10的形狀相互配合。It is worth mentioning that, in this embodiment, the size of each
請參照圖14的步驟S22。在步驟S22中,接合多個單晶模板與支撐基板,多個單晶模相互拼接而共同形成一拼接式單晶模板。如圖15所示,將被切割成預定形狀的多個單晶模板10設置在支撐基板2上,而形成拼接式單晶模板100。在本實施例中,拼接式單晶模板100局部地覆蓋接合層23A的接合表面232,而使部分接合層23A被裸露出來,但本創作不以此為限。Please refer to step S22 in FIG. 14 . In step S22, a plurality of single crystal templates are bonded to the supporting substrate, and the plurality of single crystal molds are spliced together to form a spliced single crystal template. As shown in FIG. 15 , a plurality of
如前所述,拼接式單晶模板100與磊晶層22的材料可以是第一元素的氮化物,而接合層23A的材料可以包含第二元素,且第二元素為與第一元素同族的元素。舉例而言,拼接式單晶模板100與磊晶層22的材料為氮化鎵,則第一元素為鎵。因此,接合層23A的材料所包含的第二元素可以是鋁、銦或鉈。也就是說,接合層23A的材料可以是鋁金屬、銦金屬、鉈金屬或含有前述金屬的合金。As mentioned above, the material of the spliced
請參照圖16,可利用加熱器3對拼接式單晶模板100與支撐基板進行加熱,以使接合層23A與拼接式單晶模板100以及與磊晶層22產生合金反應。在一實施例中,可在氮氣氛或者氧氣氛下,對拼接式單晶模板100與支撐基板2加熱到預定反應溫度,並持溫一預定反應時間。前述的預定反應溫度可根據接合層23A的材料而決定,但不超過1200
oC,較佳是600
oC至1000
oC,以避免支撐基板2翹曲變形。
Referring to FIG. 16 , the
當單晶模板10與磊晶層22的材料都為氮化鎵,且接合層23A的材料為鋁層時,預定反應溫度至少800
oC,且預定反應時間至少1小時,但本創作不以此例為限。
When the
請參照圖17,接合層23A被反應之後,形成一界面反應層23。界面反應層23會與拼接式單晶模板100以及與磊晶層22都產生鍵結,從而使拼接式單晶模板100被接合在支撐基板2上。Referring to FIG. 17 , after the
在一實施例中,以拼接式單晶模板100與磊晶層22的材料都為氮化鎵,且接合層23A的材料為鋁舉例說明。在氮氣氛下進行加熱後,拼接式單晶模板100或者磊晶層22中的鎵原子擴散到接合層23A內,且接合層23A內的鋁原子與鎵原子與氮原子反應。另一方面,接合層23A內的鋁原子也可擴散到磊晶層22或拼接式單晶模板100內,而取代鎵原子,而與磊晶層22或拼接式單晶模板100的氮原子產生穩定的化學鍵結。In one embodiment, it is exemplified that the material of the spliced
因此,接合層23A產生合金反應後所形成的界面反應層23的材料包含氮化鋁鎵。值得一提的是,在進行加熱時,接合層23A的接合表面232沒有被拼接式單晶模板100覆蓋的區域會被氧化或氮化。據此,界面反應層23的材料除了可包含氮化鋁鎵之外,也會包括氮化鋁或者氧化鋁中的至少一者。Therefore, the material of the
在另一實施例中,當接合層23A的材料為銦時,界面反應層23的材料除了包含氮化銦鎵之外,還包含氮化銦或者氧化銦中的至少一者。接合層23A的材料為銦鋁合金時,界面反應層23的材料除了包含氮化鋁銦鎵之外,還可包含氮化鋁銦或者氧化鋁銦中的至少一者。In another embodiment, when the material of the
請再參照圖14的步驟S23及S24,在步驟S23中,切割拼接式單晶模板,以將拼接式單晶模板分離成一第一部分與一第二部分,第一部分在支撐基板上形成一單晶層。接著在步驟S24中,拋光單晶層的表面。如圖18所示,在本實施例中,拼接式單晶模板100是被橫向切割,以被分離成兩個部分。在一實施例中,可執行雷射剝離製程(laser lift-off process),來橫向切割拼接式單晶模板100。Please refer to steps S23 and S24 of FIG. 14 again. In step S23, the spliced single crystal template is cut to separate the spliced single crystal template into a first part and a second part, and the first part forms a single crystal on the support substrate. Floor. Next in step S24, the surface of the single crystal layer is polished. As shown in FIG. 18 , in this embodiment, the spliced
請參照圖19,將拼接式單晶模板100的第二部分100B剝離,而在支撐基板2上留下第一部分,而形成單晶層100A。值得注意的是,第一部分 (單晶層100A)的厚度小於第二部分100B的厚度。在一實施例中,第一部分 (單晶層100A)的厚度與拼接式單晶模板100的總厚度之間的比值為1至1000。舉例而言,當拼接式單晶模板100的總厚度為1 mm時,單晶層100A約只有1μm。在拋光單晶層100A的表面100s之後,接合基板Z2的單晶層100A的表面10s就可用於磊晶成長元件,如:發光二極體、高功率元件或是射頻元件。在一實施例中,可以通過化學機械研磨,將單晶層100A的表面100s拋光到具有極低表面粗糙度。Referring to FIG. 19 , the
值得一提的是,本創作實施例的製造方法還可進一步包括:接合拼接式單晶模板100的第二部分100B與另一支撐基板2。須說明的是,在第二部分100B與另一支撐基板2接合之前,第二部分100B的表面也可以先被拋光而具有較低的表面粗糙度,以增加第二部分100B與另一支撐基板2之間的結合力。It is worth mentioning that the manufacturing method of the present invention may further include: joining the
如圖19所示,通過本實施例所提供的製造方法,可以製作用來成長元件的另一種接合基板Z2。本實施例的接合基板Z2與圖13所示的接合基板Z1相同的元件具有相同或相似的標號,且不再贅述。As shown in FIG. 19 , another bonding substrate Z2 for growing components can be fabricated through the manufacturing method provided in this embodiment. Components of the bonding substrate Z2 in this embodiment that are the same as those of the bonding substrate Z1 shown in FIG. 13 have the same or similar reference numerals and will not be repeated here.
接合基板Z2包括支撐基板2以及單晶層100A。支撐基板2可包括基底20、緩衝層21、磊晶層22以及界面反應層23。在本實施例中,單晶層100A是局部地覆蓋界面反應層23。The bonding substrate Z2 includes the supporting
單晶層10A與磊晶層22的材料可以是第一元素的氮化物,而界面反應層23的材料可包含第一元素的氮化物或氧化物與第二元素的氮化物或氧化物,且第二元素是第一元素的同族元素。The material of the
舉例而言,若第一元素為鎵,第二元素可以是鋁、銦或鉈。也就是說,磊晶層22與單晶層10A的材料可以分別是多晶氮化鎵與單晶氮化鎵,而界面反應層23的材料可以是氮化鋁鎵、氮化銦鎵、或是氮化鋁銦鎵。如此,界面反應層23、磊晶層22及單晶層10A的材料都是III-V族化合物半導體,且晶格常數可相互匹配,可使單晶層10A與磊晶層22之間有很強的結合力。For example, if the first element is gallium, the second element may be aluminum, indium or thallium. That is to say, the material of the
在本實施例中,界面反應層23的材料除了包含氮化鋁鎵、氮化銦鎵或氮化鋁銦鎵之外,還進一步包括氮化鋁、氮化銦、氮化鋁銦、氧化鋁、氧化銦或是氧化鋁銦中的其中一種或其任意組合。In this embodiment, besides aluminum gallium nitride, indium gallium nitride or aluminum indium gallium nitride, the material of the
在本實施例中,單晶層100A是部分地覆蓋界面反應層23,但本創作不以此為限。單晶層100A的表面100s經過拋光,而具有很低的表面粗糙度,而可作為後續磊晶成長元件的成長面。詳細而言,單晶層100A的表面100s的平均表面粗糙度可低於5nm,甚至低於1 nm。In this embodiment, the
[實施例的有益效果][Advantageous Effects of Embodiment]
本創作的其中一有益效果在於,本創作所提供的接合基板及其製造方法,其能通過“提供一或多個單晶模板10”、“提供一支撐基板2,其中,支撐基板2包括基底20、接合層23A以及磊晶層22,磊晶層22位於基底20與接合層23A之間,且磊晶層22與單晶模板10的材料相同”以及 “接合一或多個單晶模板10與支撐基板2”的技術方案,來降低製造成本。另外,本實施例的支撐基板2中的磊晶層22可以通過相對較低溫的製程(如:濺鍍)來製作,因此,在製作大尺寸的支撐基板2時,可避免支撐基板2翹曲變形。One of the beneficial effects of this invention is that the bonding substrate and its manufacturing method provided by this invention can "provide one or more
在接合一或多個單晶模板10與支撐基板2的步驟中,使接合層23A與單晶模板10以及磊晶層22產生合金反應,而形成與單晶模板10的晶格常數相匹配的界面反應層23,也可提升單晶模板10與支撐基板2之間的接合強度。In the step of bonding one or more
另一方面,本創作實施例所提供的單晶模板10可重複使用。也就是說,同一個單晶模板10可重複地和多個支撐基板2貼合,來大量製造接合基板Z1, Z2,可以降低元件的製造成本。On the other hand, the
以上所公開的內容僅為本創作的優選可行實施例,並非因此侷限本創作的申請專利範圍,所以凡是運用本創作說明書及圖式內容所做的等效技術變化,均包含於本創作的申請專利範圍內。The content disclosed above is only the preferred feasible embodiment of this creation, and does not limit the scope of patent application for this creation. Therefore, all equivalent technical changes made by using the instructions and drawings of this creation are included in the application of this creation. within the scope of the patent.
Z1, Z2:接合基板
GS:成長基板
10:單晶模板
10A:單晶層
10s:表面
10B:第二部分
L:雷射光
2:支撐基板
20:基底
21:緩衝層
22:磊晶層
23A:接合層
231:接合界面
232:接合表面
23:界面反應層
100:拼接式單晶模板
100B:第二部分
100A:單晶層
100s:表面
3:加熱器
S10-S14, S20-S24:流程步驟
Z1, Z2: Bonded substrate
GS: Growth Substrate
10:
圖1為本創作第一實施例的接合基板的製造方法的流程圖。FIG. 1 is a flowchart of a method for manufacturing a bonded substrate according to a first embodiment of the present invention.
圖2為本創作第一實施例在形成單晶模板於成長基板的步驟中的示意圖。FIG. 2 is a schematic diagram of the step of forming a single crystal template on a growth substrate according to the first embodiment of the present invention.
圖3為本創作第一實施例在分離單晶模板與成長基板的步驟中的示意圖。FIG. 3 is a schematic diagram of the step of separating the single crystal template and the growth substrate according to the first embodiment of the present invention.
圖4為本創作第一實施例在分離單晶模板與成長基板的步驟後的示意圖。FIG. 4 is a schematic diagram of the first embodiment of the present invention after the step of separating the single crystal template and the growth substrate.
圖5為本創作第一實施例的支撐基板在形成緩衝層於基底上後的示意圖。FIG. 5 is a schematic diagram of the supporting substrate of the first embodiment of the present invention after a buffer layer is formed on the substrate.
圖6為本創作第一實施例的支撐基板在形成磊晶層於緩衝層上的步驟後的示意圖。FIG. 6 is a schematic diagram of the supporting substrate after the step of forming an epitaxial layer on the buffer layer according to the first embodiment of the present invention.
圖7為本創作第一實施例的支撐基板在形成接合層在磊晶層上的步驟後的示意圖。FIG. 7 is a schematic diagram of the supporting substrate after the step of forming the bonding layer on the epitaxial layer according to the first embodiment of the present invention.
圖8為本創作第一實施例在接合單晶模板與支撐基板的步驟中的立體示意圖。FIG. 8 is a three-dimensional schematic view of the step of bonding the single crystal template and the supporting substrate according to the first embodiment of the present invention.
圖9為本創作第一實施例在接合單晶模板與支撐基板的步驟的示意圖。FIG. 9 is a schematic diagram of the step of bonding the single crystal template and the supporting substrate according to the first embodiment of the present invention.
圖10為本創作第一實施例在加熱單晶模板與支撐基板的步驟的示意圖。FIG. 10 is a schematic diagram of the step of heating the single crystal template and the supporting substrate according to the first embodiment of the present invention.
圖11為本創作第一實施例在接合單晶模板與支撐基板的步驟後的示意圖。FIG. 11 is a schematic diagram of the first embodiment of the present invention after the step of bonding the single crystal template and the supporting substrate.
圖12為本創作第一實施例在切割單晶模板的步驟中的示意圖。FIG. 12 is a schematic diagram of the step of cutting a single crystal template according to the first embodiment of the present invention.
圖13為本創作第一實施例在切割單晶模板的步驟之後的示意圖。FIG. 13 is a schematic diagram of the first embodiment of the present invention after the step of cutting the single crystal template.
圖14為本創作第二實施例的接合基板的製造方法的流程圖。FIG. 14 is a flowchart of a method for manufacturing a bonded substrate according to a second embodiment of the present invention.
圖15為本創作第二實施例在接合多個單晶模板與支撐基板的步驟中的立體示意圖。FIG. 15 is a schematic perspective view of the second embodiment of the present invention during the step of bonding a plurality of single crystal templates and a supporting substrate.
圖16為本創作第二實施例在加熱拼接式單晶模板與支撐基板的步驟的示意圖。FIG. 16 is a schematic diagram of the step of heating the spliced single crystal template and the supporting substrate according to the second embodiment of the present invention.
圖17為本創作第二實施例在接合拼接式單晶模板與支撐基板的步驟後的示意圖。FIG. 17 is a schematic diagram of the second embodiment of the present invention after the step of joining the spliced single crystal template and the supporting substrate.
圖18為本創作第二實施例在切割拼接式單晶模板的步驟中的示意圖。FIG. 18 is a schematic diagram of the second embodiment of the present invention during the step of cutting the spliced single crystal template.
圖19為本創作第二實施例在切割拼接式單晶模板的步驟之後的示意圖。FIG. 19 is a schematic diagram of the second embodiment of the present invention after the step of cutting the spliced single crystal template.
10:單晶模板 10:Single crystal template
2:支撐基板 2: Support substrate
20:基底 20: base
21:緩衝層 21: buffer layer
22:磊晶層 22: epitaxial layer
23A:接合層 23A: bonding layer
231:接合界面 231: Bonding interface
232:接合表面 232: joint surface
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111209381U TWM634692U (en) | 2022-08-30 | 2022-08-30 | Junction substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111209381U TWM634692U (en) | 2022-08-30 | 2022-08-30 | Junction substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
TWM634692U true TWM634692U (en) | 2022-11-21 |
Family
ID=85785083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111209381U TWM634692U (en) | 2022-08-30 | 2022-08-30 | Junction substrate |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWM634692U (en) |
-
2022
- 2022-08-30 TW TW111209381U patent/TWM634692U/en unknown
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100969812B1 (en) | Manufacturing Method of Gallium Nitride Single Crystalline Substrate Using Self-Split | |
JP4335187B2 (en) | Nitride semiconductor device manufacturing method | |
US8143702B2 (en) | Group III-V nitride based semiconductor substrate and method of making same | |
TWI426162B (en) | Method for preparing substrate for growing gallium nitride and method for preparing gallium nitride substrate | |
CN100505164C (en) | Fabrication process of nitride semiconductor substrate and composite material substrate | |
JP2018087128A (en) | Method for growing nitride semiconductor layer | |
JP2003119100A (en) | Substrate for epitaxial treatment, epitaxial wafer, semiconductor device, and epitaxial growth method | |
JP2009505938A (en) | Semiconductor substrate, method for manufacturing a self-supporting semiconductor substrate by hydride vapor phase epitaxy, and mask layer used therefor | |
JP2009102218A (en) | Method for manufacturing compound semiconductor substrate | |
KR101672213B1 (en) | Method for manufacturing semiconductor device | |
JP4333466B2 (en) | Manufacturing method of semiconductor substrate and manufacturing method of free-standing substrate | |
CN106206258A (en) | Form method and the GaN substrate of GaN layer on a silicon substrate | |
JP5056299B2 (en) | Nitride semiconductor base substrate, nitride semiconductor multilayer substrate, and method of manufacturing nitride semiconductor base substrate | |
KR20050006409A (en) | Growth method of nitride epitaxial layer using conversion of nitride interlayer into metallic phase | |
KR19990016925A (en) | Baline single crystal manufacturing method | |
TWM634692U (en) | Junction substrate | |
TWI844930B (en) | Bonded substrate and method of manufacturing the same | |
KR20120008141A (en) | Substrate for producing semiconductor device and method for producing semiconductor device | |
TW202410156A (en) | Bonded substrate and method of manufacturing the same | |
KR20040078211A (en) | Method for manufacturing GaN substrate | |
JP2010251743A (en) | Substrate for growing group-iii nitride semiconductor, group-iii nitride semiconductor device, free-standing substrate for group-iii nitride semiconductor, and method for manufacturing the same | |
JP2009084136A (en) | Method for manufacturing semiconductor device | |
KR100949212B1 (en) | Method for manufacturing substrate of Nitride chemical substrate | |
KR20130049590A (en) | Substrate having thin film of joined and method of fabricating thereof | |
KR20040078209A (en) | Method of manufacturing compound semiconductor substrate using buffer layer with void |