TWM634452U - Lead frame for chip packaging and chip package structure device - Google Patents

Lead frame for chip packaging and chip package structure device Download PDF

Info

Publication number
TWM634452U
TWM634452U TW111206104U TW111206104U TWM634452U TW M634452 U TWM634452 U TW M634452U TW 111206104 U TW111206104 U TW 111206104U TW 111206104 U TW111206104 U TW 111206104U TW M634452 U TWM634452 U TW M634452U
Authority
TW
Taiwan
Prior art keywords
lead frame
pins
stage
chip
voltage pin
Prior art date
Application number
TW111206104U
Other languages
Chinese (zh)
Inventor
張學豪
李軍
李棟杰
趙時峰
Original Assignee
大陸商昂寶電子（上海）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商昂寶電子（上海）有限公司 filed Critical 大陸商昂寶電子（上海）有限公司
Publication of TWM634452U publication Critical patent/TWM634452U/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

提供了晶片封裝的引線框架和晶片封裝結構裝置。該用於晶片封裝的引線框架，包括至少一個主載片台、至少一個次載片台、以及多個引腳，其中，至少一個主載片台所在的平面相對於多個引腳所在的平面是下沉平面，並且至少一個次載片台與多個引腳位於同一平面上。 A chip package lead frame and a chip package structure device are provided. The lead frame for chip packaging includes at least one main loading stage, at least one secondary loading stage, and a plurality of pins, wherein the plane where at least one main loading stage is located is opposite to the plane where the multiple pins are located is a sunken plane, and at least one substage is on the same plane as the plurality of pins.

Description

用於晶片封裝的引線框架和晶片封裝結構裝置 Lead frame and chip package structure device for chip package

本創作涉及積體電路領域，尤其涉及一種用於晶片封裝的引線框架和晶片封裝結構裝置。 The invention relates to the field of integrated circuits, in particular to a lead frame for chip packaging and a chip packaging structural device.

積體電路晶片(簡稱晶片)是把一定數量的常用電子元件(例如，電阻、電容、電晶體等)以及這些元件之間的連線通過半導體工藝集成在半導體晶片或介質基片上，然後封裝在一個管殼內形成的微型結構。積體電路晶片具有體積小、重量輕、引出線和焊接點少、壽命長、可靠性高、性能好等優點，同時成本低、便於大規模生產。 An integrated circuit chip (referred to as a chip) is to integrate a certain number of commonly used electronic components (such as resistors, capacitors, transistors, etc.) A microstructure formed within a package. Integrated circuit chips have the advantages of small size, light weight, fewer lead wires and soldering points, long life, high reliability, and good performance. At the same time, they are low in cost and easy to mass produce.

積體電路晶片不僅在民用電子設備(例如，收錄機、電視機、電腦等)方面得到廣泛的應用，同時在軍事、通訊、遙控等方面也得到廣泛的應用。用積體電路晶片來裝配電子設備，其裝配密度比電晶體可提高幾十倍至幾千倍，電子設備的穩定工作時間也可大大提高。 Integrated circuit chips are not only widely used in civilian electronic equipment (such as radio recorders, televisions, computers, etc.), but also in military affairs, communications, and remote control. Using integrated circuit chips to assemble electronic equipment, its assembly density can be increased by tens to thousands of times compared with transistors, and the stable working time of electronic equipment can also be greatly improved.

根據本創作實施例的用於晶片封裝的引線框架，包括至少一個主載片台、至少一個次載片台、以及多個引腳，其中，至少一個主載片台所在的平面相對於多個引腳所在的平面是下沉平面，並且至少一個次載片台與多個引腳位於同一平面上。 A lead frame for chip packaging according to an embodiment of the present invention includes at least one main stage, at least one substage, and a plurality of pins, wherein the plane where the at least one main stage is located is opposite to the plurality of pins. The plane where the pins are located is a sunken plane, and at least one sub-stage is located on the same plane as the plurality of pins.

根據本創作實施例的晶片封裝結構裝置，包括上述引線框架。 A chip package structure device according to an embodiment of the present invention includes the above-mentioned lead frame.

1B-1:主載片台 1B-1: Main loading stage

1B-2:次載片台 1B-2: Sub-stage

100:引線框架 100: lead frame

1,2,3,4,5,6:引腳 1,2,3,4,5,6: pins

110:功率積體電路晶片 110: Power integrated circuit chips

120:電源控制晶片 120: Power control chip

130:散熱通道 130: cooling channel

從下面結合圖式對本創作的具體實施方式的描述中可以更好地理解本創作，其中： 圖1A和1B分別示出了根據本創作實施例的用於晶片封裝的引線框架的俯視圖和側面圖；圖2示出了圖1A和1B所示的引線框架上裝貼功率積體電路晶片和電源控制晶片後的結構示意圖；圖3A和3B分別示出了根據本創作實施例的晶片封裝結構裝置的俯視圖和側面圖；圖4示出了根據本創作實施例的晶片封裝結構裝置的引腳定義示例的示意圖；圖5示出了採用圖4所示的晶片封裝結構裝置的開關電源應用電路的示意圖。 This creation can be better understood from the following description of the specific implementation manner of this creation in conjunction with the drawings, wherein: 1A and 1B respectively show a top view and a side view of a lead frame for chip packaging according to an embodiment of the present invention; FIG. Schematic diagram of the structure behind the power supply control chip; Figure 3A and 3B respectively show a top view and a side view of the chip package structure device according to the embodiment of the invention; Figure 4 shows the pins of the chip package structure device according to the embodiment of the invention A schematic diagram of a definition example; FIG. 5 shows a schematic diagram of a switching power supply application circuit using the chip package structure device shown in FIG. 4 .

下面將詳細描述本創作的各個方面的特徵和示例性實施例。在下面的詳細描述中，提出了許多具體細節，以便提供對本創作的全面理解。但是，對於本領域技術人員來說很明顯的是，本創作可以在不需要這些具體細節中的一些細節的情況下實施。下面對實施例的描述僅僅是為了通過示出本創作的示例來提供對本創作的更好的理解。本創作決不限於下面所提出的任何具體配置，而是在不脫離本創作的精神的前提下覆蓋了元素和部件的任何修改、替換和改進。在圖式和下面的描述中，沒有示出公知的結構和技術，以便避免對本創作造成不必要的模糊。另外，需要說明的是，這裡使用的用語“A與B連接”可以表示“A與B直接連接”也可以表示“A與B經由一個或多個其他元件間接連接”。 Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the invention by showing an example of the invention. The invention is in no way limited to any specific configuration set forth below, but rather covers any modifications, substitutions and improvements of elements and parts without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention. In addition, it should be noted that the term "A is connected to B" used herein may mean "A and B are directly connected" or "A and B are indirectly connected via one or more other elements".

一般，積體電路晶片的製造過程主要包括以下幾個階段：積體電路晶片的設計階段、積體電路晶片的製作階段、積體電路晶片的封裝階段、以及積體電路晶片的測試階段。當積體電路晶片製作完成後，積體電路晶片上通常有多個焊墊。在積體電路晶片的封裝階段，通常會把積體電路晶片上的這些焊墊與對應的引線框架互相電連接。積體電路晶片通常是通過焊線或者以植球結合的方式連接到引線框架上，使得積體電路晶片 的這些焊墊與引線框架的接點電連接，從而實現積體電路晶片的封裝結構內部的電氣連接。 Generally, the manufacturing process of the IC chip mainly includes the following stages: the design stage of the IC chip, the manufacturing stage of the IC chip, the packaging stage of the IC chip, and the testing stage of the IC chip. After the integrated circuit chip is fabricated, there are usually a plurality of solder pads on the integrated circuit chip. During the packaging stage of the integrated circuit chip, these pads on the integrated circuit chip are usually electrically connected to the corresponding lead frames. The integrated circuit chip is usually connected to the lead frame by wire bonding or by ball bonding, so that the integrated circuit chip These pads are electrically connected to the contacts of the lead frame, thereby realizing the electrical connection inside the packaging structure of the integrated circuit chip.

隨著功率類積體電路晶片越來越多地被使用，如何實現功率類積體電路晶片的高散熱性能的封裝成為半導體行業普遍關心的問題。因此，提出了根據本創作實施例的用於晶片封裝的引線框架。 As power integrated circuit chips are used more and more, how to realize packaging of power integrated circuit chips with high heat dissipation performance has become a common concern in the semiconductor industry. Therefore, a lead frame for chip packaging according to an embodiment of the present invention is proposed.

圖1A和1B分別示出了根據本創作實施例的用於晶片封裝的引線框架100的俯視圖和側面圖。如圖1A和1B所示，在一些實施例中，引線框架100包括至少一個主載片台(例如，主載片台1B-1)、至少一個次載片台(例如，次載片台1B-2)、以及多個引腳(例如，引腳1至引腳6)，其中，至少一個主載片台1B-1所在的平面相對於多個引腳1~6所在的平面是下沉平面，並且至少一個次載片台1B-2與多個引腳1~6位於同一平面上。 1A and 1B show a top view and a side view, respectively, of a lead frame 100 for chip packaging according to an embodiment of the present invention. As shown in FIGS. 1A and 1B , in some embodiments, leadframe 100 includes at least one primary stage (e.g., primary stage 1B-1), at least one secondary stage (e.g., secondary stage 1B-1), -2), and a plurality of pins (for example, pins 1 to 6), wherein the plane where at least one main carrier stage 1B-1 is located is sunken relative to the plane where multiple pins 1~6 are located plane, and at least one sub-stage 1B-2 is located on the same plane as the plurality of pins 1-6.

如圖1A和圖1B所示，在一些實施例中，引線框架100包括至少一個高壓引腳和至少一個低壓引腳，其中，至少一個高壓引腳中的每個高壓引腳與至少一個低壓引腳中與該高壓引腳相鄰的低壓引腳之間的間距大於至少一個低壓引腳中的任意兩個相鄰的低壓引腳之間的間距。例如，至少一個高壓引腳中的每個高壓引腳與至少一個低壓引腳中與該高壓引腳相鄰的低壓引腳之間的間距大於或等於1.2mm且小於或等於2.54mm。 As shown in FIGS. 1A and 1B , in some embodiments, the lead frame 100 includes at least one high-voltage pin and at least one low-voltage pin, wherein each of the at least one high-voltage pin is connected to at least one low-voltage pin. The distance between the low-voltage pins adjacent to the high-voltage pin in the pin is larger than the distance between any two adjacent low-voltage pins in the at least one low-voltage pin. For example, the distance between each of the at least one high-voltage pin and the adjacent low-voltage pin of the at least one low-voltage pin is greater than or equal to 1.2mm and less than or equal to 2.54mm.

如圖1A和1B所示，在一些實施例中，每個主載片台1B-1與至少一個引腳1~6相連。這樣，可確保引線框架100的結構穩定性，同時可輔助提升引線框架100的散熱能力，提高晶片的使用壽命。 As shown in FIGS. 1A and 1B , in some embodiments, each master stage 1B- 1 is connected to at least one pin 1-6. In this way, the structural stability of the lead frame 100 can be ensured, and at the same time, the heat dissipation capability of the lead frame 100 can be assisted to improve the service life of the chip.

如圖1A和1B所示，在一些實施例中，與一個或多個主載片台1B-1相連的每個引腳1~6的寬度為未與任意一個主載片台相連的每個引腳的寬度的1至1.5倍。這樣，可提高引線框架100的加工過程的穩定性，同時可輔助提升引線框架100的散熱能力。 As shown in FIGS. 1A and 1B , in some embodiments, each pin 1-6 connected to one or more master stages 1B-1 has a width equal to that of each pin not connected to any master stage. 1 to 1.5 times the width of the pin. In this way, the stability of the processing process of the lead frame 100 can be improved, and at the same time, the heat dissipation capability of the lead frame 100 can be assisted to be improved.

如圖1A和1B所示，在一些實施例中，至少一個主載片台1B-1所在的平面相對於多個引腳1~6所在的平面的下沉高度小於或等於 1.6mm。這樣，可使主載片台1B-1與次載片台1B-2和引腳1~6之間的焊線連接簡單順暢，從而可明顯提升晶片封裝的良品率。 As shown in Figures 1A and 1B, in some embodiments, the sinking height of the plane where at least one main slide stage 1B-1 is located relative to the plane where the plurality of pins 1~6 is located is less than or equal to 1.6mm. In this way, the bonding wire connection between the primary loading stage 1B- 1 and the secondary loading stage 1B- 2 and the pins 1-6 can be made simple and smooth, thereby significantly improving the yield rate of chip packaging.

如圖1A和1B所示，在一些實施例中，引線框架100的多個引腳1~6的長度不相等，並且這些引腳彼此之間是非平行的。這樣，可有效控制內部焊線連接時的弧度控制和加工過程的塑膠充填導致的碰絲、塌絲、沖絲等失效，從而大大提高晶片封裝的良品率。 As shown in FIGS. 1A and 1B , in some embodiments, the lengths of the plurality of pins 1 - 6 of the lead frame 100 are not equal, and the pins are non-parallel to each other. In this way, it is possible to effectively control the radian control of the internal wire connection and the failures caused by the plastic filling in the processing process, such as wire collision, collapse, and punching, thereby greatly improving the yield rate of chip packaging.

如圖1A和1B所示，在一些實施例中，引線框架100的每個引腳1~6的厚度大於或等於0.25mm且小於或等於0.55mm。 As shown in FIGS. 1A and 1B , in some embodiments, the thickness of each pin 1 - 6 of the lead frame 100 is greater than or equal to 0.25 mm and less than or equal to 0.55 mm.

如圖1A和1B所示，在一些實施例中，每個主載片台1B-1的厚度大於或等於0.25mm且小於或等於1.4mm。 As shown in FIGS. 1A and 1B , in some embodiments, the thickness of each master stage 1B- 1 is greater than or equal to 0.25 mm and less than or equal to 1.4 mm.

本領域技術人員應該明白，引線框架100可根據實際需要包括例如，6個、8個、10個、12個等數目的更多引腳或者包括例如，4個等數目的更少引腳。 Those skilled in the art should understand that the lead frame 100 may include more pins such as 6, 8, 10, 12 or fewer pins such as 4 according to actual needs.

圖2示出了圖1A和1B所示的引線框架100上裝貼功率積體電路晶片110和電源控制晶片120後的結構示意圖。如圖2所示，位於次載片台1B-2上的電源控制晶片通過焊接線分別與位於主載片台1B-1上的功率積體電路晶片110和引腳1~6進行互連，內部電路連接後形成對應的電路功能。 FIG. 2 shows a schematic view of the structure of the lead frame 100 shown in FIGS. 1A and 1B after the power integrated circuit chip 110 and the power control chip 120 are mounted. As shown in FIG. 2 , the power control chip on the sub-carrier 1B-2 is interconnected with the power integrated circuit chip 110 and pins 1-6 on the main carrier 1B-1 respectively through bonding wires, The corresponding circuit functions are formed after the internal circuits are connected.

當引線框架100被應用到晶片封裝結構裝置中時，可以通過把主載片台1B-1暴露在晶片封裝結構裝置的外部來擴大承載在主載片臺1B-1上的積體電路晶片與外部環境的散熱通道130。圖3A和3B分別示出了根據本創作實施例的晶片封裝結構裝置的俯視圖和側面圖。 When the lead frame 100 is applied to the chip package structure device, the integrated circuit chip and the integrated circuit chip carried on the main chip stage 1B-1 can be enlarged by exposing the main chip stage 1B-1 to the outside of the chip package structure device. The heat dissipation channel 130 of the external environment. 3A and 3B respectively show a top view and a side view of a chip package structure device according to an embodiment of the present invention.

在一些實施例中，為了使主載片台1B-1暴露在晶片封裝結構裝置的外部，可以將晶片封裝結構裝置的厚度減小，使結構外觀比例更合理，同時合理控制製造成本。 In some embodiments, in order to expose the main wafer stage 1B-1 to the outside of the chip package structure device, the thickness of the chip package structure device can be reduced to make the proportion of the structure appearance more reasonable, and at the same time reasonably control the manufacturing cost.

圖4示出了根據本創作實施例的晶片封裝結構裝置的引腳定義示例的示意圖。圖5示出了採用圖4所示的晶片封裝結構裝置的開關電 源應用電路的示意圖。經過驗證，採用根據本創作實施例的引線框架100的晶片封裝結構製造具有超越同類產品的良好散熱性能，可提升電子產品的可靠性和應用壽命，同時可明顯降低電子產品的應用成本。 FIG. 4 shows a schematic diagram of an example of pin definition of a chip package structure device according to an embodiment of the present invention. Fig. 5 shows the switching circuit adopting the chip package structure device shown in Fig. 4 Schematic of the source application circuit. It has been verified that the chip packaging structure of the lead frame 100 according to the present invention has better heat dissipation performance than similar products, can improve the reliability and service life of electronic products, and can significantly reduce the application cost of electronic products.

綜上所述，根據本創作實施例的用於晶片封裝的引線框架和晶片封裝結構裝置具有成本低、散熱性能高等優點。另外，在根據本創作實施例的用於晶片封裝的引線框架和晶片封裝結構裝置中，高壓引腳和低壓引腳之間的間距較大，可以預防某些應用條件尤其是潮濕環境下相鄰引腳(特別是高壓與低壓引腳)間的打火問題，從而可以保證晶片封裝結構裝置的可靠性和安全性。 To sum up, the lead frame for chip packaging and the structural device for chip packaging according to the embodiment of the present invention have the advantages of low cost and high heat dissipation performance. In addition, in the lead frame for chip packaging and the chip package structure device according to the embodiment of the present invention, the distance between the high-voltage pins and the low-voltage pins is relatively large, which can prevent adjacent pins under certain application conditions, especially in humid environments. The ignition problem between the pins (especially the high-voltage and low-voltage pins) can ensure the reliability and safety of the chip package structure device.

本創作可以以其他的具體形式實現，而不脫離其精神和本質特徵。當前的實施例在所有方面都被看作是示例性的而非限定性的，本創作的範圍由所附請求項而非上述描述定義，並且落入請求項的含義和等同物的範圍內的全部改變都被包括在本創作的範圍中。 This creation can be realized in other specific forms without departing from its spirit and essential characteristics. The current embodiments are to be considered in all respects as illustrative rather than restrictive, and the scope of the present creation is defined by the appended claims rather than the above description, and what falls within the meanings and equivalents of the claims All changes are included within the scope of this work.

1B-1:主載片台 1B-1: Main loading stage

1B-2:次載片台 1B-2: Sub-stage

100:引線框架 100: lead frame

1,2,3,4,5,6:引腳 1,2,3,4,5,6: pins

Claims (14)

一種用於晶片封裝的引線框架，其特徵在於，包括至少一個主載片台、至少一個次載片台、以及多個引腳，其中，所述至少一個主載片台所在的平面相對於所述多個引腳所在的平面是下沉平面，並且所述至少一個次載片台與所述多個引腳位於同一平面上。 A lead frame for chip packaging, characterized in that it includes at least one main loading stage, at least one secondary loading stage, and a plurality of pins, wherein the plane where the at least one main loading stage is located is relative to the The plane where the plurality of pins are located is a sunken plane, and the at least one sub-stage is located on the same plane as the plurality of pins. 如請求項1所述的引線框架，其中，所述多個引腳包括至少一個高壓引腳和至少一個低壓引腳。 The lead frame according to claim 1, wherein the plurality of pins include at least one high voltage pin and at least one low voltage pin. 如請求項2所述的引線框架，其中，所述至少一個高壓引腳中的每個高壓引腳與所述至少一個低壓引腳中與該高壓引腳相鄰的低壓引腳之間的間距大於所述至少一個低壓引腳中的任意兩個相鄰的低壓引腳之間的間距。 The lead frame according to claim 2, wherein the distance between each high-voltage pin of the at least one high-voltage pin and the low-voltage pin adjacent to the high-voltage pin among the at least one low-voltage pin greater than the distance between any two adjacent low-voltage pins in the at least one low-voltage pin. 如請求項2所述的引線框架，其中，所述至少一個高壓引腳中的每個高壓引腳與所述至少一個低壓引腳中與該高壓引腳相鄰的低壓引腳之間的間距大於或等於1.2mm且小於或等於2.54mm。 The lead frame according to claim 2, wherein the distance between each high-voltage pin of the at least one high-voltage pin and the low-voltage pin adjacent to the high-voltage pin among the at least one low-voltage pin Greater than or equal to 1.2mm and less than or equal to 2.54mm. 如請求項1所述的引線框架，其中，所述至少一個主載片台中的每個主載片台與所述多個引腳中的至少一個引腳相連。 The lead frame of claim 1, wherein each of the at least one main stage is connected to at least one of the plurality of pins. 如請求項5所述的引線框架，其中，所述多個引腳中與所述至少一個主載片台中的一個或多個主載片台相連的每個引腳的寬度為所述多個引腳中未與所述至少一個主載片台中的任意一個主載片台相連的每個引腳的寬度的1至1.5倍。 The lead frame according to claim 5, wherein the width of each of the plurality of pins connected to one or more of the at least one main carrier stage is the width of the plurality of 1 to 1.5 times the width of each of the pins not connected to any one of the at least one main stage. 如請求項1所述的引線框架，其中，所述至少一個主載片台所在的平面相對於所述多個引腳所在的平面的下沉高度小於或等於1.6mm。 The lead frame according to claim 1, wherein the sinking height of the plane where the at least one main carrier stage is located relative to the plane where the plurality of pins are located is less than or equal to 1.6mm. 如請求項1所述的引線框架，其中，所述多個引腳的長度不相等，並且所述多個引腳彼此之間是非平行的。 The lead frame according to claim 1, wherein the lengths of the plurality of pins are not equal, and the plurality of pins are non-parallel to each other. 如請求項1所述的引線框架，其中，所述多個引腳中的每個引腳的厚度大於或等於0.25mm且小於或等於0.55mm。 The lead frame according to claim 1, wherein the thickness of each of the plurality of leads is greater than or equal to 0.25 mm and less than or equal to 0.55 mm. 如請求項1所述的引線框架，其中，所述至少一個主載片台中的每個主載片台的厚度大於或等於0.25mm且小於或等於1.4mm。 The lead frame of claim 1, wherein each of the at least one main stage has a thickness greater than or equal to 0.25 mm and less than or equal to 1.4 mm. 一種晶片封裝結構裝置，其特徵在於，包括請求項1至10中任一項所述的引線框架。 A chip package structure device, characterized by comprising the lead frame described in any one of Claims 1 to 10. 如請求項11所述的晶片封裝結構裝置，其特徵在於，所述引線框架的至少一個主載片台暴露在所述晶片封裝結構裝置的外部。 The chip package structure device according to claim 11, wherein at least one main carrier stage of the lead frame is exposed outside the chip package structure device. 如請求項11所述的晶片封裝結構裝置，其特徵在於，所述引線框架的至少一個主載片台用於承載大功率積體電路晶片。 The chip package structure device according to Claim 11 is characterized in that at least one main chip stage of the lead frame is used to carry a high-power integrated circuit chip. 如請求項11所述的晶片封裝結構裝置，其特徵在於，所述引線框架的至少一個次載片台用於承載電源控制晶片。 The chip package structure device according to claim 11, wherein at least one sub-stage of the lead frame is used to carry a power control chip.
TW111206104U 2022-03-08 2022-06-09 Lead frame for chip packaging and chip package structure device TWM634452U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202220501605.9U CN217426736U (en) 2022-03-08 2022-03-08 Lead frame for chip packaging and chip packaging structure device
CN202220501605.9 2022-03-08

Publications (1)

Publication Number Publication Date
TWM634452U true TWM634452U (en) 2022-11-21

Family

ID=83179260

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111206104U TWM634452U (en) 2022-03-08 2022-06-09 Lead frame for chip packaging and chip package structure device

Country Status (2)

Country Link
CN (1) CN217426736U (en)
TW (1) TWM634452U (en)

Also Published As

Publication number Publication date
CN217426736U (en) 2022-09-13

Similar Documents

Publication Publication Date Title
US10566320B2 (en) Method for fabricating electronic package
US8759157B2 (en) Heat dissipation methods and structures for semiconductor device
TWI277185B (en) Semiconductor package structure
US12015019B2 (en) Stacked die multichip module package
KR20050044925A (en) Semiconductor multi-package module having wire bond interconnection between stacked packages
US9748205B2 (en) Molding type power module
US9905439B2 (en) Power module package having patterned insulation metal substrate
JP2022051530A (en) Package structure for low-capacity tvs
US9655265B2 (en) Electronic module
US9761507B1 (en) Stacked rectifiers in a package
US9865531B2 (en) Power module package having patterned insulation metal substrate
US20060274497A1 (en) Electronic apparatus with thermal module
CN213150769U (en) High-power integrated circuit chip packaging device
CN215933584U (en) High-power integrated circuit chip packaging device and lead frame
TWM634452U (en) Lead frame for chip packaging and chip package structure device
US9601419B1 (en) Stacked leadframe packages
CN106328620B (en) Integrated circuit package and method of manufacturing the same
KR102016019B1 (en) High thermal conductivity semiconductor package
TWM634451U (en) Lead frame for chip package and chip package structure device
CN218939662U (en) Lead frame for chip package and chip package structure device
US7091608B2 (en) Chip package
CN217655869U (en) Semiconductor package assembly
KR20140147528A (en) semiconductor package and connection structure of a semiconductor package and mounting method of semiconductor packages
KR102418409B1 (en) Electrically isolated power semiconductor with heat clip
US20070164395A1 (en) Chip package with built-in capacitor structure