TWM634451U - Lead frame for chip package and chip package structure device - Google Patents

Abstract

A lead frame for chip packaging and a chip package structural device are provided. The lead frame for chip packaging includes at least two chip stages and a plurality of pins, wherein one of the at least two chip stages is connected to at least three pins of the plurality of pins at the same time.

Description

Lead frame and chip package structure device for chip package

The invention relates to the field of integrated circuits, in particular to a lead frame for chip packaging and a chip packaging structural device.

An integrated circuit chip (referred to as chip) is to integrate a certain number of commonly used electronic components (such as resistors, capacitors, transistors, etc.) A microstructure formed within a package. Integrated circuit chips have the advantages of small size, light weight, fewer lead wires and soldering points, long life, high reliability, and good performance. At the same time, they are low in cost and easy to mass produce.

Integrated circuit chips are not only widely used in civilian electronic equipment (such as radio recorders, televisions, computers, etc.), but also in military affairs, communications, and remote control. Using integrated circuit chips to assemble electronic equipment, its assembly density can be increased by tens to thousands of times compared with transistors, and the stable working time of electronic equipment can also be greatly improved.

A lead frame for chip packaging according to an embodiment of the present invention includes at least two chip stages and a plurality of pins, wherein one of the at least two chip stages is connected to one of the plurality of pins at the same time At least three pins.

A chip package structure device according to an embodiment of the present invention includes the above-mentioned lead frame for chip package.

1,2,3,4,5,6,7: pins

100: lead frame

11,21 31 41 51,61,71: Lock glue hole

81: Main loading stage

82: Secondary main stage

811,821: silver plating

812,822: not silver plated

820: Oval lock glue hole

823: full silver plating

814,824: Semi-etched circular locking hole

G1, G2: spacing

93: Chip packaging structure device

94: Application circuit of chip package structure device

This creation can be better understood from the following description of the specific implementation manner of this creation in conjunction with the drawings, wherein: 1A and 1B show top and side views, respectively, of a lead frame for a die package according to an embodiment of the invention.

FIG. 2 shows a view of the silver plated area of the lead frame shown in FIGS. 1A and 1B .

FIG. 3 shows a schematic diagram of the arrangement of half-etched circular locking holes on the back of the carrier stage in the lead frame shown in FIGS. 1A and 1B .

FIG. 4 shows a schematic structural view of the lead frame shown in FIGS. 1A and 1B after mounting a power chip and a main control chip.

FIG. 5 shows a schematic diagram of an example functional pin configuration of a chip package structure device employing the lead frame shown in FIGS. 1A and 1B .

FIG. 6 shows a schematic structural diagram of an example application circuit using the chip package structure device shown in FIG. 5 .

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the invention by showing an example of the invention. The invention is in no way limited to any specific configuration set forth below, but rather covers any modifications, substitutions and improvements of elements and parts without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention. In addition, it should be noted that the term "A is connected to B" used herein may mean "A and B are directly connected" or "A and B are indirectly connected via one or more other elements".

Generally, the manufacturing process of the IC chip mainly includes the following stages: the design stage of the IC chip, the manufacturing stage of the IC chip, the packaging stage of the IC chip, and the testing stage of the IC chip. After the integrated circuit chip is fabricated, there are usually a plurality of solder pads on the integrated circuit chip. During the packaging stage of the integrated circuit chip, these pads on the integrated circuit chip are usually electrically connected to the corresponding lead frames. Integrated circuit chips are usually The bonding pads of the integrated circuit chip are electrically connected to the contacts of the lead frame by bonding wires or ball bonding to the lead frame, thereby realizing the electrical connection inside the packaging structure of the integrated circuit chip.

With the increasing use of highly integrated multi-chip packaged integrated circuit chips, how to realize reliable packaging of multiple chips with high integration and high heat dissipation performance has become a common concern in the semiconductor industry. Therefore, a lead frame for a chip package and a chip package structure device according to an embodiment of the present invention are proposed.

1A and 1B show a top view and a side view, respectively, of a lead frame 100 for chip packaging according to an embodiment of the present invention. As shown in FIGS. 1A and 1B , in some embodiments, the lead frame 100 includes at least two stages (e.g., a primary stage and a secondary stage) and a plurality of pins (e.g., pin 1 to lead Pin 7), wherein one of the at least two slide stages is connected to at least three of the plurality of pins simultaneously.

In the lead frame 100 for chip packaging according to the present creative embodiment, since there are at least two wafer stages, at least two wafers can be integrated and packaged; since one wafer stage is connected to at least three pins at the same time, it can Increase chip heat dissipation channels (at least three pins dissipate heat at the same time) and improve chip working electrical performance (at least three pins conduct work at the same time), which can be adapted to power chips of various specifications (including ultra-high power chips).

As shown in FIGS. 1A and 1B , in some embodiments, one pin is connected to each of the at least two stages other than the stage to which at least three pins are connected simultaneously. In this way, both the function of pins and the fixing function of the carrier table can be taken into account, the space occupied by the pins can be saved, the loading area of the carrier table can be increased, and it can be adapted to single-chip and multi-chip loading; at the same time, it can help improve the heat dissipation capacity of the lead frame and improve chip lifetime.

As shown in FIGS. 1A and 1B , in some embodiments, at least two slide stages are on the same plane as the plurality of pins. In this way, the bonding wire connection between each chip carrier and the pins can be made simple and smooth, thereby significantly improving the yield rate of the chip package.

As shown in FIGS. 1A and 1B , in some embodiments, the plane on which at least two slide stages lie is a sunken plane relative to the plane on which the plurality of pins lie. In this way, each load connected can be reduced The length of the line arc between the chip mounted on the chip stage and the pins can significantly improve the yield rate of the chip package.

As shown in FIGS. 1A and 1B , in some embodiments, the distance between adjacent ones of at least two slide stages is greater than or equal to 0.2 mm. In this way, the area of the loading table can be maximized while meeting the manufacturing process requirements of the lead frame, and the range of wafer type selection and the number of loaded wafers can be expanded. At the same time, after the chip package is completed, it can adapt to a safe distance and withstand a voltage capability of more than 1KV.

1A and 1B, in some embodiments, the plurality of pins 1, 2, 3, 4, 5, 6, 7 includes at least one high voltage pin on the same side of at least two slide stages 81, 82 (e.g., pin 7) and at least one low-voltage pin (e.g., pins 5 and 6), and each of the at least one high-voltage pin is adjacent to the high-voltage pin of the at least one low-voltage pin The distance G1 between the low-voltage pins is larger than the distance G2 between any two adjacent low-voltage pins in at least one low-voltage pin. In this way, sparking problems between high-voltage and low-voltage pins can be prevented under certain application conditions, especially in humid environments, thereby ensuring the reliability and safety of the chip package structure device.

As shown in FIGS. 1A and 1B , in some embodiments, the plurality of pins 1 , 2 , 3 , 4 , 5 , 6 , 7 also includes a plurality of high voltage pins located on the same side of at least two stages 81 , 82 . pins (for example, pins 1 to 4). In this way, special pin position requirements can be met.

0.125mm的圓弧，整體長度L

0.5mm，該設計可在不犧牲裝片面積的前提下最大化載片台與塑封料間的互鎖，提升晶片封裝的可靠性。 As shown in FIGS. 1A and 1B , in some embodiments, one or more of the at least two slide stages 81, 82 (for example, sub-stages) are provided with locking holes (for example, oval Shape lock hole 820). In this way, the interlock between the lead frame 100 and the molding compound can be effectively enhanced, thereby greatly improving the reliability of the chip package. For example, the ends of an oval lockhole on the substage are R

0.125mm arc, overall length L

0.5mm, this design can maximize the interlock between the loading stage and the molding compound without sacrificing the loading area, and improve the reliability of chip packaging.

As shown in FIGS. 1A and 1B , in some embodiments, at least one of the upper left corner, lower left corner, upper right corner, and lower right corner of each of the at least two slide stages 81, 82 is made Cut corner processing. In this way, failures such as wire collapse and wire punching caused by the filling of plastic encapsulants during internal wire connection and processing can be effectively controlled, thereby greatly improving the yield rate of chip packaging.

As shown in FIGS. 1A and 1B , in some embodiments, each of the lead frame 100 Pins 1, 2, 3, 4, 5, 6, and 7 are all provided with locking glue holes 11, 21 31 41 51, 61, 71 (for example, each pin is provided with a round locking glue hole at the end). In this way, the interlock between the lead frame 100 and the molding compound can be effectively enhanced, and the ability of the chip package to resist internal stress and external moisture interference can be improved. For example, the circular locking holes 11, 21 31 41 51, 61, 71 on each pin 1, 2, 3, 4, 5, 6, 7 can adopt the size of R=0.125mm, which can make the plastic package While the material flows smoothly, it meets the process and manufacturing requirements of the lead frame.

As shown in FIGS. 1A and 1B , in some embodiments, the gap between each of the at least two slide stages 81 , 82 and the pin adjacent thereto is 0.2 mm. In this way, the area of the loading table can be maximized while meeting the manufacturing process requirements of the lead frame, and the range of wafer type selection and the number of loaded wafers can be expanded.

FIG. 2 shows a view of the silvered area of the lead frame 100 shown in FIGS. 1A and 1B . As shown in FIG. 2 , in some embodiments, the silver-plated area 101 of the lead frame 100 is partially selectively silver-plated, thereby retaining the reliable combination of the original bare copper material of the lead frame 100 and the plastic encapsulant in areas where no wire bonding is required. , can greatly improve the reliability of chip packaging. For example, the main carrier table 81 is partially silver-plated 811 to meet the space requirements for grounding wire bonding; the four external pins 1, 2, 3, and 4 of the main carrier table 81 are not plated with silver 812 to enhance the contact between the plastic molding compound and The combination between the loading stages, while minimizing the possibility of external moisture penetrating into the device through pins 1, 2, 3, and 4; the sub-mounting stage 82 is silver-plated with 821, and ground wire space is reserved around the loading stage , taking into account the needs of chip packaging expansion; the central area of the sub-stage 82 is not plated with silver 822 in a large area to enhance the combination between the molding compound and the stage; the independent pins 5, 6, which are not connected to any stage 7. Fully silver-plated 823 to maximize the pin bonding area.

FIG. 3 shows a schematic diagram of the arrangement of half-etched circular locking glue holes 814 , 824 on the backs of the two slide stages 81 , 82 of the lead frame 100 shown in FIGS. 1A and 1B . As shown in FIG. 3 , in some embodiments, circular half-etched locking glue holes 814, 824 may be configured on the backs of the two carrier stages 81, 82 of the lead frame 100, which can effectively enhance the interlock between the lead frame and the molding compound. Therefore, the reliability of chip packaging is greatly improved.

FIG. 4 shows a schematic structural view of the lead frame 100 shown in FIGS. 1A and 1B after the power chip and the main control chip are mounted on it. As shown in Figure 4, the master wafer positioned on the sub-stage 82 92 is interconnected with the power chips 91 and pins on the same stage and on the main stage 81 through welding wires (connection lines as shown in the figure), and the corresponding functional circuits are formed after the internal circuits are connected.

FIG. 5 shows a schematic diagram of an example functional pin configuration of a chip package structure device 93 employing the lead frame 100 shown in FIGS. 1A and 1B . FIG. 6 shows a schematic structural diagram of an example application circuit 94 using the chip package structure device 93 shown in FIG. 5 . It has been verified that the chip package structure device using the lead frame 100 according to the embodiment of the invention has good electrical performance and heat dissipation performance surpassing similar products, can improve the reliability and service life of electronic products, and can significantly reduce the application cost of electronic products .

Those skilled in the art should understand that the lead frame 100 may include, for example, 3, 4 or more chip stages according to actual needs, and may include, for example, 8, 9, 10 or more stages according to actual needs. Multiple pins or include, for example, 4, 5, 6 or fewer pins.

In summary, the lead frame for chip packaging and the chip packaging structure device according to the embodiment of the present invention have the advantages of low cost, high integration, multi-chip structure, and high heat dissipation performance. In addition, in the lead frame and chip packaging structure device for chip packaging according to the embodiment of the invention, multiple control chips and power chips can be sealed at the same time to form a high-efficiency, low-cost, high-reliability packaging structure; high-voltage pins and The distance between the low-voltage pins is large, which can prevent sparking problems between adjacent pins (especially high-voltage and low-voltage pins) under certain application conditions, especially in humid environments, so as to ensure the reliability of the chip package structure device and security.

This creation can be realized in other specific forms without departing from its spirit and essential characteristics. The current embodiments are to be considered in all respects as illustrative rather than restrictive, and the scope of the present creation is defined by the appended claims rather than the above description, and what falls within the meanings and equivalents of the claims All changes are included within the scope of this work.

1,2,3,4,5,6,7: pins

100: lead frame

11,21 31 41 51,61,71: Lock glue hole

81: Main loading stage

82: Secondary main stage

820: Oval lock glue hole

Claims (15)

A lead frame for chip packaging, characterized in that it includes at least two chip stages and a plurality of pins, wherein one of the at least two chip stages is simultaneously connected to one of the plurality of pins of at least three pins. The lead frame according to claim 1, wherein each of the at least two chip stages different from the stage connected to the at least three pins at the same time is connected to one of the plurality of pins a pin. The lead frame according to claim 1, wherein the at least two chip stages are located on the same plane as the plurality of pins. The lead frame according to claim 1, wherein the plane where the at least two slide stages are located is a sunken plane relative to the plane where the plurality of pins are located. The lead frame according to claim 1, wherein the distance between adjacent ones of the at least two wafer stages is greater than or equal to 0.2mm. The lead frame according to claim 1, wherein the plurality of pins include at least one high-voltage pin and at least one low-voltage pin located on the same side of the at least two slide stages, and the at least one high-voltage pin The distance between each high-voltage pin in the pin and the low-voltage pin adjacent to the high-voltage pin in the at least one low-voltage pin is greater than any two adjacent low-voltage pins in the at least one low-voltage pin Spacing between feet. The lead frame according to claim 6, wherein the plurality of pins further include a plurality of high voltage pins located on the same side of the at least two slide stages. The lead frame according to claim 1, wherein one or more of the at least two loading stages are provided with locking glue holes. The lead frame according to claim 1, wherein at least one of the upper left corner, lower left corner, upper right corner, and lower right corner of each of the at least two loading stages is corner-cut . The lead frame according to claim 1, wherein each pin of the plurality of pins is provided with a locking glue hole. The lead frame according to claim 1, wherein the back side of the lead frame is provided with a half-etched glue hole. The lead frame according to claim 1, wherein each of the at least two wafer stages is partially silver-plated. The lead frame according to claim 1, wherein, among the plurality of pins, independent pins not connected to any stage are fully silver-plated. The lead frame according to claim 1, wherein the gap between each of the at least two chip stages and the adjacent lead is 0.2mm. A chip package structure device, characterized by comprising the lead frame described in any one of Claims 1 to 13.

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