TWM634451U - Lead frame for chip package and chip package structure device - Google Patents
Lead frame for chip package and chip package structure device Download PDFInfo
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- TWM634451U TWM634451U TW111206103U TW111206103U TWM634451U TW M634451 U TWM634451 U TW M634451U TW 111206103 U TW111206103 U TW 111206103U TW 111206103 U TW111206103 U TW 111206103U TW M634451 U TWM634451 U TW M634451U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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Abstract
提供了用於晶片封裝的引線框架和晶片封裝結構裝置。該用於晶片封裝的引線框架包括至少兩個載片台和多個引腳,其中,該至少兩個載片台中的一個載片台同時連接該多個引腳中的至少三個引腳。 A lead frame for chip packaging and a chip package structural device are provided. The lead frame for chip packaging includes at least two chip stages and a plurality of pins, wherein one of the at least two chip stages is connected to at least three pins of the plurality of pins at the same time.
Description
本創作涉及積體電路領域,尤其涉及一種用於晶片封裝的引線框架和晶片封裝結構裝置。 The invention relates to the field of integrated circuits, in particular to a lead frame for chip packaging and a chip packaging structural device.
積體電路晶片(簡稱晶片)是把一定數量的常用電子元件(例如,電阻、電容、電晶體等)以及這些元件之間的連線通過半導體工藝集成在半導體晶片或介質基片上,然後封裝在一個管殼內形成的微型結構。積體電路晶片具有體積小、重量輕、引出線和焊接點少、壽命長、可靠性高、性能好等優點,同時成本低、便於大規模生產。 An integrated circuit chip (referred to as chip) is to integrate a certain number of commonly used electronic components (such as resistors, capacitors, transistors, etc.) A microstructure formed within a package. Integrated circuit chips have the advantages of small size, light weight, fewer lead wires and soldering points, long life, high reliability, and good performance. At the same time, they are low in cost and easy to mass produce.
積體電路晶片不僅在民用電子設備(例如,收錄機、電視機、電腦等)方面得到廣泛的應用,同時在軍事、通訊、遙控等方面也得到廣泛的應用。用積體電路晶片來裝配電子設備,其裝配密度比電晶體可提高幾十倍至幾千倍,電子設備的穩定工作時間也可大大提高。 Integrated circuit chips are not only widely used in civilian electronic equipment (such as radio recorders, televisions, computers, etc.), but also in military affairs, communications, and remote control. Using integrated circuit chips to assemble electronic equipment, its assembly density can be increased by tens to thousands of times compared with transistors, and the stable working time of electronic equipment can also be greatly improved.
根據本創作實施例的用於晶片封裝的引線框架,包括至少兩個載片台和多個引腳,其中,該至少兩個載片台中的一個載片台同時連接該多個引腳中的至少三個引腳。 A lead frame for chip packaging according to an embodiment of the present invention includes at least two chip stages and a plurality of pins, wherein one of the at least two chip stages is connected to one of the plurality of pins at the same time At least three pins.
根據本創作實施例的晶片封裝結構裝置,包括上述用於晶片封裝的引線框架。 A chip package structure device according to an embodiment of the present invention includes the above-mentioned lead frame for chip package.
1,2,3,4,5,6,7:引腳 1,2,3,4,5,6,7: pins
100:引線框架 100: lead frame
11,21 31 41 51,61,71:鎖膠孔 11,21 31 41 51,61,71: Lock glue hole
81:主載片台 81: Main loading stage
82:次主載片台 82: Secondary main stage
811,821:鍍銀 811,821: silver plating
812,822:不鍍銀 812,822: not silver plated
820:橢圓形鎖膠孔 820: Oval lock glue hole
823:全鍍銀 823: full silver plating
814,824:半蝕刻圓形鎖膠孔 814,824: Semi-etched circular locking hole
G1,G2:間距 G1, G2: spacing
93:晶片封裝結構裝置 93: Chip packaging structure device
94:晶片封裝結構裝置的應用電路 94: Application circuit of chip package structure device
從下面結合圖式對本創作的具體實施方式的描述中可以更好地理解本創作,其中: 圖1A和1B分別示出了根據本創作實施例的用於晶片封裝的引線框架的俯視圖和側面圖。 This creation can be better understood from the following description of the specific implementation manner of this creation in conjunction with the drawings, wherein: 1A and 1B show top and side views, respectively, of a lead frame for a die package according to an embodiment of the invention.
圖2示出了圖1A和1B所示的引線框架的鍍銀區域圖。 FIG. 2 shows a view of the silver plated area of the lead frame shown in FIGS. 1A and 1B .
圖3示出了圖1A和1B所示的引線框架中的載片台背面的半蝕刻圓形鎖膠孔佈置的示意圖。 FIG. 3 shows a schematic diagram of the arrangement of half-etched circular locking holes on the back of the carrier stage in the lead frame shown in FIGS. 1A and 1B .
圖4示出了圖1A和1B所示的引線框架上裝貼功率晶片和主控晶片後的結構示意圖。 FIG. 4 shows a schematic structural view of the lead frame shown in FIGS. 1A and 1B after mounting a power chip and a main control chip.
圖5示出了採用圖1A和1B所示的引線框架的晶片封裝結構裝置的示例功能腳位元配置的示意圖。 FIG. 5 shows a schematic diagram of an example functional pin configuration of a chip package structure device employing the lead frame shown in FIGS. 1A and 1B .
圖6示出了採用圖5所示的晶片封裝結構裝置的示例應用電路的結構示意圖。 FIG. 6 shows a schematic structural diagram of an example application circuit using the chip package structure device shown in FIG. 5 .
下面將詳細描述本創作的各個方面的特徵和示例性實施例。在下面的詳細描述中,提出了許多具體細節,以便提供對本創作的全面理解。但是,對於本領域技術人員來說很明顯的是,本創作可以在不需要這些具體細節中的一些細節的情況下實施。下面對實施例的描述僅僅是為了通過示出本創作的示例來提供對本創作的更好的理解。本創作決不限於下面所提出的任何具體配置,而是在不脫離本創作的精神的前提下覆蓋了元素和部件的任何修改、替換和改進。在圖式和下面的描述中,沒有示出公知的結構和技術,以便避免對本創作造成不必要的模糊。另外,需要說明的是,這裡使用的用語“A與B連接”可以表示“A與B直接連接”也可以表示“A與B經由一個或多個其他元件間接連接”。 Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the invention by showing an example of the invention. The invention is in no way limited to any specific configuration set forth below, but rather covers any modifications, substitutions and improvements of elements and parts without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention. In addition, it should be noted that the term "A is connected to B" used herein may mean "A and B are directly connected" or "A and B are indirectly connected via one or more other elements".
一般,積體電路晶片的製造過程主要包括以下幾個階段:積體電路晶片的設計階段、積體電路晶片的製作階段、積體電路晶片的封裝階段、以及積體電路晶片的測試階段。當積體電路晶片製作完成後,積體電路晶片上通常有多個焊墊。在積體電路晶片的封裝階段,通常會把積體電路晶片上的這些焊墊與對應的引線框架互相電連接。積體電路晶片通常 是通過焊線或者以植球結合的方式連接到引線框架上,使得積體電路晶片的這些焊墊與引線框架的接點電連接,從而實現積體電路晶片的封裝結構內部的電氣連接。 Generally, the manufacturing process of the IC chip mainly includes the following stages: the design stage of the IC chip, the manufacturing stage of the IC chip, the packaging stage of the IC chip, and the testing stage of the IC chip. After the integrated circuit chip is fabricated, there are usually a plurality of solder pads on the integrated circuit chip. During the packaging stage of the integrated circuit chip, these pads on the integrated circuit chip are usually electrically connected to the corresponding lead frames. Integrated circuit chips are usually The bonding pads of the integrated circuit chip are electrically connected to the contacts of the lead frame by bonding wires or ball bonding to the lead frame, thereby realizing the electrical connection inside the packaging structure of the integrated circuit chip.
隨著高集成度的多晶片合封類積體電路晶片越來越多地被使用,如何實現多個晶片的高集成度且高散熱性能的可靠封裝成為半導體行業普遍關心的問題。因此,提出了根據本創作實施例的用於晶片封裝的引線框架和晶片封裝結構裝置。 With the increasing use of highly integrated multi-chip packaged integrated circuit chips, how to realize reliable packaging of multiple chips with high integration and high heat dissipation performance has become a common concern in the semiconductor industry. Therefore, a lead frame for a chip package and a chip package structure device according to an embodiment of the present invention are proposed.
圖1A和1B分別示出了根據本創作實施例的用於晶片封裝的引線框架100的俯視圖和側面圖。如圖1A和1B所示,在一些實施例中,引線框架100包括至少兩個載片台(例如,主載片台和次載片台)以及多個引腳(例如,引腳1至引腳7),其中,該至少兩個載片台中的一個載片台同時連接該多個引腳中的至少三個引腳。
1A and 1B show a top view and a side view, respectively, of a
在根據本創作實施例的用於晶片封裝的引線框架100中,由於存在至少兩個載片台,所以可以集成封裝至少兩個晶片;由於一個載片台同時連接至少三個引腳,所以可以增加晶片散熱通道(至少三個引腳同時散熱)並提高晶片工作電性能(至少三個引腳同時傳導工作),可適配各種規格的功率晶片(包括超高功率晶片)。
In the
如圖1A和1B所示,在一些實施例中,至少兩個載片台中不同於同時連接至少三個引腳的載片台的每個載片台連接一個引腳。這樣,可兼顧引腳功能及載片台固定作用,節約引腳佔用空間、提升載片台裝片面積,可適配單晶片及多晶片裝片;同時可輔助提升引線框架的散熱能力,提高晶片的使用壽命。 As shown in FIGS. 1A and 1B , in some embodiments, one pin is connected to each of the at least two stages other than the stage to which at least three pins are connected simultaneously. In this way, both the function of pins and the fixing function of the carrier table can be taken into account, the space occupied by the pins can be saved, the loading area of the carrier table can be increased, and it can be adapted to single-chip and multi-chip loading; at the same time, it can help improve the heat dissipation capacity of the lead frame and improve chip lifetime.
如圖1A和1B所示,在一些實施例中,至少兩個載片台與多個引腳位於同一平面上。這樣,可使每個載片台與引腳之間的焊線連接簡單順暢,從而可明顯提升晶片封裝的良品率。 As shown in FIGS. 1A and 1B , in some embodiments, at least two slide stages are on the same plane as the plurality of pins. In this way, the bonding wire connection between each chip carrier and the pins can be made simple and smooth, thereby significantly improving the yield rate of the chip package.
如圖1A和1B所示,在一些實施例中,至少兩個載片台所在的平面相對於多個引腳所在的平面是下沉平面。這樣,可降低連接每個載 片台上裝貼的晶片與引腳之間的線弧長度,從而可明顯提升晶片封裝的良品率。 As shown in FIGS. 1A and 1B , in some embodiments, the plane on which at least two slide stages lie is a sunken plane relative to the plane on which the plurality of pins lie. In this way, each load connected can be reduced The length of the line arc between the chip mounted on the chip stage and the pins can significantly improve the yield rate of the chip package.
如圖1A和1B所示,在一些實施例中,至少兩個載片台中的相鄰載片台之間的間距大於等於0.2mm。這樣,可在滿足引線框架的製作工藝要求的同時最大化載片台的面積,拓展晶片選型範圍及裝片數量。同時,在晶片封裝完成後,可適應安全距離耐壓能力在1KV以上。 As shown in FIGS. 1A and 1B , in some embodiments, the distance between adjacent ones of at least two slide stages is greater than or equal to 0.2 mm. In this way, the area of the loading table can be maximized while meeting the manufacturing process requirements of the lead frame, and the range of wafer type selection and the number of loaded wafers can be expanded. At the same time, after the chip package is completed, it can adapt to a safe distance and withstand a voltage capability of more than 1KV.
如圖1A和1B所示,在一些實施例中,多個引腳1,2,3,4,5,6,7包括位於至少兩個載片台81,82同一側的至少一個高壓引腳(例如,引腳7)和至少一個低壓引腳(例如,引腳5和6),並且至少一個高壓引腳中的每個高壓引腳與至少一個低壓引腳中與該高壓引腳相鄰的低壓引腳之間的間距G1大於至少一個低壓引腳中的任意兩個相鄰的低壓引腳之間的間距G2。這樣,可預防某些應用條件尤其是潮濕環境下高壓與低壓引腳間的打火問題,從而保證晶片封裝結構裝置的可靠性和安全性。
1A and 1B, in some embodiments, the plurality of
如圖1A和1B所示,在一些實施例中,多個引腳1,2,3,4,5,6,7還包括位於至少兩個載片台81,82同一側的多個高壓引腳(例如,引腳1至4)。這樣,可滿足特殊腳位需求設置。
As shown in FIGS. 1A and 1B , in some embodiments, the plurality of
如圖1A和1B所示,在一些實施例中,至少兩個載片台81,82中的一個或多個載片台(例如,次載片台)上設置有鎖膠孔(例如,橢圓形鎖膠孔820)。這樣,可有效增強引線框架100與塑封料間的互鎖,從而大大提高晶片封裝的可靠性。例如,次載片台上的橢圓形鎖膠孔的兩端為R0.125mm的圓弧,整體長度L0.5mm,該設計可在不犧牲裝片面積的前提下最大化載片台與塑封料間的互鎖,提升晶片封裝的可靠性。
As shown in FIGS. 1A and 1B , in some embodiments, one or more of the at least two slide stages 81, 82 (for example, sub-stages) are provided with locking holes (for example, oval Shape lock hole 820). In this way, the interlock between the
如圖1A和1B所示,在一些實施例種,至少兩個載片台81,82中的每個載片台的左上角、左下角、右上角、以及右下角中的至少一個角部做了切角處理。這樣,可有效控制內部焊線連接時和加工過程中的塑封料充填導致的塌絲、沖絲等失效,從而大大提高晶片封裝的良品率。 As shown in FIGS. 1A and 1B , in some embodiments, at least one of the upper left corner, lower left corner, upper right corner, and lower right corner of each of the at least two slide stages 81, 82 is made Cut corner processing. In this way, failures such as wire collapse and wire punching caused by the filling of plastic encapsulants during internal wire connection and processing can be effectively controlled, thereby greatly improving the yield rate of chip packaging.
如圖1A和1B所示,在一些實施例中,引線框架100的每個
引腳1,2,3,4,5,6,7均配置有鎖膠孔11,21 31 41 51,61,71(例如,每個引腳的尾端設置有圓形鎖膠孔)。這樣,可有效增強引線框架100與塑封料間的互鎖,提升晶片封裝抵抗內部應力及外部潮氣干擾的能力。例如,每個引腳1,2,3,4,5,6,7上的圓形鎖膠孔11,21 31 41 51,61,71可採用R=0.125mm的尺寸,該尺寸可使塑封料順暢流過的同時滿足引線框架的工藝製造要求。
As shown in FIGS. 1A and 1B , in some embodiments, each of the
如圖1A和1B所示,在一些實施例中,至少兩個載片台81,82中的每個載片台和與其相鄰的引腳之間的間隙為0.2mm。這樣,可在滿足引線框架的製作工藝要求的同時最大化載片台的面積,拓展晶片選型範圍及裝片數量。 As shown in FIGS. 1A and 1B , in some embodiments, the gap between each of the at least two slide stages 81 , 82 and the pin adjacent thereto is 0.2 mm. In this way, the area of the loading table can be maximized while meeting the manufacturing process requirements of the lead frame, and the range of wafer type selection and the number of loaded wafers can be expanded.
圖2示出了圖1A和1B所示的引線框架100的鍍銀區域圖。如圖2所示,在一些實施例中,引線框架100的鍍銀區域101採用局部選擇性鍍銀,從而在不需要實施打線的區域保留引線框架100原本的裸銅材質與塑封料的可靠結合,可大大提升晶片封裝的可靠性。例如,主載片台81局部鍍銀811,以滿足接地線打線空間需求;主載片台81外連的四個引腳1,2,3,4區域不鍍銀812,以增強塑封料與載片台間的結合,同時最大化降低外部潮氣通過引腳1,2,3,4向器件內部滲透的可能;次載片台82環鍍銀821,載片台四周均預留接地線空間,兼顧晶片封裝拓展的需求;次載片台82的中央區域大面積不鍍銀822,以增強塑封料與載片台間的結合;不與任何載片台連接的獨立引腳5,6,7全鍍銀823,以最大化引腳打線區。
FIG. 2 shows a view of the silvered area of the
圖3示出了圖1A和1B所示的引線框架100的兩個載片台81,82背面的半蝕刻圓形鎖膠孔814,824佈置的示意圖。如圖3所示,在一些實施例中,引線框架100的兩載片台81,82背面可以配置有圓形半蝕刻鎖膠孔814,824,這樣可有效增強引線框架與塑封料間的互鎖,從而大大提高晶片封裝的可靠性。
FIG. 3 shows a schematic diagram of the arrangement of half-etched circular
圖4示出了圖1A和1B所示的引線框架100上裝貼功率晶片和主控晶片後的結構示意圖。如圖4所示,位於次載片台82上的主制晶片
92通過焊接線分別與同載片台及位於主載片台81上的功率晶片91和引腳互連(如圖上所示的連線),內部電路連接後形成對應的功能電路。
FIG. 4 shows a schematic structural view of the
圖5示出了採用圖1A和1B所示的引線框架100的晶片封裝結構裝置93的示例功能腳位元配置的示意圖。圖6示出了採用圖5所示的晶片封裝結構裝置93的示例應用電路94的結構示意圖。經過驗證,採用根據本創作實施例的引線框架100的晶片封裝結構裝置具有超越同類產品的良好電氣性能和散熱性能,可提升電子產品的可靠性和應用壽命,同時可明顯降低電子產品的應用成本。
FIG. 5 shows a schematic diagram of an example functional pin configuration of a chip
本領域技術人員應該明白的是,引線框架100可根據實際需要包括例如,3個、4個或更多個載片台,並且可根據實際需要包括例如,8個、9個、10個或更多個引腳或包括例如,4個、5個、6個或更少數目的引腳。
Those skilled in the art should understand that the
綜上所述,根據本創作實施例的用於晶片封裝的引線框架和晶片封裝結構裝置具有低成本、高集成度、多晶片結構、以及高散熱性能等優點。另外,在根據本創作實施例的用於晶片封裝的引線框架和晶片封裝結構裝置中,可同時封入多顆控制晶片及功率晶片,形成高效、低成本、高可靠性封裝結構;高壓引腳和低壓引腳之間的間距較大,可以預防某些應用條件尤其是潮濕環境下相鄰引腳(特別是高壓與低壓引腳)間的打火問題,從而可以保證晶片封裝結構裝置的可靠性和安全性。 In summary, the lead frame for chip packaging and the chip packaging structure device according to the embodiment of the present invention have the advantages of low cost, high integration, multi-chip structure, and high heat dissipation performance. In addition, in the lead frame and chip packaging structure device for chip packaging according to the embodiment of the invention, multiple control chips and power chips can be sealed at the same time to form a high-efficiency, low-cost, high-reliability packaging structure; high-voltage pins and The distance between the low-voltage pins is large, which can prevent sparking problems between adjacent pins (especially high-voltage and low-voltage pins) under certain application conditions, especially in humid environments, so as to ensure the reliability of the chip package structure device and security.
本創作可以以其他的具體形式實現,而不脫離其精神和本質特徵。當前的實施例在所有方面都被看作是示例性的而非限定性的,本創作的範圍由所附請求項而非上述描述定義,並且落入請求項的含義和等同物的範圍內的全部改變都被包括在本創作的範圍中。 This creation can be realized in other specific forms without departing from its spirit and essential characteristics. The current embodiments are to be considered in all respects as illustrative rather than restrictive, and the scope of the present creation is defined by the appended claims rather than the above description, and what falls within the meanings and equivalents of the claims All changes are included within the scope of this work.
1,2,3,4,5,6,7:引腳 1,2,3,4,5,6,7: pins
100:引線框架 100: lead frame
11,21 31 41 51,61,71:鎖膠孔 11,21 31 41 51,61,71: Lock glue hole
81:主載片台 81: Main loading stage
82:次主載片台 82: Secondary main stage
820:橢圓形鎖膠孔 820: Oval lock glue hole
Claims (15)
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CN202220616501.2U CN218039185U (en) | 2022-03-21 | 2022-03-21 | Lead frame for chip packaging and chip packaging structure device |
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