TWM622448U - Inductors structure - Google Patents
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- TWM622448U TWM622448U TW110209465U TW110209465U TWM622448U TW M622448 U TWM622448 U TW M622448U TW 110209465 U TW110209465 U TW 110209465U TW 110209465 U TW110209465 U TW 110209465U TW M622448 U TWM622448 U TW M622448U
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本創作係有關一種電感結構,尤指一種可嵌埋於封裝基板中之基板型電感(Substrate-based Inductor)之複數組併列串聯之線圈電感結構。 The present invention relates to an inductance structure, especially a coil inductance structure consisting of a plurality of parallel and series-connected substrate-based inductors that can be embedded in a package substrate.
一般半導體應用裝置,例如通訊或高頻半導體裝置中,常需要將電阻器、電感器、電容器及振盪器(oscillator)等多數射頻(radio frequency)被動元件電性連接至所封裝之半導體晶片,俾使該半導體晶片具有特定之電流特性或發出訊號。例如:傳統電感有諸多之種類,有其各種應用(濾波、扼流、DC-DC converter等,但不限於上述)及其優劣勢。 In general semiconductor application devices, such as communication or high-frequency semiconductor devices, it is often necessary to electrically connect most passive components of radio frequency (radio frequency), such as resistors, inductors, capacitors and oscillators, to the packaged semiconductor chips, so that Make the semiconductor chip have a specific current characteristic or send out a signal. For example, there are many types of traditional inductors, with their various applications (filtering, choke, DC-DC converter, etc., but not limited to the above) and their advantages and disadvantages.
以常用於具有射頻模組之裝置中的螺旋電感元件為例,在射頻模組高密度元件配置及微型化的需求下,縮小了各個元件之間的距離,同時也造成各個元件之間的容易產生電磁干擾,因此,如何避免各個元件之間的電磁干擾,且電感元件如何提供更佳的磁遮罩性、防電磁干擾的能力及電感元件本身的微型化,乃傳統的電感元件所面臨的問題。 Taking the spiral inductance element commonly used in devices with RF modules as an example, under the requirement of high-density component configuration and miniaturization of RF modules, the distance between each component is reduced, and it also makes it easier for each component. Electromagnetic interference is generated. Therefore, how to avoid electromagnetic interference between various components, and how to provide better magnetic shielding, anti-electromagnetic interference capability, and miniaturization of the inductive component itself are the challenges faced by traditional inductive components. problem.
又,螺旋電感元件在高頻應用時,如何提供較低的磁性損耗與渦流效應及較高的電感值,以得到較佳的Q值,進而降低電感元件能耗並提升效能,俾達到良好的電性,亦為傳統的電感元件另一個不斷要克服的課題。 In addition, how to provide lower magnetic loss and eddy current effect and higher inductance value of spiral inductance element in high frequency application, so as to obtain a better Q value, thereby reducing the energy consumption of the inductive element and improving the performance, so as to achieve a good Electricity is another problem that traditional inductance components have to overcome constantly.
基於上述問題,業界如TWI611439專利(如圖1所示)之使用磁性包覆件130提供磁遮罩及防電磁干擾能力,但於絕緣材中混合磁性粉末後其導磁率比起原磁性粉末相對地較低,致使該混合物對電感元件於提高電感值及磁遮罩及防電磁干擾能力依然有所限制。
Based on the above problems, the industry such as the TWI611439 patent (as shown in FIG. 1 ) uses the
再者,於絕緣材中混合磁性粉末,該混合物之均勻性較差,導致難以控制導磁性,且磁性粉末於載板成型後,因其材料特性不宜進行線路圖案化製程,故後續無法於該介電層或該磁性包覆件上進行增層線路之製作。 Furthermore, when the magnetic powder is mixed in the insulating material, the uniformity of the mixture is poor, which makes it difficult to control the magnetic permeability. After the magnetic powder is formed on the carrier plate, it is not suitable for the circuit patterning process due to its material properties, so it cannot be used in the subsequent process. The build-up circuit is fabricated on the electrical layer or the magnetic coating.
又,TWI611439專利之線圈元件100因採用射出成型、轉注成型或低温共燒等方式製作,致使加工性不佳,因而僅只能進行小面積加工,無法大板面量產製作導致,電感之加工成本提高,且所製作出之線圈元件之幾何精度不佳,導致電感值之精度(Tolerance)不佳。
In addition, the
因此,如何克服上述習知技術之問題,實已成為目前業界亟待克服之課題。 Therefore, how to overcome the above-mentioned problems of the prior art has become an urgent issue to be overcome in the current industry.
有鑑於習知技術之問題,本創作提供一種電感結構,係包括:一絕緣體;複數電感線路,係由呈層狀間隔之多個線圈堆疊而埋設於該絕緣體中,且每層至少有二個併列而彼此未電性連接之線圈,其中,各該電感線路係至少一單圈螺旋狀線圈,且該電感線路之一最外層之線圈係彼此電性連接;複數牆狀之導電體,係埋設於該絕緣體中並連接任二相鄰間隔堆疊之該線圈;一第一導電柱,係埋設於該絕緣體中並電性連接該電感線路最底層之線圈,且該第一導電柱至少其中之一端面係露出於該絕緣體並連接一電性接觸墊;以及一第二導電柱, 係埋設於該絕緣體中並電性連接該電感線路最底層之線圈,且該第二導電柱至少其中之一端面係露出於該絕緣體並連接一電性接觸墊。 In view of the problems of the prior art, the present invention provides an inductance structure, which includes: an insulator; a plurality of inductance lines, which are stacked by a plurality of coils spaced in layers and buried in the insulator, and each layer has at least two Coils that are parallel but not electrically connected to each other, wherein each of the inductance lines is at least one single-turn spiral coil, and the outermost coils of one of the inductance lines are electrically connected to each other; a plurality of wall-shaped conductors are embedded in the insulator and connected to any two adjacently stacked coils; a first conductive column embedded in the insulator and electrically connected to the coil at the bottom layer of the inductance circuit, and at least one of the first conductive columns The end surface is exposed on the insulator and connected to an electrical contact pad; and a second conductive column, It is embedded in the insulator and is electrically connected to the coil on the bottom layer of the inductance circuit, and at least one end surface of the second conductive column is exposed to the insulator and connected to an electrical contact pad.
前述之電感結構中,該導電體之圖案形狀係對應該電感線路之局部弧形區段。 In the aforementioned inductor structure, the pattern shape of the conductor corresponds to a partial arc section of the inductor circuit.
前述之電感結構中,該導電體之圖案形狀係對應該電感線路之全部區段。 In the aforementioned inductor structure, the pattern shape of the conductor corresponds to all sections of the inductor circuit.
前述之電感結構中,該複數牆狀之導電體之部分層之各該導電體之圖案形狀係對應該電感線路之全部區段,而該複數牆狀之導電體之部分層之各該導電體之圖案形狀係對應該電感線路之局部區段。 In the above-mentioned inductor structure, the pattern shape of each of the conductors of the partial layers of the plurality of wall-shaped conductors corresponds to the entire section of the inductor circuit, and the conductors of the partial layers of the plurality of wall-shaped conductors The pattern shape corresponds to a local section of the inductor circuit.
前述之電感結構中,該複數電感線路之同層之線圈之圈身圖案形狀係呈兩個半圓形。 In the above-mentioned inductor structure, the shape of the coils of the coils on the same layer of the multiple inductor lines is two semicircles.
前述之電感結構中,該第一導電柱之截面形狀係對應所連接之該電性接觸墊之圖案形狀。 In the aforementioned inductor structure, the cross-sectional shape of the first conductive column corresponds to the pattern shape of the connected electrical contact pad.
前述之電感結構中,該第二導電柱之截面形狀係對應所連接之該電性接觸墊之圖案形狀。 In the aforementioned inductor structure, the cross-sectional shape of the second conductive column corresponds to the pattern shape of the connected electrical contact pad.
前述之電感結構中,復包括嵌埋於該絕緣體中之遮蔽層,其係由若干彼此間並未電性連接之導電線段組合而成,且該遮蔽層係至少遮蔽該複數電感線路之其中一外側面且未電性連接該電感線路。 In the above-mentioned inductor structure, a shielding layer embedded in the insulator is further included, which is composed of a plurality of conductive line segments that are not electrically connected to each other, and the shielding layer shields at least one of the plurality of inductive lines. The outer side is not electrically connected to the inductive circuit.
由上可知,本創作之電感結構,主要藉由該複數組併列且複數層電感線路串聯之螺旋狀線圈之設計,以提升電感值及品質因子,故相較於習知技術,本創作之電感結構無需使用習知導磁件及習知磁性粉末之混合物,即可滿足所需之要求,因而得以克服習知技術之種種缺失。 It can be seen from the above that the inductor structure of the present creation is mainly designed to improve the inductance value and quality factor through the design of the spiral coils with multiple parallel arrays and multiple layers of inductor lines in series. Therefore, compared with the prior art, the inductors of the present creation The structure can meet the required requirements without using the mixture of the conventional magnetic conductive member and the conventional magnetic powder, thus overcoming various deficiencies of the conventional technology.
100:線圈元件 100: Coil Components
130:磁性包覆件 130: Magnetic wrap
3:電感結構 3: Inductor structure
3a:電感本體 3a: Inductor body
20:絕緣體 20: Insulator
20a:第一側 20a: First side
20b:第二側 20b: Second side
22a,22b,32a,32b,32c,32d:電感線路 22a, 22b, 32a, 32b, 32c, 32d: Inductive lines
220,221,222,223:線圈 220, 221, 222, 223: Coils
221a,222a,223a:線圈組 221a, 222a, 223a: Coil Sets
23,33a,33b,43:導電體 23, 33a, 33b, 43: Conductors
24a:第一導電柱 24a: the first conductive column
24b:第二導電柱 24b: second conductive column
25a:第一電性接觸墊 25a: first electrical contact pad
25b:第二電性接觸墊 25b: second electrical contact pad
26:表面處理層 26: Surface treatment layer
27b:絕緣保護層 27b: Insulating protective layer
300:開口區 300: Open area
31a,31b:遮蔽層 31a, 31b: Masking layer
310:線段 310: Line segment
38:導接線路 38: Conductor line
320:起始點 320: starting point
321:第一中繼點 321: First relay point
322:第二中繼點 322: Second relay point
323:第三中繼點 323: Third relay point
324:第四中繼點 324: Fourth relay point
325:停止點 325: stop point
H:厚度 H: Thickness
t:距離 t: distance
圖1係為習知電感結構之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional inductor structure.
圖2係為本創作之電感結構之剖面示意圖。 FIG. 2 is a schematic cross-sectional view of the inductor structure of the present invention.
圖2-1係為圖2之另一態樣之剖面示意圖。 FIG. 2-1 is a schematic cross-sectional view of another aspect of FIG. 2 .
圖2A係為本創作之電感結構之另一實施例之剖面示意圖。 FIG. 2A is a schematic cross-sectional view of another embodiment of the inductor structure of the present invention.
圖2A-1係為圖2A之另一態樣之剖面示意圖。 2A-1 is a schematic cross-sectional view of another aspect of FIG. 2A.
圖2B係為本創作之電感結構之另一實施例之剖面示意圖。 FIG. 2B is a schematic cross-sectional view of another embodiment of the inductor structure of the present invention.
圖2B-1係為圖2B之另一態樣之剖面示意圖。 FIG. 2B-1 is a schematic cross-sectional view of another aspect of FIG. 2B .
圖3A係為圖2-1之絕緣體之其中一側之上視平面示意圖。 FIG. 3A is a schematic top plan view of one side of the insulator of FIG. 2-1 .
圖3B、圖3C及圖3D係為圖2之各層線圈之上視平面示意圖。 FIG. 3B , FIG. 3C and FIG. 3D are schematic top plan views of the coils of each layer of FIG. 2 .
圖3E係為圖2之絕緣體之另一側之下視平面示意圖。 FIG. 3E is a schematic bottom plan view of the other side of the insulator of FIG. 2 .
圖3F係為圖2之電感結構之另一側之下視平面示意圖。 FIG. 3F is a schematic bottom plan view of another side of the inductor structure of FIG. 2 .
圖3F-1至圖3F-4係為圖3A之其它態樣之上視平面示意圖。 3F-1 to 3F-4 are schematic top plan views of other aspects of FIG. 3A.
以下藉由特定的具體實施例說明本創作之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本創作之其他優點及功效。 The following specific embodiments are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本創作可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本創作所能產生之 功效及所能達成之目的下,均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本創作可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本創作可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of this creation. Therefore, it has no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size will not affect the production of this creation. The effect and the purpose that can be achieved should still fall within the scope that the technical content disclosed in this creation can cover. At the same time, the terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of implementation of this creation. Changes or adjustments to their relative relationships, provided that there is no substantial change in the technical content, shall also be regarded as the scope of the implementation of this creation.
圖2係為本創作之電感結構3之剖面示意圖。如圖2所示,所述之電感結構3係包括一絕緣體20、以及一埋設於該絕緣體20中之電感本體3a,且該電感本體3a係包含複數組(如圖2所示之左右兩組併列)電感線路32a,32b、及連接各組電感線路32a,32b之導接線路38。
FIG. 2 is a schematic cross-sectional view of the inductor structure 3 of the present invention. As shown in FIG. 2 , the inductance structure 3 includes an
所述之絕緣體20係具有相對之第一側20a與第二側20b。於本實施例中,該絕緣體20係為介電材,如ABF(Ajinomoto Build-up Film)、感光型樹脂、聚醯亞胺(Polyimide,簡稱PI)、雙馬來醯亞胺三嗪(Bismaleimide Triazine,簡稱BT)、FR5之預浸材(Prepreg,簡稱PP)、模壓樹脂(Molding Compound)、膜狀環氧模壓樹脂(Epoxy Molding Compound,簡稱EMC)或其它適當材質。該絕緣體20之較佳之材料為易於做線路加工之PI、ABF或EMC。
The
所述之電感線路32a,32b係立體螺旋狀線圈,其藉由多層(如三層)線圈221,222,223與導電體33a,33b係構成一立體(3D)架體,其中,該兩組電感線路32a,32b之線圈221係藉由該導接線路38串聯相接。
The
於本實施例中,該電感線路32a,32b之繞圈路徑係由圖3D所示之電感線路32a之線圈223之起始點320(即其中一接點)經過第一中繼點321與導電體33b來到圖3C所示之電感線路32a之線圈222,再經過第二中繼點322與導電體33a來到圖3B所示之電感線路32a之線圈221,再經過該導接線路38來到圖3B所示之另一電感線路32b之線圈221,之後,經過圖3B所示之另一電感線路32b之線圈221
之第三中繼點323與導電體33a來到圖3C所示之電感線路32b之線圈222,最後,經過圖3C所示之電感線路32b之線圈222之第四中繼點324與導電體33b回到圖3D所示之電感線路32b之線圈223而於其停止點325(即另一接點)結束,使各該電感線路32a,32b之同層之線圈221,222,223之圈身圖案形狀係呈如圖3B、圖3C及圖3D所示之兩個半圓形(即兩個類D形)。
In this embodiment, the winding paths of the
再者,該導電體33a,33b之圖案形狀係對應該電感線路32a,32b之線圈221,222,223之局部弧形區段。
Furthermore, the pattern shapes of the
應可理解地,該電感本體3a可依需求增設多組繞圈路徑之立體線圈,如圖2A所示之增厚型電感線路22a,22b,其中,各該電感線路22a,22b係將同一繞圈路徑定義為線圈組221a,222a,223a,且每一線圈組由多層線圈220藉由牆形導電體23相疊接而成。或者,亦可將所有線圈221,222,223以牆形導電體43疊接成一個厚度H更厚之電感線路32c,32d,如圖2B所示,且該導電體43之圖案形狀係對應該電感線路32c,32d之線圈221,222,223之全部區段。應可理解地,該導電體33a,33b,43之圖案形狀於同一電感本體3a中可依需求對應該線圈221,222,223之全部區段及/或局部區段,且有關該電感線路之厚度可依需求設計,並不限於上述。
It should be understood that the
所述之導電體33a,33b係疊架各層線圈221,222,223,使該些導電體33a,33b位於各層線圈221,222,223之間,以令該電感本體3a呈縱向立體線圈態樣。
The
於本實施例中,該導電體33a,33b係呈牆狀,其對應連接各該電感線路32a,32b之各層線圈221,222,223之區段,如圖3B至圖3D所示,故相較於習知技術用雷射開圓孔之導電盲孔或通孔之方式,更能取得大面積接觸該些電感線路32a,32b之需求。
In this embodiment, the
再者,該電感本體3a之兩接點(即起始點320與停止點325)係分別位於兩電感線路32a,32b之外端部,以作為輸入埠及輸出埠。例如,於該絕緣體20中埋設第一導電柱24a與第二導電柱24b,以令該第一導電柱24a連通該絕緣
體20之第二側20b與其中一電感線路32b以連接其中一接點(如圖3D所示之停止點325),且該第二導電柱24b連通該絕緣體20之第二側20b與另一電感線路32a以連接另一接點(如圖3D所示之起始點320)。應可理解地,該第一導電柱24a與第二導電柱24b可依需求連通該絕緣體20之第一側20a。
Furthermore, the two contacts (ie, the
又,該第一導電柱24a之端面係連接一設於該絕緣體20第二側20b上之第一電性接觸墊25a,且該第二導電柱24b之端面係連接一設於該絕緣體20第二側20b上之第二電性接觸墊25b,以令該第一與第二電性接觸墊25a,25b用以外接其它電子元件,該第一與第二電性接觸墊25a,25b可設於單側或兩側(如圖2及圖3A所示)。例如,該第一導電柱24a與第二導電柱24b係為實心不規則柱狀,且該第一導電柱24a與第二導電柱24b之截面形狀係對應所連接之第一與第二電性接觸墊25a,25b之圖案形狀,以接觸該第一與第二電性接觸墊25a,25b較多面積,藉以取得最大的導通面積。
In addition, the end surface of the first
另外,可於該第一與第二電性接觸墊25a,25b上形成一表面處理層26及/或焊錫材料,以利於接置其它電子元件,其中,形成該表面處理層26之材質係為鎳/金(Ni/Au)、鎳/鈀/金(Ni/Pd/Au)或有機保焊劑(OSP)等。例如,可於該絕緣體20之第二側20b上形成一絕緣保護層27b,並外露出該第一與第二電性接觸墊25a,25b或其上之表面處理層26,其中,形成該絕緣保護層27b之材質係為介電材、感光或非感光之有機絕緣材,如防焊材、ABF及EMC等。
In addition, a
應可理解地,可於該絕緣體20之第一側20a上形成另一絕緣保護層(圖略),且該另一絕緣保護層之材質係為介電材、感光或非感光之有機絕緣材,如防焊材、ABF及EMC等,但不限於上述。進一步,該絕緣保護層27b與該絕緣體20可為相同材質或不同材質,且為相同材質時,可簡化材料組合。
It should be understood that another insulating protective layer (not shown) can be formed on the
於另一態樣中,如圖2-1、圖2A-1及圖2B-1所示,可於該絕緣體20中嵌埋至少一遮蔽層31a,31b,其係由若干彼此間並未電性連接之導電線段310
(如圖3A及圖3B所示)組合而成,且該遮蔽層31a,31b係至少遮蔽該複數電感線路22a,22b,32a,32b,32c,32d之其中一外側面且未電性連接該電感線路。
In another aspect, as shown in FIGS. 2-1 , 2A-1 and 2B-1, at least one
所述之遮蔽層31a,31b係嵌埋於該絕緣體20之第一側20a及第二側20b中,以佈設於該電感本體3a之上下兩側而遮蔽該些電感線路22a,22b,32a,32b,32c,32d,且該遮蔽層31a,31b未電性連接該電感本體3a(或該電感線路32a,32b),其中,該遮蔽層31a,31b係包含複數不互相連接之線段310(如圖3A及圖3E所示),且各該線段310之間的距離t可相同或不相同。
The shielding layers 31a, 31b are embedded in the
於本實施例中,該遮蔽層31a,31b係以電鍍、濺鍍(Sputtering)或物理氣相沉積(Physical Vapor Deposition,簡稱PVD)等方式沉積而成,且該些線段310可為排設成圓形輪廓、多邊形輪廓(如圖3F-1所示)或其它輪廓等之圖案,亦可呈現輻射狀、多環狀(如圖3F-2所示)或其它形狀等。應可理解地,該線段310之圖案可為對稱形式(如圖3F-2或圖3F-3所示)或非對稱形式(如圖3F-4所示)。
In this embodiment, the shielding layers 31a and 31b are deposited by electroplating, sputtering or physical vapor deposition (PVD), and the
再者,該遮蔽層31a,31b係為導磁性材料,其包含鐵(Fe)、鎳(Ni)、鈷(Co)、錳(Mn)、鋅(Zn)或其合金,亦或其它等磁性物質。此外,亦可組合導磁材料及銅(Cu)等非磁性金屬以形該遮蔽層31a,31b,例如,先電鍍或化學鍍銅(Cu),再鍍上導磁材料,亦或先鍍上導磁層再鍍非磁性金屬。
Furthermore, the shielding
又,其中一遮蔽層31b未外露於該絕緣體20之第一側20a(如圖3F所示),而另一遮蔽層31a可外露於該絕緣體20之第一側20a,且於該絕緣體20之第一側20a上可形成絕緣保護層(圖略),以覆蓋該遮蔽層31a。例如,可藉由該遮蔽層31a凹陷於該第一側20a之設計,使該遮蔽層31a與該絕緣保護層之間具有較佳的結合力。
In addition, one of the shielding
因此,本創作之電感結構3主要藉由立體繞圈路徑形成該電感本體3a,使該些電感線路22a,22b,32a,32b,32c,32d產生多個開口區300,如圖3B至圖3D所示,以增加磁感應面積。
Therefore, the inductor structure 3 of the present invention mainly forms the
再者,該電感結構3在該電感本體3a之相對兩側之至少一側上形成一含有導磁材料之遮蔽層31a,31b,以覆蓋該些電感線路22a,22b,32a,32b,32c,32d,較佳者為形成一組相對之遮蔽層31a,31b,藉以降地電磁干擾效應,並增加抗電磁干擾效應的能力,以提升電感值及品質因子(或電感之Q值,即ωL/R,其中,ω代表頻率,L為電感,R為電感之電阻)。進一步,為了提高Q值,在各該電感線路22a,22b,32a,32b,32c,32d之層間之導通連接方式可採用微影圖案化電鍍金屬柱之方式製作該些導電體23,33a,33b,43,其形狀係對應各該電感線路22a,22b,32a,32b,32c,32d之孤形,如圖3B至圖3D所示,以獲取較寬之導電面積而降低電感的電阻R及較高的熱傳導性能。
Furthermore, the inductor structure 3 forms a
另外,該遮蔽層31a,31b可依電感值的需求選擇符合導磁率條件的導磁性材料。
In addition, the shielding
綜上所述,本創作之電感結構3,其可採用電路板(PCB)或載板的加工方式進行製作,以輕易地進行大板面量產,且採用無核心層(coreless)態樣之圖案化增層線路製法將導磁材料以電鍍或沈積方式形成,使該遮蔽層31a,31b之精度之控制極佳,故相較於習知技術,本創作之電感結構3之幾何圖案(如電感線路22a,22b,32a,32b,32c,32d之螺旋狀及遮蔽層31a,31b之圖案)之精度佳,且電感值之精度控制極佳。
To sum up, the inductor structure 3 of the present creation can be fabricated by the processing method of a circuit board (PCB) or a carrier board, so as to easily mass-produce a large board area, and it adopts a coreless form. The patterned build-up circuit method forms the magnetic conductive material by electroplating or deposition, so that the precision of the shielding layers 31a and 31b can be controlled extremely well. The spiral shapes of the
再者,由於可輕易地使用導磁材料及絕緣體知各層絕緣層進行圖案化線路製程,故該電感結構3有利於各種設計及應用。 Furthermore, since the patterned circuit process can be easily performed using magnetic conductive materials and insulating layers and insulating layers, the inductor structure 3 is beneficial to various designs and applications.
又,該遮蔽層31a,31b藉由不互相連接之線段310之設計,以提
升磁屏蔽效應及其抗電磁(EMI)干擾之能力,並可降低渦電流及磁損耗對Q值的影響。
In addition, the shielding
另外,相較於習知技術之鐵芯塊之配置,本創作之電感結構3之電感線路22a,22b,32a,32b,32c,32d之厚度可依需求調整而無需配置鐵芯塊,因而更易於微型化,以利於終端產品符合微小化之需求。應可理解地,相較於習知技術之磁粉介電層之配置,本創作之電感結構3之絕緣體20易於製作無需摻雜磁粉,因而更能降低製作成本,以利於終端產品符合經濟效益之需求。
In addition, compared with the configuration of the iron core blocks in the prior art, the thicknesses of the
上述實施例係用以例示性說明本創作之原理及其功效,而非用於限制本創作。任何熟習此項技藝之人士均可在不違背本創作之精神及範疇下,對上述實施例進行修改。因此本創作之權利保護範圍,應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Anyone skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present creation. Therefore, the protection scope of the rights of this creation should be listed in the patent application scope mentioned later.
3:電感結構 3: Inductor structure
3a:電感本體 3a: Inductor body
20:絕緣體 20: Insulator
20a:第一側 20a: First side
20b:第二側 20b: Second side
221,222,223:線圈 221, 222, 223: Coils
24a:第一導電柱 24a: the first conductive column
24b:第二導電柱 24b: second conductive column
25a:第一電性接觸墊 25a: first electrical contact pad
25b:第二電性接觸墊 25b: second electrical contact pad
26:表面處理層 26: Surface treatment layer
27b:絕緣保護層 27b: Insulating protective layer
32a,32b:電感線路 32a, 32b: Inductive lines
38:導接線路 38: Conductor line
33a,33b:導電體 33a, 33b: Conductors
Claims (8)
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