TWM616053U - Integrated circuit carrier board structure for packaging and testing - Google Patents

Abstract

This creation is about an integrated circuit carrier board structure for packaging and testing, including a substrate layer made of glass, quartz, sapphire or ceramic; a dielectric layer bonded to the surface of the substrate layer; at least An insulating layer is combined with the surface of the dielectric layer. The insulating layer, the dielectric layer and the substrate layer are respectively drilled with a plurality of penetrating electrical conduction holes, and a plurality of circuits are formed in the penetrating electrical conduction holes. In this way, the integrated circuit carrier board can be processed in a large area, and more circuits can be made, and it is not easy to deform under high temperature, has excellent anti-electromagnetic wave interference and can improve the heat dissipation efficiency.

Description

Integrated circuit carrier board structure for packaging and testing

This creation is about an integrated circuit carrier board for wafer packaging and testing that can be processed in a large area and produce more circuits.

At present, the common wafers must undergo packaging testing after the packaging is completed to ensure the wafer's pass rate. When testing the wafer, the probe of the wafer probe card of the test equipment is mainly used to penetrate the contact pad on the die to form electrical contact, and then the test signal measured by the probe is sent to the automatic The test equipment performs analysis and judgment, so that the electrical characteristics test results of each die on the wafer can be obtained.

Wafer testing equipment, such as the new patent case No. M323619 "IC test carrier board solderless assembly structure" announced on December 11, 1996, which discloses: the use of long metal bumps to embed the IC test motherboard On (Probe Card PCB), bumps are used to replace solder balls and reflow connection assembly, which includes: an IC probe card; a metal bump; an IC test carrier board; a screw; a screw Seat; and a spring. The screw is threaded through the screw seat, and the IC probe card is placed on the IC test carrier by using the screw to match the screw hole. The screw is threaded through the spring, and the flatness of the IC test carrier is controlled by adjusting the height of the spring and the screw.

There is also a patent case of Invention No. I454710 "Probe card and its manufacturing method" announced on October 1, 103 of the Republic of China, which discloses: it is used to contact a plurality of probes; the probe card contains a substrate , At least two IC carrier boards and a plurality of probe pads; wherein the IC carrier boards are arranged on the substrate and are separated by a predetermined distance; each IC carrier board has a plurality of conductive contacts; the probes The pads are respectively plated on the IC carrier boards, and are respectively connected to each of the lead contact points, so as to shield each of the lead contact points, and enclose a needle cloth area on each IC carrier plate; the probe pads Used to contact each probe respectively.

However, in the test equipment of the previous patents mentioned above, the integrated circuit substrate (Substrate) used is also referred to as the IC substrate. The main function of the IC substrate is to carry the IC as a carrier and use the IC substrate. The internal circuit connects the signal between the chip and the printed circuit board (PCB), mainly for protection circuits, fixed circuits and heat conduction. The key parts in the packaging process account for 30-50% of the cost of the packaging process. With the evolution of wafer process technology, The increased performance requirements for wafer wiring density, transmission rate, and signal interference have gradually increased the demand for IC substrates. The substrate of the IC carrier is similar to the copper foil substrate of the PCB. The main materials can be divided into three types: hard substrates (including ABF), flexible film substrates and co-fired ceramic substrates. However, whether it is a rigid substrate, a flexible film substrate or a co-fired ceramic substrate, it has disadvantages such as difficult processing when large in size, easy to warp and deform, poor electromagnetic interference resistance, and difficult heat dissipation at high temperatures, so it is not easy to use. Not ideal.

This creation is to solve the above-mentioned shortcomings of the integrated circuit carrier used in the wafer packaging test equipment. Therefore, this creation provides an integrated circuit carrier board structure for packaging and testing, which is provided with a substrate layer, which is made of glass, quartz, sapphire or ceramic; and a dielectric layer, which is bonded to the surface of the substrate layer; At least one insulating layer is combined with the surface of the dielectric layer. The insulating layer, the dielectric layer and the substrate layer are respectively drilled with a plurality of penetrating electrical vias, and a plurality of circuits are formed in the penetrating electrical vias. .

The above-mentioned ceramics are made of alumina or aluminum nitride.

The thickness of the substrate layer is 0.4 to 1.2 mm.

The thickness of the above-mentioned dielectric layer is 0.01 to 0.03 μm.

The above-mentioned dielectric layer is made of titanium or copper.

The above-mentioned insulating layer is made of ceramic material.

The above-mentioned ceramic material is made of alumina or aluminum nitride.

The number of the above-mentioned insulating layers is between 1 and 6 layers.

The thickness of the above-mentioned insulating layer is 0.1 to 0.3 mm.

The above system uses laser drilling to form the penetrating electrical via holes.

The diameter of the above-mentioned penetrating electrical via hole is 0.025 to 0.15 mm.

In the above system, these lines are formed by laser etching or yellow light etching.

The above technical features have the following advantages:

1. The substrate layer is made of glass, quartz, sapphire or ceramic, so it can be processed in a large area, and more circuits can be made, so as to reduce the number of insulating layers to achieve better test efficiency.

2. Because glass, quartz, sapphire or ceramics have a small thermal expansion coefficient, they are not easily deformed and warped at high temperatures, and are easy to process.

3. The substrate layer made of glass, quartz, sapphire or ceramic has excellent anti-electromagnetic interference characteristics.

4. The matching insulating layer is ceramic or aluminum oxide, aluminum nitride, so it can effectively improve the efficiency of heat dissipation.

Please refer to the first, second and third figures. The integrated circuit carrier 1 of this creative embodiment includes: a base material layer 2, a dielectric layer 3 and at least one insulating layer 4, of which:

The substrate layer 2 is made of glass, quartz, sapphire or ceramics, and the ceramics is made of alumina or aluminum nitride. The thickness of the substrate layer 2 is 0.4 to 1.2 mm.

The dielectric layer 3 is bonded to the surface of the substrate layer 2. The dielectric layer 3 is made of titanium or copper. The thickness of the dielectric layer 3 is 0.01 to 0.03 μm.

At least one insulating layer 4 is bonded to the surface of the dielectric layer 3 (that is, one or both sides of the substrate layer 2). The insulating layer 4 is aided by the dielectric layer 3, so that the insulating layer 4 can interact with the The base material layer 2 achieves the function of combining dissimilar materials. The insulating layer 4 is made of ceramic material, and the ceramic material is made of aluminum oxide or aluminum nitride. The number of the insulating layer 4 includes between 1 and 6 layers. The thickness of the insulating layer 4 is 0.1 to 0.3 mm. In addition, the insulating layer 4 can be laser-drilled according to different wafer test circuits. A plurality of penetrating electrical vias 5 are drilled on the insulating layer 4, the dielectric layer 3, and the substrate layer 2 respectively. The diameter of the penetrating electrical vias 5 is 0.025 to 0.15 mm. Finally, laser etching or yellow light etching is used to connect and form a plurality of lines 6 in the through electrical via 5. The circuits 6 can be connected to both sides of the base material layer 2 and the insulating layer 4.

The integrated circuit carrier board 1 of this invention can be used in a variety of different packaging modes when testing wafer packaging. As shown in the fourth figure, it is a BGA mode of wire bonding, in which a die A is bonded to one side of the integrated circuit carrier 1 and then is completely covered by a sealing compound B. Then a bonding wire C is connected between the integrated circuit carrier 1 and the bare die A, and the other side of the integrated circuit carrier 1 is combined with a solder ball D as a pin. In this way, it can be used as a die. The circle is used for testing.

As shown in the fifth figure, it is a flip chip package (Flip Chip) BGA mode. The connection point of the die A is provided with bumps E (bump), and then the die A is turned over to make the bump E It is directly connected to the integrated circuit carrier board 1 and then completely covered by the sealing compound B, and the other side of the integrated circuit carrier board 1 is combined with solder balls D as pins. In this way, it can also be used as a wafer test.

As shown in FIG. 6, it is a QFN mode of wire bonding, in which a die A is bonded to one side of the integrated circuit carrier 1, and the die A is then completely covered by a sealant B. Then, a bonding wire C is connected between the integrated circuit carrier 1 and the bare die A, and the integrated circuit carrier 1 is combined with conductive blocks F as pins. In this way, it can be used as a wafer Test use.

As shown in the seventh figure, it is a flip chip package (Flip Chip) QFN mode. The connection point of the die A is provided with bumps E, and then the die A is turned over to make the bumps E and the product. The integrated circuit carrier board 1 is directly connected, and then is completely covered by the sealing compound B, and the integrated circuit carrier board 1 is penetrated and combined with conductive blocks F as pins. In this way, it can also be used as a wafer test.

Therefore, the base material layer 2 of this creation is made of glass material, so more circuits 6 can be made in a smaller area, so as to reduce the number of insulating layers 4 to achieve better testing. efficient. Since glass has a small thermal expansion coefficient, it is not easily deformed and warped at high temperatures, and is easy to process. In addition, the substrate layer 2 made of glass has good resistance to electromagnetic waves and is not easily disturbed. In addition, the insulating layer 4 is made of ceramic material or aluminum oxide or aluminum nitride, so the heat dissipation efficiency can be effectively improved.

In addition, four materials including printed circuit board (PCB), glass, aluminum nitride and aluminum oxide have been tested, and their dielectric constants are between 4.2 and 4.4 at the same frequency, and glass is 6.17. Nitrided Aluminum is 8.7 and alumina is 9.5. Therefore, the base material layer 2 and the insulating layer 4 of this invention are made of glass or ceramic materials. Therefore, the integrated circuit carrier board 1 of this invention is not easy to be burned or short-circuited after long-term use.

Based on the description of the above-mentioned embodiments, when we can fully understand the operation, use and effects of this creation, but the above-mentioned embodiments are only the preferred embodiments of this creation, and the implementation of this creation cannot be limited by this. The scope, that is, the simple equivalent changes and modifications made according to the scope of the patent application for this creation and the content of the creation description, are all within the scope of this creation.

1: Integrated circuit carrier board 2: Substrate layer 3: Dielectric layer 4: Insulation layer 5: Through electrical vias 6: Line A: bare die B: Sealing glue C: Wire up D: Tin ball E: bump F: conductive block

[The first picture] is a three-dimensional external view of the front of this creative embodiment.

[Second Picture] is a three-dimensional external view of the back of this creative embodiment.

[The third figure] is a combined cross-sectional view of this creative embodiment.

[Fourth Figure] is a schematic diagram of the BGA mode used in the bonding and packaging of this creative embodiment.

[Fifth Figure] is a schematic diagram of this creative embodiment used in the flip chip package BGA mode.

[Figure 6] is a schematic diagram of the QFN mode used in the bonding and packaging of this creative embodiment.

[The seventh figure] is a schematic diagram of the QFN mode used in the flip chip package in this creative embodiment.

1: Integrated circuit carrier board

2: Substrate layer

3: Dielectric layer

4: Insulation layer

5: Through electrical vias

6: Line

Claims (12)

An integrated circuit carrier board structure for packaging and testing, including: A substrate layer made of glass, quartz, sapphire or ceramics; A dielectric layer is bonded to the surface of the substrate layer; At least one insulating layer is combined with the surface of the dielectric layer. The insulating layer, the dielectric layer and the substrate layer are respectively drilled with a plurality of penetrating electrical vias, and a plurality of circuits are formed in the penetrating electrical vias. . For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the ceramic is made of alumina or aluminum nitride. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the thickness of the substrate layer is 0.4 to 1.2 mm. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the thickness of the dielectric layer is 0.01 to 0.03 μm. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the dielectric layer is made of titanium or copper. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the insulating layer is made of ceramic material. For example, the integrated circuit carrier board structure for packaging and testing of claim 6, wherein the ceramic material is made of alumina or aluminum nitride. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the number of the insulating layer is between 1 and 6 layers. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the thickness of the insulating layer is 0.1 to 0.3 mm. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein a laser drilling method is used to form the penetrating electrical vias. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the diameter of the penetrating electrical via holes is 0.025 to 0.15 mm. For example, the integrated circuit carrier board structure for packaging and testing of claim 1, wherein the circuits are formed by laser etching or yellow light etching.

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