TWM613506U - Serial array type alloy sheet structure of alloy resistor - Google Patents
Serial array type alloy sheet structure of alloy resistor Download PDFInfo
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- TWM613506U TWM613506U TW110200162U TW110200162U TWM613506U TW M613506 U TWM613506 U TW M613506U TW 110200162 U TW110200162 U TW 110200162U TW 110200162 U TW110200162 U TW 110200162U TW M613506 U TWM613506 U TW M613506U
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Abstract
一種合金電阻的串行陣列型式合金板材結構,係在一合金板材上所規劃的複數個矩陣區塊的每一個矩陣區塊中包括一沖除區域和複數個彼此平行且相隔一間隔距離的合金電阻佈設迴路或至少一合金電阻佈設迴路,每一個該合金電阻佈設迴路中,佈設一合金電阻區串行陣列,而該合金電阻區串行陣列則包括複數個彼此間隔相鄰的合金電阻區。A serial array type alloy sheet structure of alloy resistance. Each matrix block of a plurality of matrix blocks planned on an alloy sheet includes an erasing area and a plurality of alloys that are parallel to each other and spaced apart from each other. The resistance arrangement circuit or at least one alloy resistance arrangement circuit, each of the alloy resistance arrangement circuits, is arranged with a series array of alloy resistance areas, and the series array of alloy resistance areas includes a plurality of alloy resistance areas spaced and adjacent to each other.
Description
本創作係關於一種合金電阻結構,特別是一種合金電阻的串行陣列型式合金板材結構,其係在一合金板材上所規劃的矩陣區塊中包括至少一合金電阻佈設迴路,且在該合金電阻佈設迴路中佈設包括複數個彼此間隔相鄰的合金電阻區的合金電阻區串行陣列。This creation is about an alloy resistance structure, especially a series array type alloy sheet structure of alloy resistance, which includes at least one alloy resistance wiring circuit in a matrix block planned on an alloy sheet, and in the alloy resistance A series array of alloy resistance regions including a plurality of alloy resistance regions spaced adjacent to each other is arranged in the layout loop.
查傳統表面黏著型晶片電阻器一般是以厚膜印刷製程予以製造,其主要係在選定之陶瓷基板上經過一序列之印刷、雷射修整、銅端極、電鍍製程在該陶瓷基板上形成所需之電阻器。而在另一種電阻器之型態中,則為廣泛使用之合金電阻器。Check that traditional surface mount chip resistors are generally manufactured by a thick film printing process, which is mainly formed on a selected ceramic substrate through a sequence of printing, laser trimming, copper terminals, and electroplating processes on the ceramic substrate. Resistors needed. In another type of resistor, alloy resistors are widely used.
合金電阻器雖然具有其特定的優點,但在合金電阻器之加工過程中,仍存在一些技術問題。例如在材料利用率方面,現行技術由於規劃佈局不良,使得昂貴的合金板材耗損率高,無法達到最佳化的面積利用率,從而無法達到節省材料成本的目的。Although alloy resistors have their specific advantages, there are still some technical problems in the processing of alloy resistors. For example, in terms of material utilization, the current technology due to poor planning and layout makes expensive alloy plates high in wear rate, unable to achieve optimal area utilization, and thus unable to achieve the purpose of saving material costs.
再者,不良的規劃佈局往往無法提高合金電阻的元件佈設密集度。在完成製程後的元件測試過程中,也往往受限,因而無法提昇產製效率和封裝效率。Furthermore, poor planning and layout often fail to increase the density of component placement of alloy resistors. In the process of component testing after the completion of the manufacturing process, it is often limited, so that the production efficiency and packaging efficiency cannot be improved.
緣此,本創作之主要目的即是提供一種合金電阻的串行陣列型式合金板材結構,以期克服上述現行技術的各項缺失。For this reason, the main purpose of this creation is to provide a serial array type alloy sheet structure of alloy resistors in order to overcome the above-mentioned shortcomings of the current technology.
本創作所採用之技術手段係在一合金板材上所規劃的複數個矩陣區塊的每一個矩陣區塊中包括一沖除區域和複數個彼此平行且相隔一間隔距離的合金電阻佈設迴路或至少一合金電阻佈設迴路,每一個該合金電阻佈設迴路中,佈設一合金電阻區串行陣列,而該合金電阻區串行陣列則包括複數個彼此間隔相鄰的合金電阻區。每一個該合金電阻區再由一封裝體封裝。The technical means used in this creation is that each matrix block of a plurality of matrix blocks planned on an alloy plate includes a flushing area and a plurality of alloy resistance wiring circuits that are parallel to each other and separated by a distance or at least An alloy resistance arrangement loop, each of the alloy resistance arrangement loops, is arranged with a series array of alloy resistance zones, and the series array of alloy resistance zones includes a plurality of alloy resistance zones spaced and adjacent to each other. Each of the alloy resistance areas is then encapsulated by a package body.
較佳地,每一個該合金電阻佈設迴路的一端係是在該沖除區域的一第一沖除側緣連接於該合金板材,而另一端則以向著該沖除區域的一第二沖除側緣的方向延伸出呈一自由端型式,而與該第二沖除側緣相隔一距離。Preferably, one end of each of the alloy resistance wiring circuits is connected to the alloy sheet at a first flushed side edge of the flushed area, and the other end is connected to a second flushed area toward the flushed area. The direction of the side edge extends to form a free end pattern, and is separated from the second flushed side edge by a distance.
在效果方面,由於本創作是在合金電阻的製程中,在合金板材上形成複數個彼此平行且相隔一間隔距離的合金電阻佈設迴路或至少一個合金電阻佈設迴路,再於每一個合金電阻佈設迴路中採串行陣列型式佈設複數個彼此間隔相鄰的該合金電阻區,故可達到合金板材的較高面積利用率、節省材料成本、提高元件佈設密集度、利於單體測試、提昇產製效率和封裝效率。In terms of effect, since this creation is in the process of alloy resistance, a plurality of alloy resistance wiring circuits or at least one alloy resistance wiring circuit that are parallel to each other and separated by a distance are formed on the alloy plate, and then a circuit is laid on each alloy resistance. Zhongcai serial array layout of multiple resistance zones of the alloy adjacent to each other can achieve higher area utilization of alloy plates, save material costs, increase the density of component layout, facilitate single-unit testing, and improve production efficiency And packaging efficiency.
本創作所採用的具體技術,將藉由以下之實施例及附呈圖式作進一步之說明。The specific technology used in this creation will be further explained by the following embodiments and accompanying drawings.
同時參閱圖1、2所示,首先以例如鎳、鉻合金或其它適合作為合金電阻的材料製備延伸型式的合金板材1(圖1所示),然後在該合金板材1的有效面積上,規劃出複數個彼此相隔一間隔距離的矩陣區塊2(例如圖2中所示的2x6個矩陣區塊2)。Refer to Figures 1 and 2 at the same time. First, an extended type alloy plate 1 (shown in Figure 1) is prepared with nickel, chromium alloy or other materials suitable for alloy resistance, and then the effective area of the
參閱圖3所示,在合金板材1上所規劃出的複數個矩陣區塊的每一個矩陣區塊2中,依據所須合金電阻成品的尺寸及阻值規劃出沖除區域21和複數個彼此平行且相隔一間隔距離的合金電阻佈設迴路31、32、33(如圖2所示)。Referring to Fig. 3, in each
參閱圖4所示,在後續製程中,以沖壓製程沖除該沖除區域21後,即在該每一個矩陣區塊2中形成一第一沖除側緣22、一第二沖除側緣23,同時留下至少一個合金電阻佈設迴路31或複數個彼此平行且相隔一間隔距離的合金電阻佈設迴路31、32、33。Referring to FIG. 4, in the subsequent process, after the punched
同時參閱圖5~7所示,其中圖5顯示圖4中其中一個矩陣區塊2中所形成的數個合金電阻佈設迴路的擴大視圖,圖6顯示圖5中A-A斷面的剖視圖,而圖7顯示圖5中B-B斷面的剖視圖。如圖所示,每一個合金電阻佈設迴路31、32、33的一端(左側端)都是在第一沖除側緣22連接於未沖除的合金板材1,而另一端(右側端)則以向著第二沖除側緣23的方向延伸出呈一自由端型式,而與合金板材1的第二沖除側緣23相隔一距離。如此的佈設型式,有助於板材應力的釋放,防止可能的成型變形的問題。Also refer to Figures 5-7. Figure 5 shows an enlarged view of several alloy resistor wiring circuits formed in one of the
在圖式所顯示的每一個合金電阻佈設迴路31、32、33都是由同一個方向延伸。習於此項技術者也可以瞭解到本創作的其它實施例中,基於最大面積利用率、板材應力、沖壓簡便性...等因素,亦可以不限此一型式。例如一部分的合金電阻佈設迴路和雙數位的合金電阻佈設迴路是朝不同方向延伸,或是間隔的合金電阻佈設迴路(例如區分為雙數位和單數位的合金電阻佈設迴路)是朝不同方向延伸。更者,選擇性地,各個合金電阻佈設迴路的兩端亦可分別連結於合金板材1的第一沖除側緣22和第二沖除側緣23,而不是在一端呈斷開的型式。Each of the alloy
參閱圖8所示,其顯示每一個合金電阻佈設迴路31、32、33中,規劃佈設包括有複數個彼此間隔相鄰的合金電阻區的合金電阻區串行陣列。例如,以合金電阻佈設迴路31為例,在該合金電阻佈設迴路31中規劃佈設一合金電阻區串行陣列4,而該合金電阻區串行陣列4中則進一步包括複數個彼此間隔相鄰的合金電阻區41、42、43、44、45。每一個合金電阻區則定義有一注模區段和分別位在該注模區段兩相反端個導電區段。Referring to FIG. 8, it shows that in each of the alloy
參閱圖9所示,在後續製程中,每一個合金電阻區41、42、43、44、45再由封裝體51、52、53、54、55予以封裝。該封裝體51、52、53、54、55經硬化之後,可以達到保護合金電阻並達到絕緣之目的。該封裝體4所選用之材料可為環氧樹脂或其它具有良好絕緣及包覆效果之材料。Referring to FIG. 9, in the subsequent manufacturing process, each of the
最後,即可將各個合金電阻區分離,而完成多數個合金電阻單體。合金電阻單體之兩端再以導電端極材料形成導電端極,以利日後實際應用時之銲鍚作業。Finally, each alloy resistance zone can be separated, and a plurality of alloy resistance monomers can be completed. The two ends of the alloy resistor monomer are then made of conductive terminal materials to form conductive terminals to facilitate the welding operation in practical applications in the future.
以上所舉實施例僅係用以說明本創作,並非用以限制本創作之範圍,凡其他未脫離本創作所揭示之精神下而完成的等效修飾或置換,均應包含於後述申請專利範圍內。The above-mentioned examples are only used to illustrate the creation, not to limit the scope of the creation. All other equivalent modifications or replacements completed without departing from the spirit of the creation should be included in the scope of the patent application described below. Inside.
1:合金板材
2:矩陣區塊
21:沖除區域
22:第一沖除側緣
23:第二沖除側緣
31、32、33:合金電阻佈設迴路
4:合金電阻區串行陣列
41、42、43、44、45:合金電阻區
51、52、53、54、55:封裝體1: Alloy sheet
2: Matrix block
21: flush out the area
22: First flush off the side edge
23: Second flushing off the
圖1顯示本創作先製備一合金板材的平面示意圖。 圖2顯示本創作在合金板材規劃出複數個矩陣區塊的平面示意圖。 圖3顯示本創作在各個矩陣區塊規劃沖除區域和複數個合金電阻佈設迴路的平面示意圖。 圖4顯示本創作合金板材的各個矩陣區塊經沖壓形成多數個合金電阻佈設迴路的平面示意圖。 圖5顯示圖4中其中一個矩陣區塊中所形成的數個合金電阻佈設迴路的擴大視圖。 圖6顯示圖5中A-A斷面的剖視圖。 圖7顯示圖5中B-B斷面的剖視圖。 圖8顯示本創作在每一個合金電阻佈設迴路中規劃佈設合金電阻區串行陣列的平面示意圖。 圖9顯示本創作在每一個合金電阻區以封裝體封裝的平面示意圖。 Figure 1 shows a schematic plan view of an alloy plate prepared in this creation. Figure 2 shows a schematic plan view of a plurality of matrix blocks planned for the alloy sheet in this creation. Figure 3 shows the plan view of this creation in each matrix block to plan the flushing area and the circuit of multiple alloy resistors. Fig. 4 shows a schematic plan view of a plurality of alloy resistor wiring circuits formed by stamping each matrix block of the alloy sheet of the invention. FIG. 5 shows an enlarged view of several alloy resistor wiring circuits formed in one of the matrix blocks in FIG. 4. Fig. 6 shows a cross-sectional view of the A-A section in Fig. 5. Fig. 7 shows a cross-sectional view of the B-B section in Fig. 5. Figure 8 shows a plan view of a serial array of alloy resistance areas planned and arranged in each of the alloy resistance circuits in this creation. Figure 9 shows a schematic plan view of each alloy resistor area of the invention encapsulated by a package body.
1:合金板材 1: Alloy sheet
21:沖除區域 21: flush out the area
22:第一沖除側緣 22: First flush off the side edge
23:第二沖除側緣 23: Second flushing off the side edge
31、32、33:合金電阻佈設迴路 31, 32, 33: alloy resistance wiring circuit
4:合金電阻區串行陣列 4: Serial array of alloy resistance zone
41、42、43、44、45:合金電阻區 41, 42, 43, 44, 45: alloy resistance zone
Claims (6)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110200162U TWM613506U (en) | 2021-01-07 | 2021-01-07 | Serial array type alloy sheet structure of alloy resistor |
CN202220034545.4U CN216671319U (en) | 2021-01-07 | 2022-01-07 | Serial array type alloy plate structure of alloy resistor |
JP2022000023U JP3236660U (en) | 2021-01-07 | 2022-01-07 | Alloy resistant serial array type alloy sheet structure |
Applications Claiming Priority (1)
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TW110200162U TWM613506U (en) | 2021-01-07 | 2021-01-07 | Serial array type alloy sheet structure of alloy resistor |
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TWM613506U true TWM613506U (en) | 2021-06-21 |
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TW110200162U TWM613506U (en) | 2021-01-07 | 2021-01-07 | Serial array type alloy sheet structure of alloy resistor |
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JP (1) | JP3236660U (en) |
CN (1) | CN216671319U (en) |
TW (1) | TWM613506U (en) |
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TWI718971B (en) * | 2020-07-07 | 2021-02-11 | 旺詮股份有限公司 | Manufacturing method for mass production of miniature resistance elements |
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2021
- 2021-01-07 TW TW110200162U patent/TWM613506U/en unknown
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2022
- 2022-01-07 JP JP2022000023U patent/JP3236660U/en active Active
- 2022-01-07 CN CN202220034545.4U patent/CN216671319U/en active Active
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JP3236660U (en) | 2022-03-08 |
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