TWM610519U - Chip package and both electronic device and circuit board assembly including the chip packages - Google Patents

Abstract

A chip package includes a carrier and a first chip. The carrier includes an insulating part, a circuit structure, a heat-dissipating pad, a thermal conductive part and a first chip. The insulating part has a first surface, a second surface opposite to the first surface, and a sidewall surface located between the first surface and the second surface. The circuit structure is located in the insulating part, and a part of the circuit structure is exposed at the first surface. The heat-dissipating pad is attached to the sidewall surface. The thermal conductive part is located in the insulating part and thermally coupled to the heat-dissipating pad. The first chip is mounted on the first surface and electrically connected to the circuit structure, in which the first chip is thermally coupled to the thermal conductive part.

Description

Chip package and electronic device and circuit board assembly including the chip package

This creation relates to a chip package, and more particularly to a chip package with heat dissipation pads, and an electronic device and circuit board assembly including the chip package.

With the advancement of semiconductor manufacturing processes, today's chips have powerful functions, and such powerful chips usually generate a lot of heat energy during operation. However, most of the molding compounds used in chip packages have low thermal conductivity. Therefore, the heat generated by the chips is not easily dissipated from the molding materials and is easy to accumulate, resulting in the temperature of the chips. Rise and reduce performance, and even overheat (overheat) may cause chip damage.

At least one embodiment of the present invention provides a chip package that includes heat dissipation pads to help heat dissipation.

Another embodiment of the present invention provides a circuit board assembly, which includes the above-mentioned chip package.

Another embodiment of the present invention provides an electronic device, which includes the above-mentioned chip package.

The chip package provided by at least one embodiment of the present invention includes a carrier board and a first chip. The carrier board includes an insulating part, a circuit structure, a heat dissipation pad, a heat conduction part and a first chip. The insulating portion has a first surface, a second surface opposite to the first surface, and a sidewall surface located between the first surface and the second surface. The circuit structure is located in the insulating part, and a part of the circuit structure is exposed on the first surface. The heat dissipation pad is fixed on the side wall surface. The heat-conducting part is located in the insulating part and is thermally coupled to the heat-dissipating pad. The first chip is mounted on the first surface and is electrically connected to the circuit structure, wherein the first chip is thermally coupled to the heat conducting part.

In at least one embodiment of the present invention, both the heat-conducting portion and the heat-dissipating pad are separated from the circuit structure and electrically insulated from each other, and the first chip is electrically insulated from the heat-conducting part and the heat-dissipating pad.

In at least one embodiment of the present invention, the above-mentioned heat-conducting part includes a heat-conducting pad and a connecting member. The thermal pad is located on the first surface and is thermally coupled to the first chip, wherein the first chip is disposed on the thermal pad. The connector is located in the insulating part, and thermally couples the heat-conducting pad and the heat-dissipating pad.

In at least one embodiment of the present invention, the aforementioned thermal pad is connected to the thermal pad, and the thermal pad and the thermal pad are integrally formed.

In at least one embodiment of the present invention, the above-mentioned first chip has a connection pad, and the connection pad is thermally coupled to the thermal pad and is electrically insulated from the circuit structure.

In at least one embodiment of the present invention, the above-mentioned connecting member includes a metal layer and at least one metal member. The metal layer directly contacts the heat dissipation pad. The metal piece is located between the metal layer and the heat-conducting pad, and connects the metal layer and the heat-conducting pad.

In at least one embodiment of the present invention, the above-mentioned connecting member includes a plurality of metal members, and these metal members are a plurality of metal pillars.

In at least one embodiment of the present invention, the above-mentioned insulating portion includes a plurality of insulating layers stacked on each other, and two of the insulating layers have a first surface and a second surface, respectively. The circuit structure includes at least one inner circuit layer and two outer circuit layers. The outer circuit layers are located on the first surface and the second surface, respectively. The outer circuit layer on the first surface is electrically connected to the first chip, and the inner circuit layer and the metal layer are located between the two insulating layers.

In at least one embodiment of the present invention, the aforementioned chip package further includes a second chip disposed on the second surface and electrically connected to the circuit structure. The second chip is thermally coupled to the heat-conducting part, and is electrically insulated from the heat-conducting part and the heat-dissipating pad.

In at least one embodiment of the present invention, the above-mentioned heat conducting part includes a plurality of heat conducting pads and a plurality of connecting members. The thermally conductive pads are respectively located on the first surface and the second surface, and are thermally coupled to the first chip and the second chip, respectively, wherein the first chip and the second chip are respectively disposed on the thermally conductive pads. These connectors connect the thermal pads and the thermal pads.

In at least one embodiment of the present invention, the backside of the second chip is thermally coupled to the thermal pad on the second surface.

In at least one embodiment of the present invention, each connecting member includes a metal layer and at least one metal member. The metal layer directly contacts the heat dissipation pad, and the metal piece is located between the adjacent metal layer and the thermal pad, and connects the adjacent metal layer and the thermal pad.

In at least one embodiment of the present invention, the above-mentioned insulating portion includes a plurality of insulating layers stacked on each other, and two of the insulating layers have a first surface and a second surface, respectively. The circuit structure includes at least one inner circuit layer and two outer circuit layers. The outer circuit layers are located on the first surface and the second surface, respectively. The outer circuit layer on the first surface is electrically connected to the first chip, and the inner circuit layer and the metal layers are located between two insulating layers.

In at least one embodiment of the present invention, the aforementioned chip package further includes a circuit assembly, wherein the second chip is located between the carrier board and the circuit assembly, and the circuit assembly is electrically connected to the second chip and the carrier board.

The circuit board assembly provided by at least one embodiment of the present invention includes a circuit substrate and the aforementioned chip package. The circuit substrate includes a main body, a heat-conducting element and a circuit layer, wherein the heat-conducting element and the circuit layer are both located on the main body. The chip package is mounted on the main body of the circuit substrate and is electrically connected to the circuit layer, wherein the heat dissipation pad is thermally coupled to the heat conduction element.

In at least one embodiment of the present invention, the above-mentioned heat-conducting member includes a fixing part and a heat-conducting sheet. The fixing part is fixed on the main body, and the heat conducting sheet is connected to the fixing part and extends from the fixing part, wherein the heat conducting sheet is thermally coupled to the heat dissipation pad.

In at least one embodiment of the present invention, the above-mentioned first chip is located between the circuit substrate and the carrier board.

The electronic device provided by at least one embodiment of the present invention includes a casing, a circuit pattern, the aforementioned chip package, and a heat sink. The shell has a surface, and the circuit pattern is located on this surface. The chip package is mounted on the surface of the casing and is electrically connected to the circuit pattern. The heat dissipating part is thermally coupled to the heat dissipating pad.

In at least one embodiment of the present invention, the above-mentioned first chip is located between the surface of the housing and the carrier.

In at least one embodiment of the present invention, the above-mentioned housing includes a base and a wall. The base has the above-mentioned surface, and the wall is connected to the base and is located opposite to the heat dissipation pad, wherein the heat dissipation portion is located between the wall and the heat dissipation pad.

Based on the above, by using the heat conduction part and the heat dissipation pad, the heat generated by the chip (such as the first chip) in the chip package can be quickly dissipated from the heat dissipation pad to reduce or avoid the accumulation of heat, thereby preventing the chip from being degraded due to overheating. Effectiveness or damage.

In the following text, in order to clearly present the technical features of the case, the dimensions (such as length, width, thickness, and depth) of the elements (such as layers, films, substrates, and regions) in the drawings will be enlarged in unequal proportions. . Therefore, the description and explanation of the following embodiments are not limited to the size and shape presented by the elements in the drawings, but should cover the size, shape, and deviation of the two caused by actual manufacturing processes and/or tolerances. For example, the flat surface shown in the drawing may have rough and/or non-linear characteristics, and the acute angle shown in the drawing may be round. Therefore, the elements shown in the drawings of this case are mainly used for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of patent applications in this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly recorded value and range of values, but also cover those who have ordinary knowledge in the technical field can understand The allowable deviation range, where the deviation range can be determined by the error generated during the measurement, and the error is, for example, caused by the limitation of the measurement system or the process conditions. In addition, "about" may mean within one or more standard deviations of the aforementioned value, for example within ±30%, ±20%, ±10%, or ±5%. The terms "about", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties, or other properties. The standard deviation applies to all the above optical properties, etching properties, mechanical properties, and other properties.

1A to 1G are schematic diagrams of the manufacturing process of the circuit board assembly according to at least one embodiment of the present invention, wherein FIG. 1G is a schematic cross-sectional view of the circuit board assembly 200 that is substantially completed. Please refer to FIG. 1G first, the circuit board assembly 200 includes a chip package 100 and a circuit substrate 210, wherein the chip package 100 is mounted on the circuit substrate 210. The circuit substrate 210 includes a main body 211, a circuit layer 212 and a heat conducting member 213, wherein the heat conducting member 213 and the circuit layer 212 are both located on the main body 211. Taking FIG. 1G as an example, the heat conducting element 213 and the circuit layer 212 are both located on the same plane of the main body 211.

The chip package 100 is mounted on the main body 211 of the circuit substrate 210 and is electrically connected to the circuit layer 212. The chip package 100 can be mounted on the main body 211 through a plurality of solder balls B1 and is electrically connected to the circuit layer 212 , As shown in Figure 1G. However, in other embodiments, the chip package 100 can also be mounted on the main body 211 in other ways. For example, the chip package 100 can be mounted on the main body 211 by ultrasonic welding. Alternatively, the chip package 100 can also be mounted on the main body 211 and the electrical connection circuit layer 212 by wire-bonding. Therefore, FIG. 1G does not limit the manner in which the chip package 100 is mounted on the circuit substrate 210.

The circuit substrate 210 may be a single-sided wiring board, a double-sided wiring board, or a multilayer wiring board. Therefore, the circuit substrate 210 may include one or more circuit layers (including the circuit layer 212), and FIG. 1G does not limit the number of circuit layers included in the circuit substrate 210. In other words, the circuit substrate 210 may include only one circuit layer 212, or include the circuit layer 212 and at least one other circuit layer.

For example, when the circuit substrate 210 is a double-sided circuit board or a multilayer circuit board, the main body 211 may include at least one insulating layer (not shown) and at least one circuit layer (not shown). When the circuit substrate 210 is a single-layer circuit board, the main body 211 may include an insulating layer (not labeled), but does not include a circuit layer. In addition, the circuit substrate 210 may be a flexible wiring board, a rigid wiring board, or a flexible-rigid wiring board.

The heat conducting member 213 includes a fixing part A13 and a heat conducting sheet S13, wherein the heat conducting sheet S13 is connected to the fixing part A13 and extends from the fixing part A13, and the heat conducting sheet S13 can extend in a direction away from the circuit substrate 210. The fixing part A13 is fixed to the main body 211. For example, the fixing portion A13 can be attached to the main body 211 by using glue. The heat conducting member 213 may be a metal shrapnel, metal foil, metal strip or heat sink, such as copper foil, aluminum foil, copper strip or steel sheet, and the fixing part A13 and the heat conducting sheet S13 can be integrally formed. In other words, there is no obvious seam or joint between the fixing portion A13 and the thermal conductive sheet S13.

The heat conducting member 213 may also be a composite material including non-metallic materials. For example, in other embodiments not shown, the thermal conductive member 213 may include a flexible substrate and a thermal conductive layer. The thermal conductive layer is, for example, a metal layer or a carbon material layer, and is formed on the flexible substrate. The substrate may be made of a polymer material, such as Polyimide (PI) or Polyethylene Terephthalate (PET). A part of the flexible substrate can be fixed on the main body 211, and the other part is not fixed on the main body 211, so that the thermal conductive sheet S13 can be bent relative to the fixing portion A13. In addition, the aforementioned carbon material layer may be made of carbon fiber or graphene.

The chip package 100 includes a first chip 110 and a carrier 150, wherein the first chip 110 is mounted on the carrier 150. The first chip 110 may be a die, which is an unpackaged chip, so the main material of the first chip 110 may be a semiconductor material, such as silicon or gallium arsenide. However, in other embodiments, the first chip 110 may also be a packaged chip, which may include a package carrier or a lead frame (none of which is shown). Therefore, the first chip 110 is not limited to be an unpackaged die or a packaged chip.

The carrier board 150 includes an insulating portion 151 and a circuit structure 152, wherein the circuit structure 152 is located in the insulating portion 151. The insulating portion 151 has a first surface 151a, a second surface 151b opposite to the first surface 151a, and a sidewall surface 151c located between the first surface 151a and the second surface 151b. Taking FIG. 1G as an example, the upper surface and the lower surface of the insulating portion 151 are the second surface 151b and the first surface 151a, respectively, and the sidewall surface 151c is ring-shaped and extends along the edges of both the first surface 151a and the second surface 151b. .

The first chip 110 is mounted on the first surface 151 a and is electrically connected to the circuit structure 152. In detail, a part of the circuit structure 152 is exposed on the first surface 151a, and the first chip 110 can be mounted on the first surface 151a by a flip chip method, and electrically connected to the circuit structure 152 from the first surface 151a. . Taking FIG. 1G as an example, the first chip 110 may use a plurality of solder balls B1 to connect a portion of the circuit structure 152 exposed on the first surface 151a. In addition, the first chip 110 may be located between the circuit substrate 210 and the carrier 150, as shown in FIG. 1G.

The carrier 150 may be a circuit board substantially, and the circuit structure 152 includes at least one inner circuit layer 152a and two outer circuit layers 152b, wherein the inner circuit layer 152a is located between the two outer circuit layers 152b. Taking FIG. 1G as an example, the circuit structure 152 includes two inner circuit layers 152a and two outer circuit layers 152b, so the carrier 150 has four circuits, and the outer circuit layers 152b are located on the first surface 151a and the second surface, respectively. 151b, and the outer circuit layer 152b on the first surface 151a is electrically connected to the first chip 110.

The insulating part 151 includes a plurality of insulating layers L51, L52, and L53 stacked on each other, wherein the main material of the insulating layers L51, L52, and L53 may include resin. The insulating layer L52 is sandwiched between the insulating layers L51 and L53, and the two insulating layers L51 and L53 respectively have a first surface 151a and a second surface 151b, so the first wafer 110 will be adjacent to the insulating layer L51.

The insulating layers L51, L52, and L53, the inner circuit layers 152a, and the outer circuit layers 152b are stacked on each other, wherein the insulating layers L51, L52, and L53 are each sandwiched between the inner circuit layers 152a and the outer circuit layers 152b Between two of them. Taking FIG. 1G as an example, the insulating layer L52 is sandwiched between two inner circuit layers 152a, and the insulating layer L51 or L53 is sandwiched between adjacent inner circuit layers 152a and outer circuit layers 152b.

The circuit structure 152 may further include a plurality of conductive pillars V52, wherein the conductive pillars V52 are located in the insulating portion 151. For example, these conductive pillars V52 are distributed in the insulating layers L51, L52, and L53, as shown in FIG. 1G. The conductive pillars V52 connect the inner circuit layers 152a and the outer circuit layers 152b, so that current can be transmitted in the inner circuit layers 152a and the outer circuit layers 152b. In addition, the conductive pillar V52 shown in FIG. 1G is a conductive blind via structure, but in other embodiments, the conductive pillar V52 may also be a conductive through hole structure or a conductive buried hole structure. (Conductive embedded hole structure).

In this embodiment, the chip package 100 may further include a molding material 191, a plurality of metal pillars 192 and a plurality of circuit pads 193. The molding material 191 covers the first chip 110 and the first surface 151a, and covers the first chip 110, wherein the molding material 191 may be located between the carrier 150 and the circuit substrate 210. The metal pillars 192 penetrate the molding material 191 and connect the circuit pads 193 and one of the outer circuit layers 152b, and the circuit pads 193 are respectively connected to the solder balls B1, so that the metal pillars 192 can pass through the circuit pads 193 and these solder balls B1 are electrically connected to the circuit layer 212 of the circuit substrate 210. In this way, the first chip 110 can be electrically connected to the circuit substrate 210 through the carrier 150, the metal pillars 192, the circuit pads 193 and the solder balls B1.

It should be noted that in other embodiments, the first chip 110 may be electrically connected to the circuit substrate 210 only through the carrier 150 and the solder balls B1, and the carrier 150 may be located between the first chip 110 and the circuit substrate 210. In other words, the molding material 191 and the first chip 110 can be disposed on the second surface 151b, and the solder balls B1 can be connected to the outer circuit layer 152b and the circuit substrate 210 below. Therefore, the metal pillars 192 and the circuit pads 193 shown in FIG. 1G can be omitted, so that the first chip 110 can be electrically connected to the circuit substrate 210 without the metal pillars 192 and the circuit pads 193.

The carrier 150 further includes a heat dissipation pad 153 and a heat conduction portion 154. The heat dissipation pad 153 is fixed on the side wall surface 151c, and the heat conduction portion 154 is located in the insulating portion 151. The heat dissipating pad 153 is thermally coupled to the heat conducting sheet S13 of the heat conducting element 213, where the term "thermal coupling" in this case refers to the direct contact between two objects, or a high thermal conductivity such as heat dissipating glue, heat dissipating paste or heat dissipating pad is arranged between the two bodies Rate the material so that heat energy can be quickly transferred between the two objects.

Taking FIG. 1G as an example, a thermal conductive material HD1 with high thermal conductivity can be arranged between the thermal conductive sheet S13 and the thermal pad 153, such as a heat-dissipating glue, a heat-dissipating paste, or a heat-dissipating pad. The heat-conducting material HD1 may be silver glue or solder paste. , Tin glue or copper paste, or glue or gasket made of carbon material, where the carbon material is, for example, carbon fiber or graphene. Alternatively, the thermally conductive material HD1 may also be a thermally conductive polymer material with electrical insulation properties. In this way, heat energy can be quickly transferred between the thermal conductive sheet S13 and the heat dissipation pad 153.

In addition, in other embodiments, the thermal conductive sheet S13 may also directly contact the heat dissipation pad 153, and may be directly connected to the heat dissipation pad 153 through ultrasonic welding. Alternatively, the heat conducting member 213 may be a metal elastic sheet, and the heat conducting sheet S13 may press the heat dissipation pad 153 by elastic force, so that the heat conduction sheet S13 abuts the heat dissipation pad 153, but the heat conduction sheet S13 is not connected to the heat dissipation pad 153. Therefore, the thermal conductive material HD1 is not limited to be disposed between the thermal conductive sheet S13 and the thermal pad 153.

The heat conducting portion 154 is thermally coupled to the heat dissipation pad 153. In this embodiment, the heat conducting portion 154 can directly contact and connect to the heat dissipation pad 153. Specifically, the thermally conductive portion 154 may include a plurality of thermally conductive pads 154p and a plurality of connecting members 154c. The thermally conductive portion 154c in FIG. 1G as an example includes two thermally conductive pads 154p and two connecting members 154c. However, in other embodiments, the thermally conductive portion 154 may only include one thermally conductive pad 154p and one connecting member 154c. Alternatively, the thermally conductive portion 154 may include more than three thermally conductive pads 154p and more than three connecting members 154c.

The thermally conductive pads 154p are located on the first surface 151a and the second surface 151b, respectively, and the thermally conductive pads 154p on the first surface 151a are thermally coupled to the first chip 110. Taking FIG. 1G as an example, a thermally conductive material HD1 may be disposed between the first chip 110 and the adjacent thermally conductive pad 154p, so that thermal energy can be quickly transferred between the first chip 110 and the adjacent thermally conductive pad 154p.

The connectors 154c connect and thermally couple the thermal pads 154p and the thermal pads 153, and the thermal pads 154p can be connected to the thermal pads 153, wherein the thermal pads 154p and the thermal pads 153 can be integrally formed. In other words, there will be no obvious seams or joints between the thermal pad 154p and the heat dissipation pad 153. In addition, the thermal conductive pads 154p and the circuit structure 152 are separated from each other, so that the thermal conductive pads 154p and the circuit structure 152 are electrically insulated from each other. In other words, the current transferred in the circuit structure 152 will not flow to the thermal pad 154p and the heat dissipation pad 153.

Each connecting member 154c may include a metal layer M41 and a plurality of metal members M42. The metal layer M41 directly contacts and is connected to the heat dissipation pad 153, so the metal layer M41 is thermally coupled to the heat dissipation pad 153. The inner circuit layers 152a and the metal layers M41 are located between the insulating layers L51 and L53, and are located on opposite sides of the insulating layer L52.

Taking FIG. 1G as an example, the upper inner circuit layer 152a and the metal layer M41 are located between the insulating layers L53 and L52, and the lower inner circuit layer 152a and the metal layer M41 are located between the insulating layers L52 and L51. . In addition, the inner circuit layer 152a and the metal layer M41 located on the same side of the insulating layer L52 may be formed from the same metal layer by photolithography. However, the metal layer M41 and the inner circuit layer 152a are separated from each other, so that the metal layer M41 and the circuit structure 152 are electrically insulated from each other.

These metal pieces M42 are located between the metal layer M41 and the thermal pad 154p, and connect the metal layer M41 and the thermal pad 154p. In the embodiment shown in FIG. 1G, these metal pieces M42 can directly contact and connect the metal layer M41 and the thermally conductive pad 154p, so that each metal piece M42 is thermally coupled to the metal layer M41 and the thermally conductive pad 154p.

Each metal member M42 may be a metal pillar, and the shape and forming method of both the metal member M42 and the conductive pillar V52 may be the same. For example, the metal part M42 and the conductive pillar V52 can be formed in the same electroplating process, and the shapes of the two can be the same as the conductive blind hole structure. In addition, the metal parts M42 and the circuit structure 152 are separated from each other, so that the metal parts M42 and the circuit structure 152 are electrically insulated from each other.

Therefore, the metal layers M41 and the metal members M42 are electrically insulated from the circuit structure 152, so that the connecting members 154c and the circuit structure 152 are electrically insulated from each other. Since each thermal conductive pad 154p and the circuit structure 152 are also electrically insulated from each other, both the thermal conductive portion 154 and the heat dissipation pad 153 are separated from the circuit structure 152 and are electrically insulated from each other. In other words, under the normal operation of the circuit board assembly 200, the current transmitted in the circuit structure 152 will not be transmitted to the heat conducting portion 154 and the heat dissipation pad 153.

The first chip 110 is thermally coupled to the heat-conducting portion 154, so the first chip 110 can be thermally coupled to the heat-dissipating pad 153 through the heat-conducting portion 154. In the embodiment shown in FIG. 1G, the first chip 110 may have a connection pad 111, wherein under the normal operation of the first chip 110, no current will pass through the connection pad 111. In other words, the first chip 110 will neither output any electrical signals from the connection pad 111 nor receive any electrical signals from the connection pad 111, so the connection pad 111 and the circuit structure 152 are electrically insulated.

The connection pad 111 is thermally coupled to the thermal pad 154p. For example, a thermally conductive material HD1 can be arranged between the connecting pad 111 and the thermally conductive pad 154p, so that the connecting pad 111 is thermally coupled to the thermally conductive pad 154p through the thermally conductive material HD1, as shown in FIG. 1G. Alternatively, the connection pad 111 can also directly contact the thermally conductive pad 154p, and even the connection pad 111 can directly connect to the thermally conductive pad 154p. For example, the connection pad 111 can be directly connected to the thermal pad 154p by ultrasonic welding.

Under the normal operation of the first chip 110, there is no current transfer in the connection pad 111. Therefore, even if the connection pad 111 directly contacts the thermal pad 154p, the first chip 110 is still electrically insulated from the thermal pad 154p, so that the first chip 110 It is electrically insulated from the heat conducting part 154. In addition, the first chip 110 and the heat dissipation pad 153 are separated from each other, so that the first chip 110 is also electrically insulated from the heat dissipation pad 153. In other words, the first chip 110 is electrically insulated from the heat dissipation pad 153 and the heat conduction portion 154. Therefore, under normal circumstances, there is no current transfer between the heat dissipation pad 153 and the heat conduction portion 154 and the first chip 110.

Since the first chip 110 can be thermally coupled to the heat dissipation pad 153 through the heat conduction portion 154, the heat generated by the first chip 110 in operation can be quickly transferred to the heat dissipation pad 153 through the heat conduction portion 154 to reduce or avoid heat energy. It is deposited on the first wafer 110 to prevent the temperature of the first wafer 110 from being too high. Secondly, the heat dissipating pad 153 is thermally coupled to the heat conducting member 213, so the heat energy of the first chip 110 can be quickly transferred from the heat dissipating pad 153 to the heat conducting member 213 of the circuit substrate 210 to help the heat dissipate, thereby preventing the first chip 110 from being caused by Overheating reduces performance or damages.

The chip package 100 may include a plurality of chips. Taking FIG. 1G as an example, the chip package 100 may further include a second chip 120, which may be the same as the first chip 110. The second chip 120 may be disposed on the second surface 151 b and thermally coupled to the heat conducting portion 154. Therefore, the carrier 150 can be located between the first chip 110 and the second chip 120. The thermally conductive pads 154p of the thermally conductive portion 154 are respectively located on the first surface 151a and the second surface 151b, and are thermally coupled to the first chip 110 and the second chip 120, respectively, wherein the first chip 110 and the second chip 120 are respectively disposed on the thermally conductive Pad 154p.

The crystal back (not labeled) of the second chip 120 may be thermally coupled to the thermal pad 154p on the second surface 151b. For example, the crystal back of the second wafer 120 may directly contact the thermal pad 154p. Therefore, the second chip 120 can be thermally coupled to the heat dissipating pad 153 and the heat conducting element 213 through the heat conducting portion 154, so that the heat generated by the second chip 120 can also be quickly transferred from the heat dissipating pad 153 to the heat conduction of the circuit substrate 210 The component 213 helps the heat to dissipate, so as to prevent the second chip 120 from being overheated and degraded or damaged.

In addition, the second chip 120 is electrically connected to the circuit structure 152, so the second chip 120 can be electrically connected to the circuit substrate 210 through the carrier 150. Since the heat conducting portion 154 and the heat dissipating pad 153 are both electrically insulated from the circuit structure 152, and the second chip 120 is thermally coupled to the heat conducting pad 154p through the backside, the second chip 120 is not electrically connected to the heat conducting pad 154p, and Electrically insulated from the heat conducting portion 154 and the heat dissipation pad 153.

In this embodiment, the chip package 100 may further include a circuit assembly 160, wherein the second chip 120 is located between the carrier 150 and the circuit assembly 160, and the circuit assembly 160 is electrically connected to the second chip 120 and the carrier 150 to The second chip 120 can be electrically connected to the carrier 150 through the circuit assembly 160. In addition, the circuit component 160 may be a circuit board substantially.

Taking FIG. 1G as an example, the circuit assembly 160 may include an insulating layer 161, a multilayer circuit layer 162, and a plurality of conductive pillars V62. The circuit layers 162 are respectively formed on opposite sides of the insulating layer 161, that is, the insulating layer 161 is sandwiched between the circuit layers 162. The conductive pillars V62 are located in the insulating layer 161 and connected to the circuit layers 162 so that the circuit layers 162 can be electrically connected to each other through the conductive pillars V62.

The second chip 120 is electrically connected to the circuit layer 162 adjacent to the carrier 150, and the second chip 120 can be electrically connected to the circuit layer 162 in a flip chip manner. In other words, the second chip 120 can be electrically connected to the circuit layer 162 through the plurality of solder balls B1. In addition, the second chip 120 may be covered and covered by the molding material 191, and the molding material 191 and the second chip 120 covered by the molding material 191 may be located between the carrier 150 and the circuit assembly 160, as shown in FIG. 1G.

The molding material 191 covering and covering the second chip 120 may also be penetrated by a plurality of metal pillars 192, and the metal pillars 192 connect the adjacent circuit layer 162 and the outer circuit layer 152b to electrically connect the circuit component 160 and the carrier.板150. For example, the metal pillars 192 can be electrically connected to the adjacent circuit layer 162 and the outer circuit layer 152b by ultrasonic welding or solder balls B1. In this way, the second chip 120 can be electrically connected to the circuit substrate 210 through the circuit component 160 and the carrier 150.

The carrier 150 may further include two insulating protection layers 159a and 159b. The insulating protection layers 159a and 159b are respectively located on the opposite first surface 151a and the second surface 151b of the insulating portion 151, wherein the insulating protection layers 159a and 159b both have a plurality of openings (not labeled) to expose the thermal pad 154p and part of the outer circuit Layer 152b, so that the outer circuit layer 152b can electrically connect the first chip 110 and the circuit assembly 160, and the thermally conductive pads 154p can thermally couple the first chip 110 and the second chip 120, respectively. In addition, the insulating protection layers 159a and 159b may be solder masks.

The circuit assembly 160 may further include two insulating protection layers 169, wherein the insulating protection layer 169 may also be a solder mask. The insulating protection layers 169 are respectively located on opposite sides of the insulating layer 161, wherein the insulating protection layers 169 all have a plurality of openings to partially expose the circuit layers 162. In this way, the lower circuit layer 162 can electrically connect the metal pillars 192 and the second chip 120, and the upper circuit layer 162 can be used for installation of other electronic components (not shown). In addition, in other embodiments, the upper insulating protection layer 169 may not have any openings to cover the insulating layer 161 comprehensively.

In particular, in other embodiments, the chip package 100 may only include one chip. For example, the chip package 100 may include only one of the first chip 110 and the second chip 120. Therefore, the thermally conductive portion 154 may only include one thermally conductive pad 154p and one connecting member 154c to thermally couple a single chip (for example, the first chip 110 or the second chip 120). In other words, not only can one of the first chip 110 and the second chip 120 in FIG. 1G be omitted, but the set of connectors 154c and the thermal pad 154p thermally coupled to the omitted chip can also be omitted. Therefore, FIG. 1G does not limit the number of chips in the chip package 100, the number of connectors 154c, and the number of thermal pads 154p.

In the embodiment shown in FIG. 1G, the carrier board 150 includes multiple inner circuit layers 152a (FIG. 1G shows two inner circuit layers 152a), but in other embodiments, the carrier board 150 may also include only one inner circuit layer 152a. Layer circuit layer 152a, or does not include any inner circuit layer 152a. Therefore, FIG. 1G does not limit the number of inner circuit layers 152a included in the carrier 150.

Secondly, the chip package 100 shown in FIG. 1G includes a circuit assembly 160. However, in other embodiments, the chip package 100 may not include the circuit assembly 160, and both the first chip 110 and the second chip 120 may be mounted on the first chip 110 and the second chip 120. At least one of the one surface 151a and the second surface 151b. For example, the first wafer 110 and the second wafer 120 are mounted on the first surface 151a and the second surface 151b, respectively. Alternatively, the first chip 110 and the second chip 120 are mounted on the same surface of the circuit substrate 210 (ie, the first surface 151a or the second surface 151b). In this way, the first chip 110 and the second chip 120 can be electrically connected to the circuit substrate 210 through the carrier 150. In addition, the first chip 110 and the second chip 120 can also be mounted on the carrier 150 by flip chip or wire bonding. Therefore, FIG. 1G does not limit the electrical connection between the first chip 110 and the second chip 120 and the circuit substrate 210.

In addition, in other embodiments, the backside (not labeled) of the first chip 110 may also be thermally coupled to the thermally conductive pad 154p on the first surface 151a, and the second chip 120 may have a connection pad, which is the same as the first chip 110 The connection pad 111 of the second chip 120 can be thermally coupled to the thermally conductive pad 154p on the second surface 151b. Therefore, FIG. 1G does not limit the thermal coupling between the first chip 110 and the second chip 120 and the thermal pad 154p.

The manufacturing process of the circuit board assembly 200 will be described below in conjunction with FIGS. 1A to 1G. It should be noted that since the carrier 150 may include only one inner layer circuit layer 152a or not include any inner layer circuit layer 152a, and the chip package 100 may only include one chip (for example, the first chip 110 and the second chip 120 is only one of them), or it includes more than three chips. Therefore, there are many manufacturing processes of the circuit board assembly 200, and FIGS. 1A to 1G only disclose the manufacturing process of at least one of the circuit board assemblies 200.

1A, in the manufacturing process of the circuit board assembly 200, first, a core substrate 15 is provided. The core substrate 15 may include an insulating layer L52, a plurality of inner circuit layers 152a, a plurality of metal layers M41, and a plurality of conductive layers. Column V52. Next, insulating layers L51 and L53 are respectively formed on opposite sides of the core substrate 15. At this time, the insulating layers L51 and L53 completely cover the metal layers M41 and the inner circuit layers 152a.

Please refer to FIGS. 1B and 1C, wherein FIG. 1C is a schematic top view, and FIG. 1B is a schematic cross-sectional view drawn along the line 1B-1B in FIG. 1C. Next, a plurality of blind holes H51 and H52 are formed on the insulating layers L51 and L53, and a plurality of trenches T51 are formed in these insulating layers L51, L52, and L53. These blind holes H51 and H52 can be formed by laser drilling or mechanical drilling, and these grooves T51 can be formed by routing. It should be noted that FIG. 1C is drawn under the condition that the blind holes H51 and H52 and the inner circuit layer 152a are omitted. Therefore, the blind holes H51 and H52 are shown in FIG. 1B and not shown in FIG. 1C.

Each trench T51 extends from the first surface 151a of the insulating layer L51 to the second surface 151b of the insulating layer L53, so these trenches T51 are formed through the insulating layers L51, L52, and L53. In addition, the core substrate 15 has a plurality of units 15u and scribe-line cuts 15c, wherein the single units 15u can be arranged in an array. The shape of the cutting lane 15c may be a mesh shape and distributed around the single particles 15u. These grooves T51 are located in the cutting lane 15c, and are adjacent to the single particles 15u, respectively. These trenches T51 are separated from each other without communicating, so these single particles 15u are still connected to each other. Therefore, immediately after the formation of these trenches T51, the core substrate 15 still remains a single substrate, and has not been cut into a plurality of separate individual particles 15u.

1D, then, a plurality of metal parts M42 and a plurality of conductive pillars V52 are respectively formed in the blind holes H51 and H52, wherein the metal parts M42 are formed in the blind holes H51, and the conductive pillars V52 are formed in the blind holes H52 . Two outer circuit layers 152b and a plurality of thermal pads 154p are formed on the first surface 151a and the second surface 151b, respectively, and a plurality of heat dissipation pads 153 are respectively formed in the trenches T51.

The method of forming the metal part M42, the conductive pillar V52, the outer circuit layer 152b, the plurality of thermally conductive pads 154p, and the heat dissipating pad 153 may include lithography and electroplating. The metal part M42, the heat conductive pad 154p and the heat dissipating pad 153 may be in the same way. Manufactured in the electroplating process. The metal parts M42, the thermal pad 154p, and the heat dissipation pad 153 connected to each other may be integrally formed. In other words, there will be no obvious seams or joints where the metal part M42, the thermal pad 154p and the heat dissipation pad 153 are connected. After that, the insulating layers L51 and L53 and the core substrate 15 are cut along the cutting lane 15c (see FIG. 1C) to form a plurality of carrier boards 150 separated from each other.

Please refer to FIGS. 1E and 1F, in which FIG. 1E is a schematic top view, and FIG. 1F is a schematic cross-sectional view drawn along the line 1F-1F in FIG. 1E. Then, insulating protection layers 159a and 159b may be formed on the first surface 151a and the second surface 151b, respectively, wherein the insulating protection layers 159a and 159b will expose the thermal pad 154p and partially expose the outer circuit layers 152b. Then, the first wafer 110 is mounted on the first surface 151a. Thereafter, a molding material 191 covering and covering the first wafer 110 may be formed on the first surface 151a. Then, a plurality of metal pillars 192 and a plurality of circuit pads 193 penetrating through the molding material 191 can be formed, wherein the circuit pads 193 are electrically connected to the metal pillars 192 respectively.

Please refer to FIG. 1G. Next, the second chip 120 can be mounted on the second surface 151b to form a circuit component 160, wherein the circuit component 160 can be formed by a stacking method or a build-up method. So far, the chip package 100 has been substantially completed. Then, the chip package 100 is mounted on the circuit substrate 210 to form a circuit board assembly 200, wherein the heat dissipation pad 153 of the chip package 100 is thermally coupled to the heat conducting member 213 of the circuit substrate 210.

FIG. 2A is a schematic cross-sectional view of an electronic device according to another embodiment of the invention. 2A, the electronic device 400 of this embodiment can be a smart phone, a notebook computer, a tablet computer, a desktop computer, or a display, and includes a chip package 300, a housing 410, and a circuit pattern 420. The housing 410 has a surface 411 a, in which the circuit pattern 420 is located on the surface 411 a, and the chip package 300 is mounted on the surface 411 a and is electrically connected to the circuit pattern 420. Taking FIG. 2A as an example, the chip package 300 can be electrically connected to the circuit pattern 420 by ultrasonic welding. Alternatively, the chip package 300 may also be electrically connected to the circuit pattern 420 by wire bonding or a plurality of solder balls B1 (see FIG. 1G).

The wiring pattern 420 may be formed on the surface 411a by electroless plating. Specifically, the housing 410 may have a plurality of catalyst particles (not shown), wherein the catalyst particles can chemically react with the ions in the electroplating solution after being activated, so that the ions are reduced to metal deposits. Thus, the wiring pattern 420 is formed. The method of activating the catalyst particles may be laser irradiation. In other words, the catalyst particles will be activated after being irradiated by the laser, and then can reduce the ions. Regarding the formation of the above-mentioned catalyst particles and the circuit pattern 420, please refer to the patent cases of Taiwan Publication No. I362906 and I361643.

The chip package 300 is similar to the chip package 100 in the foregoing embodiment. For example, both chip packages 300 and 100 include the same and similar components, such as a first chip 110, a second chip 120, a circuit assembly 160, a heat dissipation pad 153, and a carrier 350, where the first chip 110 may be located Between the surface 411a and the carrier 350. The difference between the chip packages 300 and 100 is only: the multiple connectors 354c included in the carrier 350.

2B is a schematic top view of the electronic device 400 in FIG. 2A after the circuit component 160 and the second chip 120 are removed, wherein FIG. 2A is drawn along the line 2A-2A in FIG. 2B, and FIG. 2B may show heat conduction The top view of the pad 154p. 2A and 2B, each connecting member 354c may include a metal layer M41 and a metal member M82, wherein the metal member M82 is a metal block and has a width W82 and a thickness T82, and the ratio between the thickness T82 and the width W82 can be Less than 0.2 (ie 1:5). Therefore, the width W82 of the metal part M82 is obviously larger than the thickness T82 of the metal part M82, as shown in FIG. 2A.

From FIG. 2B, the shape of the metal piece M82 can be rectangular, and the metal piece M82 shown in FIG. 2B obviously has a pair of short sides and a pair of long sides (none of them), and the width W82 can be substantially equal to the metal piece. The length of the short side of M82 is shown in Figure 2B. These metal parts M82 can quickly transfer the heat generated by both the first chip 110 and the second chip 120 to the heat dissipation pad 153 to help the heat dissipate and avoid or reduce the accumulation of heat on the first chip 110 and the second chip 120 .

The electronic device 400 further includes a heat dissipation portion 430 thermally coupled to the heat dissipation pad 153, wherein the heat dissipation portion 430 may be a metal layer, and the formation method of the heat dissipation portion 430 may be the same as the formation method of the circuit pattern 420. For example, the heat dissipation part 430 may be formed using the above-mentioned catalyst particles. The heat dissipating part 430 can be directly connected to the heat dissipating pad 153 by ultrasonic welding. Alternatively, the heat dissipating portion 430 may also be thermally coupled to the heat dissipating pad 153 by using a thermally conductive material HD1 (please refer to FIG. 1G). In addition, in other embodiments, the heat dissipation portion 430 may simply directly contact the heat dissipation pad 153, but the heat dissipation portion 430 and the heat dissipation pad 153 are not connected to each other.

The housing 410 may include a base 411 and a wall 412, wherein the wall 412 is connected to the base 411. For example, the wall 412 and the base 411 are integrally formed, and the material of the wall 412 and the base 411 can be plastic with electrical insulation, and can be made by injection molding. The base 411 has a surface 411 a, and the wall 412 is located opposite to the heat dissipation pad 153, wherein the heat dissipation portion 430 can be located between the wall 412 and the heat dissipation pad 153.

It should be noted that, in the embodiment shown in FIGS. 2A and 2B, the heat dissipation portion 430 may be a metal layer. However, in other implementations, the heat dissipation portion 430 may be a metal housing or heat dissipation fins of the electronic device 400, and the housing 410 may be a support without a wall 412, that is, the housing 410 may be equal to the base 411. Therefore, the heat dissipation part 430 is not limited to being a metal layer. In addition, not only can one of the first chip 110 and the second chip 120 in FIG. 2A be omitted, but the set of connectors 354c and the thermal pad 154p thermally coupled to the omitted chip can also be omitted. Therefore, FIG. 2A does not limit the number of chips (for example, the first chip 110 and the second chip 120) in the chip package 300, the number of connectors 354c, and the number of thermal pads 154p.

It is worth mentioning that in the chip package 100 shown in FIG. 1G, at least one connector 154c can be replaced with a connector 354c as shown in FIG. 2A, and the chip package 300 shown in FIG. 2A can also be installed On the circuit substrate 210. In other words, the chip package 300 can also be applied to the circuit board assembly 200. Similarly, in the chip package 300 shown in FIG. 2A, at least one connector 354c can be replaced with the connector 154c shown in FIG. 1G, and the chip package 100 shown in FIG. 1G can also be installed in the housing 410 , And electrically connected to the circuit pattern 420, that is, the chip package 100 can also be applied to the electronic device 400.

In summary, by using the heat conducting portion and the heat dissipating pad, the heat generated by the chip (such as the first chip 110) in the chip package can be quickly transferred to the heat dissipating pad, so that the heat is dissipated to the external environment, thereby reducing or Avoid accumulation of heat energy. In this way, the chip package disclosed in at least one embodiment of the present invention can prevent the chip from being degraded or damaged due to overheating, thereby facilitating the packaging of today's powerful chips.

Although this creation has been disclosed in the above embodiments, it is not intended to limit this creation. Those with ordinary knowledge in the technical field to which this creation belongs can make some changes and modifications without departing from the spirit and scope of this creation. Therefore, this creation The scope of creation protection shall be subject to the scope of the attached patent application.

15: core substrate 15c: cutting track 15u: single 100, 300: chip package 110: The first chip 111: connection pad 120: second chip 150, 350: carrier board 151: Insulation part 151a: first surface 151b: second surface 151c: side wall surface 152: Line structure 152a: inner circuit layer 152b: Outer circuit layer 153: Thermal pad 154: Heat conduction part 154c, 354c: connectors 154p: thermal pad 159a, 159b, 169: insulating protective layer 160: line components 161, L51, L52, L53: insulating layer 162, 212: circuit layer 191: molding material 192: Metal column 193: line pad 200: Circuit board assembly 210: circuit board 211: Subject 213: Thermal conductive parts 410: Shell 411: base 411a: Surface 412: Wall 420: Line pattern 430: Heat Dissipation Department A13: Fixed part B1: Solder ball H51, H52: blind hole HD1: Thermally conductive material M41: Metal layer M42, M82: metal parts S13: Thermal conductive sheet T51: groove T82: Thickness V52, V62: conductive pillar W82: width

1A to 1G are schematic diagrams of the manufacturing process of the circuit board assembly according to at least one embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of an electronic device according to another embodiment of the invention. 2B is a schematic top view of the electronic device in FIG. 2A after the circuit assembly and the second chip are removed.

100: chip package

110: The first chip

111: connection pad

120: second chip

150: carrier board

151: Insulation part

151a: first surface

151b: second surface

151c: side wall surface

152: Line structure

152a: inner circuit layer

152b: Outer circuit layer

153: Thermal pad

154: Heat conduction part

154c: connector

154p: thermal pad

159a, 159b, 169: insulating protective layer

160: line components

161, L51, L52, L53: insulating layer

162, 212: circuit layer

191: molding material

192: Metal column

193: line pad

200: Circuit board assembly

210: circuit board

211: Subject

213: Thermal conductive parts

A13: Fixed part

B1: Solder ball

HD1: Thermally conductive material

M41: Metal layer

M42: Metal parts

S13: Thermal conductive sheet

V52, V62: conductive pillar

Claims (20)

A chip package includes: A carrier board, including: An insulating part having a first surface, a second surface opposite to the first surface, and a side wall surface located between the first surface and the second surface; A circuit structure located in the insulating part, wherein a part of the circuit structure is exposed on the first surface; A heat dissipation pad fixed on the side wall surface; A heat conducting part located in the insulating part and thermally coupled to the heat dissipating pad; and A first chip is installed on the first surface and electrically connected to the circuit structure, wherein the first chip is thermally coupled to the heat conducting portion. The chip package according to claim 1, wherein both the heat conducting portion and the heat dissipation pad are separated from the circuit structure and electrically insulated from each other, and the first chip is electrically insulated from the heat conducting portion and the heat sink pad. The chip package according to claim 1, wherein the heat conducting part includes: A thermal pad located on the first surface and thermally coupled to the first chip, wherein the first chip is disposed on the thermal pad; and A connecting piece is located in the insulating part and thermally couples the heat-conducting pad and the heat-dissipating pad. The chip package according to claim 3, wherein the thermal pad is connected to the thermal pad, and the thermal pad and the thermal pad are integrally formed. The chip package according to claim 3, wherein the first chip has a connection pad, and the connection pad is thermally coupled to the heat conduction pad, and the connection pad is electrically insulated from the circuit structure. The chip package according to claim 3, wherein the connector includes: A metal layer directly contacting the heat dissipation pad; and At least one metal piece is located between the metal layer and the thermal pad, and connects the metal layer and the thermal pad. The chip package according to claim 6, wherein the connecting member includes a plurality of the metal members, and the metal members are a plurality of metal pillars. The chip package according to claim 6, wherein the insulating portion includes a plurality of insulating layers stacked on each other, and two of the insulating layers respectively have the first surface and the second surface; The circuit structure includes at least one inner circuit layer and two outer circuit layers. The outer circuit layers are located on the first surface and the second surface, respectively, and the outer circuit layer on the first surface is electrically connected to the first surface. A chip, and the at least one inner circuit layer and the metal layer are located between two insulating layers. The chip package as described in claim 1, further including: A second chip is disposed on the second surface and is electrically connected to the circuit structure, wherein the second chip is thermally coupled to the heat-conducting part and is electrically insulated from the heat-conducting part and the heat-dissipating pad. The chip package according to claim 9, wherein the heat conducting part includes: A plurality of thermally conductive pads are respectively located on the first surface and the second surface, and are thermally coupled to the first chip and the second chip respectively, wherein the first chip and the second chip are respectively disposed on the thermally conductive pads; as well as A plurality of connecting elements connect the heat-conducting pads and the heat-dissipating pads. The chip package according to claim 10, wherein a backside of the second chip is thermally coupled to the thermal pad on the second surface. The chip package according to claim 10, wherein each of the connectors includes: A metal layer directly contacting the heat dissipation pad; and At least one metal piece is located between the adjacent metal layer and the thermal pad, and connects the adjacent metal layer and the thermal pad. The chip package according to claim 12, wherein the insulating portion includes a plurality of insulating layers stacked on each other, and two of the insulating layers respectively have the first surface and the second surface; The circuit structure includes at least one inner circuit layer and two outer circuit layers. The outer circuit layers are located on the first surface and the second surface, respectively, and the outer circuit layer on the first surface is electrically connected to the first surface. A chip, and the at least one inner circuit layer and the metal layers are located between two insulating layers. The chip package according to claim 9 further includes a circuit assembly, wherein the second chip is located between the carrier board and the circuit assembly, and the circuit assembly is electrically connected to the second chip and the carrier board. A circuit board assembly, including: A circuit substrate, including a main body, a heat conduction element and a circuit layer, wherein the heat conduction element and the circuit layer are both located on the main body; and A chip package according to any one of claims 1 to 14, mounted on the main body of the circuit substrate and electrically connected to the circuit layer, wherein the heat dissipation pad is thermally coupled to the heat conducting element. The circuit board assembly according to claim 15, wherein the heat conducting element includes: A fixing part fixed on the main body; and A thermally conductive sheet is connected to the fixed portion and extends from the fixed portion, wherein the thermally conductive sheet is thermally coupled to the heat dissipation pad. The circuit board assembly according to claim 15, wherein the first chip is located between the circuit substrate and the carrier board. An electronic device, including: A shell with a surface; A circuit pattern located on the surface; A chip package according to any one of claims 1 to 14, mounted on the surface and electrically connected to the circuit pattern; and A heat dissipating part, thermally coupled to the heat dissipating pad. The electronic device according to claim 18, wherein the first chip is located between the surface of the housing and the carrier board. The electronic device according to claim 18, wherein the housing includes: A substrate having the surface; and A wall is connected to the base and is located opposite to the heat dissipation pad, wherein the heat dissipation portion is located between the wall and the heat dissipation pad.

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