TWM605766U - Error signal processing circuit, pulse width modulation system and pulse frequency modulation system - Google Patents

Abstract

This creation provides an error signal processing circuit, pulse width modulation and pulse frequency modulation system. The error signal processing circuit provided by this creative embodiment is applied to a pulse width modulation or pulse frequency modulation system. The circuit includes a pulse signal generator. The pulse signal generator is used to receive the input reference voltage and the feedback signal of the system to generate a digital signal. Pulse signal; digital integrator, the input terminal of the digital integrator can be connected to the output terminal of the pulse signal generator; and digital analog converter, the input terminal of the digital analog converter can be connected to the output terminal of the digital integrator, and digital analog The converter is used to output analog signals. Through the above-mentioned scheme, a series of signal processing is carried out, and the error signal amplification and loop compensation are realized with circuit control and extremely low capacitance value.

Description

Error signal processing circuit, pulse width modulation and pulse frequency modulation system

This creation belongs to the field of integrated circuits, and in particular relates to an error signal processing circuit, pulse width modulation and pulse frequency modulation system.

The disadvantage of the traditional Pulse Width Modulation (PWM)/Pulse Frequency Modulation (PFM) system is that for some low-frequency signal systems, if it needs to meet the high power factor (PF) Power frequency signal processing system requires extremely low control loop bandwidth to achieve loop compensation. In this case, the capacitance of the compensation unit is often on the order of uF, and such compensation capacitance cannot be implemented in an integrated circuit chip. , Usually need to design a separate external capacitor, which will have an adverse effect on the system volume, cost and reliability.

This creative embodiment provides an error signal processing circuit, pulse width modulation and pulse frequency modulation system, which can use a pulse signal generator, a digital integrator and a digital analog converter to perform a series of processing on the signal, and use the circuit to control and The low capacitance value realizes error signal amplification and loop compensation.

In the first aspect, this creative embodiment provides an error signal processing circuit applied to pulse width modulation or pulse frequency modulation systems. The error signal processing circuit includes: a pulse signal generator, which is used to receive an input reference voltage and System feedback signal to generate digital pulse signal; digital integrator, the input end of the digital integrator can be connected to the output end of the pulse signal generator; and digital analog converter, the input end of the digital analog converter can be connected to the digital integration The output terminal of the converter, and the digital-to-analog converter is used to output the analog signal.

According to the error signal processing circuit provided in the first aspect, the pulse signal generator includes: an error voltage amplifier, and the input end of the error voltage amplifier is used to receive the input reference voltage and the system System feedback signal; and a voltage-to-frequency converter. The input of the voltage-to-frequency converter can be connected to the output of the error voltage amplifier, and the output of the voltage-to-frequency converter can be connected to the input of the digital integrator.

According to the error signal processing circuit provided in the first aspect, the pulse signal generator includes: an error transconductance amplifier, the input of the error transconductance amplifier is used to receive the input reference voltage and the feedback signal of the system; and the current-to-frequency converter, and the current-to-frequency conversion The input terminal of the converter can be connected to the output terminal of the error transconductance amplifier, and the output terminal of the current-to-frequency converter can be connected to the input terminal of the digital integrator.

The error signal processing circuit provided according to the first aspect further includes: a clamp cell voltage generator for generating a clamp cell voltage based on the output signal of the digital-to-analog converter, and outputting the clamp cell voltage To digital-to-analog converter, used to clamp the output signal of the digital-to-analog converter.

According to the error signal processing circuit provided in the first aspect, the clamp element voltage generator is used to generate the clamp element voltage based on the output signal of the digital-to-analog converter, including: the clamp element voltage generator is used for the output signal of the digital-to-analog converter The clamping cell voltage is generated when the voltage is greater than the upper threshold voltage and/or when the output signal of the digital-to-analog converter is lower than the lower threshold voltage.

The error signal processing circuit provided according to the first aspect further includes: a digital clamp element signal generator, which is used to generate a digital clamp element signal based on the output signal of the digital analog converter and output it to the digital The integrator is used to clamp the output signal of the digital-to-analog converter.

According to the error signal processing circuit provided in the first aspect, the digital clamp element signal generator is used to generate a digital clamp element signal based on the output signal of the digital analog converter, including: the digital clamp element signal generator is used in the digital analog converter When the output signal of is greater than the upper threshold level and/or when the output signal of the digital-to-analog converter is less than the lower threshold level, a digital clamp signal is generated.

In the second aspect, this creative embodiment provides a pulse width modulation system, including: the error signal processing circuit as in the first aspect; a pulse width modulation control unit, and the input end of the pulse width modulation control unit can be connected to the error signal The output terminal of the processing circuit; and the driver, the input terminal of the driver can be connected to the output terminal of the pulse width modulation control unit to output the driver Signal.

In the third aspect, this creative embodiment provides a pulse frequency modulation system, including: the error signal processing circuit as in the first aspect; a pulse frequency modulation control unit, the input of the pulse frequency modulation control unit can be connected to the error signal The output terminal of the processing circuit; and the driver. The input terminal of the driver can be connected to the output terminal of the pulse frequency modulation control unit to output a driving signal.

The error signal processing circuit, pulse width modulation and pulse frequency modulation system of this creative embodiment can use a pulse signal generator, a digital integrator and a digital analog converter to perform a series of processing on the signal, using circuit control and extremely low The capacitance value realizes the error signal amplification and loop compensation.

100, 200, 300, 700, 800: Error signal processing circuit

101, 201: Pulse signal generator

102: Digital Integrator

103: Digital Analog Converter (DAC)

104: Digital pulse signal

105: digital signal

106: Output voltage signal

107: Output current signal

108: Clamping element voltage generator

109: Digital clamp signal generator

110: control unit

120: drive

1011: Error voltage amplifier

1012: voltage to frequency converter

2011: Error transconductance amplifier

2012: Current to frequency converter

D1: Digital clamp signal

V1: Clamping cell voltage

Vref: reference voltage

F+, F-, FB, I+, I-, V+, V-, Vc: signal

In order to more clearly explain the technical solution of this creative embodiment, the following will briefly introduce the schemas that need to be used in this creative embodiment. For those of ordinary skill in the art, without creative work, Other schemas can be obtained from these schemas.

Figure 1 shows a schematic structural diagram of an error signal processing circuit provided by an embodiment of the invention;

FIG. 2 shows a schematic structural diagram of a specific implementation of an error signal processing circuit provided by an embodiment of the present creation;

Figure 3 shows a schematic structural diagram of a modulation system provided by an embodiment of the author;

FIG. 4 shows a schematic structural diagram of another specific implementation of an error signal processing circuit provided by an embodiment of the present creation;

Figure 5 shows a schematic structural diagram of a modulation system provided by another embodiment of the author;

6 shows a schematic diagram of the corresponding relationship between multiple signals and time of the error signal processing circuit or modulation system provided in the foregoing embodiment;

FIG. 7 shows a schematic structural diagram of an error signal processing circuit provided by another embodiment of the present creation; and

Figure 8 shows a schematic structural diagram of an error signal processing circuit provided by another embodiment of the present creation

The features and exemplary embodiments of each aspect of the creation will be described in detail below. In order to make the purpose, technical solutions, and advantages of the creation clearer, the creation will be further described in detail below in conjunction with the drawings and specific embodiments. It should be understood that the specific embodiments described here are only configured to explain the creation, and not configured to limit the creation. For those skilled in the art, this creation can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present creation by showing an example of the present creation.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply one of these entities or operations. There is any such actual relationship or order between. Moreover, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also includes Other elements of, or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the elements defined by the sentence "including..." do not exclude the existence of other same elements in the process, method, article, or equipment including the elements.

In order to solve the conventional technical problem, this creative embodiment provides an error signal processing circuit, pulse width modulation and pulse frequency modulation system. First of all, the error signal processing circuit provided by the first embodiment of this creation will be introduced below. Figure 1 shows a schematic structural diagram of an error signal processing circuit provided by an embodiment of the author.

In the embodiment shown in FIG. 1, the error signal processing circuit 100 can be applied to a pulse width modulation (Pulse Width Modulation, PWM) or pulse frequency modulation (Pulse Frequency Modulation, PFM) system, and the error signal processing circuit 100 may include: a pulse signal generator 101, the pulse signal generator 101 can be used to receive the input reference voltage (for example, Vref) and the feedback signal of the system (for example, FB) to generate a digital pulse signal 104 (for example, F+ and F-); digital integrator 102, the input end of the digital integrator 102 can be connected to the output end of the pulse signal generator 101; and digital to analog converter (Digital to Analog Converter (DAC) 103, the input terminal of the digital-to-analog converter 103 can be connected to the output terminal of the digital integrator 102, and the digital-to-analog converter 103 can be used to output an analog signal (for example, Vc).

As an example, the pulse signal generator 101 can perform error voltage amplification and conversion on the signals Vref and FB to obtain an output signal (for example, an output voltage signal or an output current signal), and then perform a series of processing on the output signal to output The corresponding digital pulse signal 104.

It should be noted that the error signal processing circuit 100 can be equivalent to an error amplifier with a larger output equivalent capacitance. Therefore, through the above-mentioned solution provided by this creative embodiment, a series of signal processing is carried out by using a pulse signal generator, a digital integrator, and a digital-to-analog converter, etc., and a circuit control and extremely low capacitance value are used to achieve error signal amplification and Loop compensation.

In addition, the error signal processing circuit provided by this creation can be applied to PWM or PFM signal processing and system control fields, including but not limited to power management, motor control, and Light Emitting Diode (LED) lighting.

The following describes in detail the error signal processing circuit provided by an embodiment of the present creation by means of specific examples. Referring to FIG. 2, FIG. 2 shows a schematic structural diagram of a specific implementation of the error signal processing circuit provided by an embodiment of the present creation.

As an example, as shown in FIG. 2, the error signal processing circuit 200 may include a pulse signal generator 101, a digital integrator 102 and a DAC 103. The pulse signal generator 101 may include an error voltage amplifier 1011 and a voltage-to-frequency converter 1012 (for example, a V/F converter).

In the embodiment shown in FIG. 2, the input terminal of the error voltage amplifier 1011 can be used to receive the input reference voltage (for example, Vref) and the feedback signal of the system (for example, FB), and the input terminal of the voltage-to-frequency converter 1012 can be Connected to the output terminal of the error voltage amplifier 1011, and the output terminal of the voltage-to-frequency converter 1012 can be connected to the input terminal of the digital integrator 102.

As an example, the error voltage amplifier 1011 can be used to amplify the error voltage of the signals Vref and FB and convert them into, for example, an output voltage signal 106 (for example, V+ and V-), which is passed through a voltage-to-frequency converter 1012 Processing to output the corresponding Digital pulse signal 104 (for example, F+ and F-), the digital pulse signal 104 can be input to the digital integrator 102, used as the up or down count of the integration counter and generate the digital signal 105, the digital signal 105 can be input to the DAC In 103, the DAC 103 can be used to convert the digital signal 105 into a corresponding analog voltage signal (for example, Vc).

It should be noted that the same elements in the embodiment shown in FIG. 2 and the embodiment shown in FIG. 1 are marked with the same drawings, and in order to simplify the description, the same elements and the connection relationship between the two are not repeated here.

In addition, this creative embodiment also provides a modulation system (for example, a pulse width modulation or pulse frequency modulation system). Refer to FIG. 3, which shows a schematic structural diagram of a modulation system provided by an embodiment of the present creation.

In the embodiment shown in FIG. 3, the modulation system may include the error signal processing circuit 200 as described in FIG. 1 or FIG. 2, a control unit 110 (for example, a PWM or PFM control unit), a driver 120, and the like.

The input terminal of the error signal processing circuit 200 can be used to receive Vref and FB to output the analog voltage signal Vc, and the output terminal of the error signal processing circuit 200 can be connected to the input terminal of the control unit 110 to convert the analog voltage signal Vc Send to the control unit 110, the control unit 110 can output a PWM or PFM signal based on the analog voltage signal Vc, the output end of the control unit 110 can be connected to the input end of the driver 120 to send the PWM or PFM signal to the driver 120, the driver 120 It can be used to amplify the input PWM or PFM signal and enhance the drive, and then output the drive signal to drive the power switch of the system (for example, PWM system or PFM system) for closed-loop control.

It should be understood that, in some embodiments, when the modulation system is a pulse width modulation system, the control unit 110 is a PWM control unit, and the output of the control unit 110 is a PWM signal; in other embodiments, when the modulation is When the system is a pulse frequency modulation system, the control unit 110 is a PFM control unit, and the output of the control unit 110 is a PFM signal.

The error signal processing circuit provided by another embodiment of the present creation will be introduced in detail below by way of specific examples. Referring to FIG. 4, FIG. 4 shows a schematic structural diagram of another specific implementation of the error signal processing circuit provided by an embodiment of the present creation.

As an example, as shown in FIG. 4, the error signal processing circuit 300 may include a pulse signal generator 201, a digital integrator 102, and a DAC 103. The pulse signal generator 201 may include an error transconductance amplifier 2011 (for example, Gm) and a current-to-frequency converter 2012 (for example, an I/F converter).

In the embodiment shown in FIG. 4, the input terminal of the error transconductance amplifier 2011 can be used to receive the input reference voltage (for example, Vref) and the feedback signal of the system (for example, FB), and the input terminal of the current-to-frequency converter 2012 It may be connected to the output terminal of the error transconductance amplifier 2011, the output terminal of the current-to-frequency converter 2012 may be connected to the input terminal of the digital integrator 102, and the output terminal of the digital integrator 102 may be connected to the input terminal of the DAC 103.

As an example, the error transconductance amplifier 2011 can be used to amplify the error voltage of the signals Vref and FB and convert them into, for example, an output current signal 107 (for example, I+ and I-), and the output current signal 107 is passed through a current-to-frequency converter The processing in 2012 is to output the corresponding digital pulse signal 104 (for example, F+ and F-). The digital pulse signal 104 can be input into the digital integrator 102 to be used as the up or down count of the integrating counter and generate the digital signal 105. The digital signal 105 can be input to the DAC 103, and the DAC 103 can be used to convert the digital signal 105 into a corresponding analog voltage signal (for example, Vc).

It should be noted that the same elements in the embodiment shown in FIG. 4 and the embodiment shown in FIG. 2 are marked with the same drawings, and in order to simplify the description, the same elements and connection relationship between the two are not repeated here.

In addition, the embodiments shown in FIG. 2 and FIG. 4 are two different implementations of the embodiment shown in FIG. 1. The main difference between the two is: in the exemplary system shown in FIG. 2, the pulse The signal generator 101 may include an error voltage amplifier 1011 and a voltage-to-frequency converter 1012; and in the exemplary system shown in FIG. 4, the pulse signal generator 201 may include an error transconductance amplifier 2011 (for example, Gm) and a current-frequency converter器2012. Other elements are the same or similar. To simplify the description, the same parts between the two are not repeated here.

In addition, this creative embodiment also provides a modulation system (for example, a pulse width modulation or pulse frequency modulation system). Referring to FIG. 5, FIG. 5 shows a schematic structural diagram of a modulation system provided by another embodiment of the present creation.

In the embodiment shown in FIG. 5, the modulation system may include the error signal processing circuit 300, the control unit 110 (for example, the PWM or PFM control unit), and the driver 120 as described in FIG.

The input terminal of the error signal processing circuit 300 can be used to receive Vref and FB and output the analog voltage signal Vc, and the output terminal of the error signal processing circuit 300 can be connected to the input terminal of the control unit 110 to transmit the analog voltage signal Vc To the control unit 110, the control unit 110 can be used to output a PWM or PFM signal based on the analog voltage signal Vc. The output end of the control unit 110 can be connected to the input end of the driver 120 to transmit the PWM or PFM signal to the driver 120. 120 can be used to amplify the input PWM or PFM signal and enhance the drive, and then output the drive signal to drive the power switch of the system (for example, the PWM system or the PFM system) for closed-loop control.

It should be understood that, in some embodiments, when the modulation system is a pulse width modulation system, the control unit 110 is a PWM control unit, and the control unit 110 outputs a PWM signal; in other embodiments, when the modulation system In the case of a pulse frequency modulation system, the control unit 110 is a PFM control unit, and the output of the control unit 110 is a PFM signal.

In addition, the exemplary system shown in FIG. 5 is similar to the exemplary system shown in FIG. 3, and the main difference between the two is: in the exemplary system shown in FIG. 3, the pulse signal generator 101 may include The error voltage amplifier 1011 and the voltage-to-frequency converter 1012; and in the exemplary system shown in FIG. 5, the pulse signal generator 201 may include an error transconductance amplifier 2011 (for example, Gm) and a current-to-frequency converter 2012. Other elements are the same or similar. To simplify the description, the same parts between the two are not repeated here.

Referring to FIG. 6, FIG. 6 shows a schematic diagram of the corresponding relationship between multiple signals and time of the error signal processing circuit or modulation system provided in the foregoing embodiment.

As shown in Figure 6, when the feedback signal FB is lower than the reference voltage Vref, the accumulative count signal (for example, F+) generated by the V/F converter or the I/F converter has a digital pulse signal output, and its pulse frequency follows The voltage difference between the signals FB and Vref changes. For example, the greater the voltage difference between signals FB and Vref, the higher the frequency, and the smaller the voltage difference between signals FB and Vref. The lower, and when the feedback signal FB is lower than the reference voltage Vref, the count signal (for example, F-) is output as a countless pulse signal.

In addition, the Vc signal output by the DAC 103 changes with the change of the voltage difference between the signals FB and Vref. For example, the Vc signal becomes larger as the voltage difference between the signals FB and Vref decreases, and the rate of change of the Vc signal curve corresponds to the frequency of the F+ signal. For example, the rate of change of the Vc signal curve decreases with the frequency of the F+ signal. Small and reduce.

However, when the feedback signal FB is higher than the reference voltage Vref, the count-up signal (for example, F-) generated by the V/F converter or the I/F converter has a digital pulse signal output, and its pulse frequency increases with FB and The voltage difference of Vref changes. For example, the greater the voltage difference between the signals FB and Vref, the higher the frequency, and the smaller the voltage difference between the signals FB and Vref, the lower the frequency, and when the feedback signal FB is higher than the reference voltage Vref, the count signal (for example, F+ ) Numerous pulse signal output.

In addition, the Vc signal output by the DAC 103 changes with the change of the voltage difference between the signals FB and Vref. For example, the Vc signal decreases as the voltage difference between the signals FB and Vref increases, and the rate of change of the Vc signal curve corresponds to the frequency of the F-signal. For example, the rate of change of the Vc signal curve increases with the frequency of the F-signal. The increase increases.

Secondly, the error signal processing circuit provided by the second embodiment of this creation will be introduced below. FIG. 7 shows a schematic structural diagram of an error signal processing circuit provided by another embodiment of the present creation.

It should be noted that the exemplary error signal processing circuit 700 shown in FIG. 7 is similar to the exemplary error signal processing circuit 100 shown in FIG. 1, except that the exemplary error signal processing circuit 700 shown in FIG. 7 includes In addition to the various components in the exemplary error signal processing circuit 100 shown in FIG. 1, a clamp cell voltage generator 108 may also be included.

As an example, the clamp cell voltage generator 108 can be used to generate a clamp cell voltage (for example, V1) based on the output signal (for example, Vc) of the DAC 103, and output the clamp cell voltage V1 to the DAC 103, The output signal of the DAC 103 is clamped.

In some embodiments, the clamp cell voltage generator is used to generate the clamp cell voltage based on the output signal of the DAC, including: the clamp cell voltage generator 108 is used in the DAC 103 When the output signal Vc is greater than the upper threshold voltage and/or when the output signal Vc of the DAC 103 is less than the lower threshold voltage, a clamp cell voltage (for example, V1) is generated.

As an example, the clamp cell voltage (for example, V1) is generated by monitoring and sensing the output signal (for example, Vc) of the signal DAC 103.

In the first embodiment, if the signal Vc is greater than the upper threshold voltage, the clamp cell voltage generator 108 may generate a first clamp cell voltage to clamp the signal Vc based on the first clamp cell voltage (to prevent Further increase); In the second embodiment, if the signal Vc is less than the lower threshold voltage, the clamp cell voltage generator 108 may generate a second clamp cell voltage to clamp the signal Vc based on the second clamp cell voltage Bit (to prevent further reduction); in the third embodiment, if the signal Vc is greater than the upper threshold voltage or the signal Vc is less than the lower threshold voltage, the clamp cell voltage generator 108 may generate a third clamp cell voltage based on The third clamp element voltage is used to clamp the signal Vc (to prevent further increase or decrease).

It should be noted that the above specific implementation methods can be set according to needs, and this creation does not limit it.

Once again, the error signal processing circuit provided by the third embodiment of the present creation will be introduced below. FIG. 8 shows a schematic structural diagram of an error signal processing circuit provided by another embodiment of the present invention.

It should be noted that the exemplary error signal processing circuit 800 shown in FIG. 8 is similar to the exemplary error signal processing circuit 100 shown in FIG. 1, and the difference between the two is mainly: the exemplary error signal shown in FIG. 8 In addition to the components of the exemplary error signal processing circuit 100 shown in FIG. 1, the processing circuit 800 may also include a digital clamp signal generator 109.

As an example, the digital clamp signal generator 109 can be used to generate a digital clamp signal (for example, D1) based on the output signal (for example, Vc) of the DAC 103, and output the digital clamp signal D1 to The digital integrator 102, and the digital output signal 105 is controlled in the digital integrator 102, and then the output signal Vc of the DAC 103 is clamped.

In some embodiments, the digital clamp element signal generator 109 is used to generate the digital clamp element signal D1 based on the output signal of the DAC 103, and includes: a digital clamp element signal generator 109 is used to generate the digital clamp signal D1 when the output signal of the DAC 103 is greater than the upper threshold level and/or when the output signal of the DAC 103 is less than the lower threshold level.

As an example, the digital clamp signal (for example, D1) is generated by monitoring and sensing the output signal (for example, Vc) of the signal DAC 103.

In the first embodiment, if the signal Vc is greater than the upper threshold voltage, the digital clamp signal generator 109 generates a first digital clamp signal to clamp the signal Vc based on the first digital clamp signal (Prevent further increase); In the second embodiment, if the signal Vc is less than the lower threshold voltage, the digital clamp signal generator 109 generates a second digital clamp signal to perform alignment based on the second digital clamp signal The signal Vc is clamped (to prevent further reduction); in the third embodiment, if the signal Vc is greater than the upper threshold voltage or the signal Vc is less than the lower threshold voltage, the digital clamp signal generator 109 generates a third digital clamp The meta signal is used to clamp the signal Vc (to prevent further increase or decrease) based on the third digital clamp element signal.

This creative embodiment provides an error signal processing circuit, pulse width modulation and pulse frequency modulation system. Through high-precision signal amplification and conversion processing, circuit control and lower capacitance values are used to achieve error signal amplification and loops. Compensation, and is suitable for the loop compensation large capacitance capacitance of the traditional lower bandwidth signal system inside the chip instead of outside the chip, thereby reducing the cost and volume of the peripheral circuit of the system.

It should be clear that the present creation is not limited to the specific configuration and processing described above and shown in the figure. For brevity, a detailed description of the known method is omitted here. In the above embodiments, plural specific steps are described and shown as examples. However, the process of the authoring method is not limited to the specific steps described and shown. After understanding the spirit of the authoring, those skilled in the art can make various changes, modifications and additions, or change the order between the steps.

The functional blocks shown in the above-mentioned structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in program, a function card, and so on. When implemented in software, the elements of this creation are programs or code fragments used to perform the required tasks. The program or program code fragments can be stored in a machine-readable medium, or transmitted over a transmission medium or communication link through a data signal carried in a carrier wave. "Machine-readable medium" may include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (Read-Only Memory, ROM), flash memory, erasable ROM (Erasable Read Only Memory, EROM), floppy disks, Read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical disc, hard disk, optical fiber media, radio frequency (RF) link, etc. The code fragments can be downloaded via computer networks such as the Internet, intranet, etc.

It should also be noted that the exemplary embodiments mentioned in this creation describe some methods or systems based on a series of steps or devices. However, the present creation is not limited to the order of the above steps, that is to say, the steps may be executed in the order mentioned in the embodiment, or may be different from the order in the embodiment, or plural steps may be executed simultaneously.

The above are only specific implementations of this creation. Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working process of the above-described systems, modules and units can be implemented with reference to the foregoing methods. The corresponding process in the example will not be repeated here. It should be understood that the protection scope of this creation is not limited to this. Anyone familiar with the technical field can easily think of various equivalent modifications or substitutions within the technical scope disclosed in this creation, and these modifications or substitutions should be covered Within the scope of protection of this creation.

100: Error signal processing circuit

101: Pulse signal generator

102: Digital Integrator

103: Digital Analog Converter (DAC)

104: Digital pulse signal

105: digital signal

Vref: reference voltage

F+, F-, FB, Vc: signal

Claims (9)

An error signal processing circuit applied to a pulse width modulation or pulse frequency modulation system, the circuit comprising: A pulse signal generator, which is used to receive the input reference voltage and the feedback signal of the system to generate a digital pulse signal; A digital integrator, the input terminal of the digital integrator is connected to the output terminal of the pulse signal generator; and A digital analog converter, the input end of the digital analog converter is connected to the output end of the digital integrator, and the digital analog converter is used to output an analog signal. The circuit according to claim 1, wherein the pulse signal generator includes: An error voltage amplifier, the input terminal of the error voltage amplifier is used to receive the input reference voltage and the feedback signal of the system; and A voltage-to-frequency converter, the input terminal of the voltage-to-frequency converter is connected to the output terminal of the error voltage amplifier, and the output terminal of the voltage-to-frequency converter is connected to the input terminal of the digital integrator. The circuit according to claim 1, wherein the pulse signal generator includes: An error transconductance amplifier, the input end of the error transconductance amplifier is used to receive the input reference voltage and the feedback signal of the system; and In a current-to-frequency converter, the input terminal of the current-to-frequency converter is connected to the output terminal of the error transconductance amplifier, and the output terminal of the current-to-frequency converter is connected to the input terminal of the digital integrator. The circuit according to claim 1, which further includes: A clamp cell voltage generator, which is used to generate a clamp cell voltage based on the output signal of the digital-to-analog converter, and output it to the digital-to-analog converter for comparing the digital-to-analog The output signal of the converter is clamped. The circuit according to claim 4, wherein the clamp cell voltage generator is configured to generate a clamp cell voltage based on the output signal of the digital-to-analog converter, including: The clamp cell voltage generator is used to generate the clamp cell voltage when the output signal of the digital-to-analog converter is greater than an upper threshold voltage and/or when the output signal of the digital-to-analog converter is less than a lower threshold voltage. The circuit according to claim 1, which further includes: Digital clamp element signal generator, the digital clamp element signal generator is used to generate a digital clamp element signal based on the output signal of the digital analog converter, and output to the digital integrator, for the The output signal of the digital analog converter is clamped. The circuit according to claim 6, wherein the digital clamp element signal generator is configured to generate a digital clamp element signal based on the output signal of the digital-to-analog converter, including: The digital clamp element signal generator is used to generate the digital clamp element when the output signal of the digital analog converter is greater than an upper threshold level and/or when the output signal of the digital analog converter is less than a lower threshold level Signal. A pulse width modulation system, including: The error signal processing circuit according to any one of claims 1 to 7; A pulse width modulation control unit, the input end of the pulse width modulation control unit is connected to the output end of the error signal processing circuit; and A driver, the input terminal of the driver is connected to the output terminal of the pulse width modulation control unit to output a driving signal. A pulse frequency modulation system, including: The error signal processing circuit according to any one of claims 1 to 7; A pulse frequency modulation control unit, the input end of the pulse frequency modulation control unit is connected to the output end of the error signal processing circuit; and A driver, the input terminal of the driver is connected to the output terminal of the pulse frequency modulation control unit to output a driving signal.

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