TWM600935U - Antimagnetic structure of semiconductor package - Google Patents
Antimagnetic structure of semiconductor package Download PDFInfo
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本新型提供一種半導體封裝結構,特別的是一種半導體封裝防磁結構。 The model provides a semiconductor packaging structure, in particular a semiconductor packaging antimagnetic structure.
小尺寸之積體電路封裝單元一般是以成批方式建構於單一個矩陣式基底上;此矩陣式基底是預先定義出多個封裝區域,其中每一個封裝區域即用以建構一個封裝單元。於完成封裝膠體製程之後,接著即可進行一分割程序(singulation process),用以將矩陣式基底上所建構之封裝單元總合結構體分割成個別之封裝單元。以此種方式製造之封裝單元例如包括薄型球柵陣列式(Thin & Fine Ball Grid Array,TFBGA)封裝單元、四邊形平面無導腳式(Quad Flat No-lead,QFN)封裝單元等等。 Small-size integrated circuit packaging units are generally constructed in batches on a single matrix substrate; the matrix substrate is pre-defined with multiple packaging areas, and each packaging area is used to construct a packaging unit. After the packaging process is completed, a singulation process can be performed to divide the integrated structure of packaging units constructed on the matrix substrate into individual packaging units. Packaging units manufactured in this way include, for example, Thin & Fine Ball Grid Array (TFBGA) packaging units, Quad Flat No-lead (QFN) packaging units, and so on.
電磁干擾是一種電磁現象,一些電器、電子設備工作時所產生的電磁波,容易對周圍的其他電氣、電子設備形成電磁干擾,引發故障或者影響信號的傳輸。而且,過度的電磁干擾會形成電磁污染,危害周遭人們的身體健康。隨著設備與結構的演進,要達到能夠正常工作而不會相互發生電磁干擾造成性能改變和設備損壞的這種相互相容的狀態越來越難。為了使整體達到電磁相容,必須以整體的電磁環境為依據,要求每個用電設備不產生超過一定限度的電磁發射,同時又要求用電設備本身要具備一定的抗干擾能力。 只有對每一個用電設備都作出這兩個方面的約束和改進,才能保證整體達到完全相容。 Electromagnetic interference is an electromagnetic phenomenon. Electromagnetic waves generated by some electrical appliances and electronic equipment when they are working can easily cause electromagnetic interference to other electrical and electronic equipment around them, causing malfunctions or affecting signal transmission. Moreover, excessive electromagnetic interference will cause electromagnetic pollution and endanger the health of people around. With the evolution of equipment and structure, it is more and more difficult to achieve a mutually compatible state that can work normally without mutual electromagnetic interference causing performance changes and equipment damage. In order to achieve electromagnetic compatibility as a whole, it must be based on the overall electromagnetic environment, requiring that each electrical equipment does not produce electromagnetic emissions exceeding a certain limit, and at the same time, the electrical equipment itself must have a certain anti-interference ability. Only by making constraints and improvements in these two aspects for each electrical equipment can it be ensured that the whole is fully compatible.
因此,如何提出一種半導體封裝結構,能夠有效改善習知技術的缺點已成為一個重要的課題。 Therefore, how to propose a semiconductor packaging structure that can effectively improve the shortcomings of the conventional technology has become an important topic.
為了解決上述需求,本創作的目的是提供了一種半導體封裝防磁結構,藉由在晶片上增加一顆表面具有金屬薄膜的半導體裸晶與下方的基板電路電性連接之後,可以防止電磁波以及增加整體封裝結構的電性。 In order to solve the above needs, the purpose of this creation is to provide a semiconductor package antimagnetic structure, by adding a semiconductor die with a metal thin film on the surface of the chip to the substrate circuit below, it can prevent electromagnetic waves and increase the overall The electrical properties of the package structure.
根據上述目的,本創作主要提出一種半導體封裝防磁結構,包含:基板、第一晶片、第一導線、膠層、第二晶片、金屬薄膜與第二導線,其中基板還具有上表面和下表面以及多個貫穿上表面及下表面的電連接結構,同時在上表面及下表面之間具有一個窗口。另外,第一晶片設有主動面及背面,第一晶片的主動面朝下設置在基板的上表面上,而且第一晶片的部份主動面還曝露於窗口中,曝露於窗口的部份主動面與基板的電連接結構電性連接,同時第一導線通過曝露於窗口的部份將第一晶片的主動面與基板的下表面電性連接。接著,膠層設置於第一晶片的背面上,然後第二晶片設置在膠層上,藉由膠層使第二晶片固定在第一晶片的背面上。金屬薄膜設置於第二晶片上,以及第二導線同時電性連接金屬薄膜的上表面及基板的上表面上。 According to the above objective, this creation mainly proposes a semiconductor package antimagnetic structure, including: a substrate, a first chip, a first wire, an adhesive layer, a second chip, a metal film, and a second wire. The substrate also has an upper surface and a lower surface, and A plurality of electrical connection structures penetrate the upper surface and the lower surface, and at the same time, there is a window between the upper surface and the lower surface. In addition, the first chip is provided with an active surface and a back surface. The active surface of the first chip is arranged on the upper surface of the substrate facing down, and part of the active surface of the first chip is also exposed in the window. The surface is electrically connected to the electrical connection structure of the substrate, and the first wire electrically connects the active surface of the first chip with the lower surface of the substrate through the portion exposed to the window. Then, the glue layer is arranged on the back surface of the first chip, and then the second chip is arranged on the glue layer, and the second chip is fixed on the back surface of the first chip by the glue layer. The metal film is disposed on the second chip, and the second wire is electrically connected to the upper surface of the metal film and the upper surface of the substrate at the same time.
根據上述目的,本創作另外又提出一種半導體封裝防磁結構,包含:基板、第一晶片、第一導線、膠層、第二晶片、金屬薄膜、第二導線與封裝結構,其中基板還具有上表面和下表面以及多個貫穿上表面及下表面的電連 接結構。另外,第一晶片設有主動面及背面,第一晶片的背面朝下設置在基板的上表面上,而且第一晶片的主動面上還具有多個焊墊,同時第一導線分別電性連接第一晶片的主動面上的多個焊墊及基板的上表面。接著,膠層設置於第一晶片的主動面上且包覆第一導線,然後第二晶片設置在膠層上,接下來金屬薄膜設置於第二晶片上,再來是第二導線同時電性連接金屬薄膜的上表面及基板的上表面上。而封裝結構設置在基板的上表面並且包覆了基板的部份上表面、金屬薄膜與第二導線。 According to the above objective, this creation also proposes a semiconductor package antimagnetic structure, including: a substrate, a first chip, a first wire, an adhesive layer, a second chip, a metal film, a second wire, and a packaging structure, wherein the substrate also has an upper surface And the lower surface and multiple electrical connections through the upper and lower surfaces 接结构。 Connected structure. In addition, the first chip is provided with an active surface and a back surface, the back side of the first chip is arranged on the upper surface of the substrate, and the active surface of the first chip also has a plurality of bonding pads, and the first wires are electrically connected respectively A plurality of bonding pads on the active surface of the first chip and the upper surface of the substrate. Next, the adhesive layer is disposed on the active surface of the first chip and covers the first wire, and then the second chip is disposed on the adhesive layer, and then the metal film is disposed on the second chip, and then the second wire is simultaneously electrically conductive Connect the upper surface of the metal film and the upper surface of the substrate. The packaging structure is arranged on the upper surface of the substrate and covers part of the upper surface of the substrate, the metal film and the second wire.
1、2:半導體封裝防磁結構 1, 2: Antimagnetic structure of semiconductor package
10、12:基板 10, 12: substrate
20、22:第一晶片 20, 22: the first chip
30、32:第一導線 30, 32: first wire
40、42:膠層 40, 42: Glue layer
50、52:第二晶片 50, 52: second chip
60、62:金屬薄膜 60, 62: metal film
70、72:第二導線 70, 72: second wire
80、82:電連接結構 80, 82: electrical connection structure
90:封裝結構 90: Package structure
101、121:上表面 101, 121: upper surface
102、122:下表面 102, 122: lower surface
103:窗口 103: Window
201、221:主動面 201, 221: Active side
202、222:背面 202, 222: back
圖1為根據本創作所揭露的技術,表示半導體封裝防磁結構的第一實施例示意圖。 FIG. 1 is a schematic diagram showing a first embodiment of the antimagnetic structure of a semiconductor package according to the technology disclosed in this creation.
圖2為根據本創作所揭露的技術,表示半導體封裝防磁結構的第二實施例示意圖。 2 is a schematic diagram showing a second embodiment of the antimagnetic structure of a semiconductor package according to the technology disclosed in this creation.
圖3為根據本創作所揭露的技術,表示半導體封裝防磁結構的第三實施例示意圖。 FIG. 3 is a schematic diagram showing a third embodiment of the antimagnetic structure of a semiconductor package according to the technology disclosed in this creation.
圖4為根據本創作所揭露的技術,表示半導體封裝防磁結構的第四實施例示意圖。 FIG. 4 is a schematic diagram showing a fourth embodiment of the antimagnetic structure of a semiconductor package according to the technology disclosed in this creation.
圖5為根據本創作所揭露的技術,表示半導體封裝防磁結構的第五實施例示意圖。 FIG. 5 is a schematic diagram showing a fifth embodiment of the antimagnetic structure of a semiconductor package according to the technology disclosed in this creation.
本創作之優點及特徵以及達到其方法將參照例示性實施例及附圖進行更詳細的描述而更容易理解。然而,本創作可以不同形式來實現且不應被理解僅限於此處所陳述的實施例。相反地,對所屬技術領域具有通常知識者而言,所提供的此些實施例將使本揭露更加透徹與全面且完整地傳達本創作的範疇。 The advantages and features of the present invention and the method for achieving the same will be described in more detail with reference to the exemplary embodiments and the accompanying drawings to make it easier to understand. However, this creation can be implemented in different forms and should not be understood to be limited to the embodiments set forth herein. On the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make this disclosure more thorough, comprehensive and complete to convey the scope of the creation.
請參考圖1,圖1為半導體封裝防磁結構的第一實施例示意圖。如圖1所示,本創作之半導體封裝防磁結構1包含基板10、第一晶片20、第一導線30、膠層40、第二晶片50、金屬薄膜60與第二導線70,其中基板10還具有上表面101和下表面102以及多個貫穿上表面101及下表面102的電連接結構80,同時在上表面101及下表面102之間具有一個窗口103。要說明的是,在基板10內的多個電連接結構80是利用內連線製程(interconnection process)來形成,其形成方式和電連接結構的功能與現有技術相同,也並非本創作的主要技術特徵,故不多加陳述。另外,第一晶片20具有主動面201及背面202,且於主動面201上設有多個焊墊(未在圖中表示)第一晶片20的主動面201朝下以覆晶(flip-chip)方式設置在基板10的上表面101上,而且第一晶片20的部份主動面201還曝露於窗口103中,曝露於窗口103的部份主動面201與基板10的電連接結構80彼此電性連接,同時第一導線30通過曝露於窗口103的部份將第一晶片20的主動面201與基板10的下表面102電性連接,具體來說是將第一導線30的一端連接於第一晶片20的主動面201上的焊墊(未在圖中表示),而第一導線30的另一端則是經過窗口103連接於基板10的下表面102。接著,膠層40設置於第一晶片20的背面202上,然後第二晶片50設置在膠層40上,藉由膠層40使第二晶片50固定在第一晶片20的背面202上。金屬薄膜60設置於第二晶片50上,以及第二導線70同時電性連接金屬薄膜60的上表面及基板10的上表面101上。
Please refer to FIG. 1, which is a schematic diagram of a first embodiment of an antimagnetic structure of a semiconductor package. As shown in FIG. 1, the semiconductor package
接下來請繼續參考圖1,在另一實施例中,本創作之半導體封裝防磁結構1包含基板10、第一晶片20、第一導線30、膠層40、第二晶片50、金屬薄膜60、第二導線70與封裝結構90,其中基板10還具有上表面101和下表面102以及多個貫穿上表面101及下表面102的電連接結構80,同時在上表面101及下表面102之間具有一個窗口103。另外,第一晶片20是一種功能晶片,其具有主動面201及背面202,第一晶片20的主動面201以覆晶方式朝下設置在基板10的上表面101上,而且第一晶片20的部份主動面201還曝露於窗口103中,曝露於窗口103的部份主動面201與基板10的電連接結構80電性連接,同時第一導線30通過曝露於窗口103的部份將第一晶片20的主動面201與基板10的下表面102電性連接,另外基板10的下表面102上還具有多個電性連接結構,其中基板10的下表面102上的電性連接結構為錫球(solder ball)或是晶圓凸塊(solder bump)。接著,膠層40設置於第一晶片20的背面202上,然後第二晶片50設置在膠層40上,藉由膠層40使第二晶片50固定在第一晶片20的背面202上,其中第二晶片50的尺寸可以大於、小於或是等於第一晶片20的尺寸,以及第二晶片50可以是半導體裸片及矽晶片。金屬薄膜60設置於第二晶片50上,以及第二導線70分別電性連接於金屬薄膜60的上表面及基板10的上表面101上。而封裝結構90包覆了基板10的部份上表面101、第二導線70、金屬薄膜60、在窗口103內的第一導線30及暴露於窗口103的基板10的下表面102,在本創作中利用第二晶片50及其上方的金屬薄膜60增加整體半導體封裝防磁結構1的電性並且可以防止電磁波的干擾以提高半導體封裝防磁結構1的工作效率。
Next, please continue to refer to FIG. 1. In another embodiment, the semiconductor package
再來請參考圖2,圖2為本創作之半導體封裝防磁結構的第二實施例示意圖。如圖2所示,本創作之半導體封裝防磁結構2包含基板12、第一晶片22、第一導線32、膠層42、第二晶片52、金屬薄膜62、第二導線72與封裝
結構90,其中基板12還具有上表面121和下表面122以及多個貫穿上表面121及下表面122的電連接結構82。另外,第一晶片22具有主動面221及背面222,第一晶片22以主動面221朝上以背面222朝下的方式設置在基板12的上表面121上,而且第一晶片22的主動面221上還具有多個焊墊(未在圖中表示),同時第一導線32分別電性連接第一晶片22的主動面221上的多個焊墊(未在圖中表示)及基板12的上表面121。接著,膠層42設置於第一晶片22的主動面221上且包覆第一導線32,然後第二晶片52設置在膠層42上,接下來金屬薄膜62設置於第二晶片52上,再來是第二導線72同時電性連接金屬薄膜62的上表面及基板12的上表面121上。而封裝結構90設置在基板12的上表面121並且包覆了基板12的部份上表面121、金屬薄膜62與第二導線72。
Please refer to FIG. 2 again. FIG. 2 is a schematic diagram of the second embodiment of the antimagnetic structure of the semiconductor package created. As shown in FIG. 2, the semiconductor package
接下來請繼續參考圖2,在另一實施例中,本創作之半導體封裝防磁結構2包含基板12、第一晶片22、第一導線32、膠層42、第二晶片52、金屬薄膜62、第二導線72與封裝結構90,其中基板12還具有上表面121和下表面122以及多個貫穿上表面121及下表面122的電連接結構82。另外,第一晶片22是一種功能晶片,其具有主動面221及背面222,第一晶片22的背面222朝下設置在基板12的上表面121上,而且第一晶片22的主動面221上還具有多個焊墊(未在圖中表示),同時第一導線32分別電性連接第一晶片22的主動面221上的多個焊墊(未在圖中表示)及基板12的上表面121,另外基板12的下表面122上還具有多個電性連接結構(未在圖中表示),其中基板12的下表面122上的電性連接結構為錫球(solder ball)或是晶圓凸塊(solder bump)。接著,膠層42設置於第一晶片22的主動面221上且包覆第一導線32,然後第二晶片52設置在膠層42上,接下來金屬薄膜62設置於第二晶片52上,其中第二晶片52的尺寸可以大於、小於或是等於第一晶片22的尺寸,以及第二晶片52可以是半導體裸片及矽晶片。然後,第二導線72同時電性連接金屬薄膜62
的上表面及基板12的上表面121上。而封裝結構90設置在基板12的上表面121並且包覆了基板12的部份上表面121、金屬薄膜62與第二導線72,增加整體半導體封裝防磁結構2的電性。
Next, please continue to refer to FIG. 2. In another embodiment, the semiconductor package
再來請同時參考圖2與圖3,圖3為本創作之半導體封裝防磁結構的第三實施例示意圖。如圖3所示,本創作之半導體封裝防磁結構2包含基板12、第一晶片22、第一導線32、膠層42、第二晶片52、金屬薄膜62、第二導線72與封裝結構90,其中圖3的第三實施例與圖2的第二實施例差別在於圖3的第三實施例中,膠層42設置於第一晶片22的主動面221上,然後第二晶片52設置在膠層42上,接下來金屬薄膜62設置於第二晶片52上,其中第二晶片52的尺寸小於第一晶片22的尺寸,然後第一導線32的一端電性連接第一晶片22的主動面221上的多個焊墊(未在圖中表示)及第一導線32的另一端電性連接於基板12的上表面121,第二導線72的一端電性連接於金屬薄膜62的上表面及另一端電性連接於基板12的上表面121上。
Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a schematic diagram of the third embodiment of the antimagnetic structure of the semiconductor package created. As shown in FIG. 3, the semiconductor package
再來請同時參考圖2與圖4,圖4為本創作之半導體封裝防磁結構的第四實施例示意圖。如圖4所示,本創作之半導體封裝防磁結構2包含基板12、第一晶片22、第一導線32、膠層42、第二晶片52、金屬薄膜62、第二導線72與封裝結構90,其中圖4的第四實施例與圖2的第二實施例差別在於圖4的第四實施例中,膠層42設置於第一晶片22的主動面221上,然後第二晶片52設置在膠層42上,接下來金屬薄膜62設置於第二晶片52上,其中第二晶片52的尺寸小於第一晶片22的尺寸,然後第一導線32的一端電性連接於金屬薄膜62及另一端電性連接於第一晶片22的主動面221沒有被膠層42覆蓋的多個焊墊(未在圖中表示)上及第二導線72的一端電性連接第一晶片22的多個焊墊上及另一端電性連接於基板12的上表面121。
Please refer to FIG. 2 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of a fourth embodiment of the antimagnetic structure of the semiconductor package created. As shown in FIG. 4, the semiconductor package
再來請同時參考圖2與圖5,圖5為本創作之半導體封裝防磁結構的第五實施例示意圖。如圖5所示,本創作之半導體封裝防磁結構2包含基板12、第一晶片22、第一導線32、膠層42、第二晶片52、金屬薄膜62、第二導線72與封裝結構90,其中圖5的第五實施例與圖2的第二實施例差別在於圖5的第五實施例中,膠層42設置於第一晶片22的主動面221上,然後第二晶片52設置在膠層42上,接下來金屬薄膜62設置於第二晶片52上,其中第二晶片52的尺寸小於第一晶片22的尺寸,然後在第一晶片22及第二晶片52的一側(如圖5的右側),第一導線32的一端電性連接於第一晶片22的主動面221且沒有被膠層42覆蓋的多個焊墊(未在圖中表示)上及另一端電性連接於基板12的上表面121。而在圖5的左側,第二導線72分別電性連接於金屬薄膜62的上表面及基板12的上表面121上,而第一導線32則是分別電性連接第一晶片22的主動面221上未被膠層42所覆蓋的多個焊墊及基板12的上表面121上。在圖5的結構中,第一導線32及第二導線72與基板12、第一晶片22及金屬薄膜62的打線方式為前述圖3及圖4的整合結構。
Please refer to FIG. 2 and FIG. 5 at the same time. FIG. 5 is a schematic diagram of a fifth embodiment of the antimagnetic structure of the semiconductor package created. As shown in FIG. 5, the semiconductor package
上述所述者僅為本創作之較佳實施例,舉凡依本創作精神所作之等效修飾或變化,依照相同概念所提出之半導體封裝防磁結構的系統架構,皆應仍屬本創作涵蓋之範圍內。 The foregoing descriptions are only preferred embodiments of this creation. Any equivalent modifications or changes made in accordance with the spirit of this creation, and the system architecture of the semiconductor package antimagnetic structure proposed in accordance with the same concept should still fall within the scope of this creation. Inside.
1:半導體封裝防磁結構 1: Antimagnetic structure of semiconductor package
10:基板 10: substrate
20:第一晶片 20: The first chip
30:第一導線 30: First wire
40:膠層 40: Glue layer
50:第二晶片 50: second chip
60:金屬薄膜 60: metal film
70:第二導線 70: second wire
80:電連接結構 80: electrical connection structure
90:封裝結構 90: Package structure
101:上表面 101: upper surface
102:下表面 102: lower surface
103:窗口 103: Window
201:主動面 201: active side
202:背面 202: back
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