TWM586491U - Power-on reset circuit for carrier tape chips - Google Patents

Abstract

The original power-on reset circuit for the carrier tape chip includes: a voltage divider module, a primary voltage adjustment module, an energy storage module, and a secondary module; the voltage divider module is used to divide the voltage of the power supply. The node voltage is transmitted to the primary voltage regulation module; one end of the energy storage module is connected to the power supply, and the other end is connected to the second node voltage between the primary voltage regulation module and the secondary module; The power supply rises and rises to trigger the forward conduction of the primary voltage regulation module. After the primary voltage regulation module is forwarded, the energy storage module starts to store energy and gradually reduces the voltage at the second node to trigger the secondary mode. Group anti-conduction output output reset voltage.

Description

Power-on reset circuit for carrier chip

This creation relates to the technical field of circuit design, in particular to the technical field of power-on reset circuit for carrier chip.

In the integrated circuit design, in order to avoid the malfunction or leakage caused by an unknown state in the circuit node when power on, it is necessary to use a power on reset signal to maintain the internal nodes. At a preset voltage, the circuit can be brought into a preset state. Therefore, the power on reset circuit design is very important for the integrated circuit design.

FIG. 1 is a conventional power-on reset circuit. The conventional power-on reset circuit uses RC charging and discharging to generate a power-on reset signal through a two-stage inverter. Figure 2 shows the timing diagram of the existing power-on reset circuit. At power-on, when V1 is charged to the high input level (Vih) of the first-stage flip-flop (composed of MP1 and MN1), V2 will be It will transition to ground. At this time, it can generate a power on reset signal after passing through a first level flip-flop (composed of MP2 and MN2). However, the variation of the resistance value in the semiconductor process is quite large, which easily causes the initial voltage and reset time generated by the power-on reset signal to be different from the simulation. The high input level (Vih) of a general flip-flop depends on the threshold voltage (Vth) of the transistor. Because the adjustable range of the threshold voltage of the transistor is too small, the starting voltage of the reset signal cannot be adjusted. Interval.

In order to overcome the problem that the threshold voltage adjustable range of the transistor is too small in the prior art, and the initial voltage of the reset signal cannot be adjusted, the present invention provides a power-on reset circuit for a carrier chip.

In order to solve the above technical problems, this creation provides a power-on reset circuit for a carrier chip, which includes: a voltage divider module, a primary voltage adjustment module, an energy storage module, and a secondary module; wherein the voltage divider module is used for Dividing the power supply and transmitting the voltage of the first node to the first-level voltage adjustment module; one end of the energy storage module is connected to the power supply, and the other end is connected to the first-level voltage adjustment module and the second-level module. The voltage of the second node between them is connected; when the power is turned on, the voltage of the first node rises with the rise of the power supply to trigger the conduction of the primary voltage regulation module; after the primary voltage regulation module is turned on, the energy storage module starts to store energy. The second node voltage is gradually reduced to trigger the secondary module to turn on and output the power-on reset voltage.

Further, the voltage-dividing module includes: a resistor R1 and a resistor R2; a power supply source is grounded through the resistor R1 and the resistor R2 in order, and the voltage between the resistor R1 and the resistor R2 is used as the first node voltage.

Further, the above-mentioned first-level voltage regulating module includes: a third NMOS transistor MN12, a fourth NMOS transistor MN11, and a fifth NMOS transistor MN13; a gate of the third NMOS transistor MN12 is connected to the first node voltage, and a drain thereof is connected to Two-level module; the gate of the fourth NMOS transistor MN11 is connected to the first node voltage and its source is grounded; the source of the third NMOS transistor MN12 is connected to the drain of the fourth NMOS transistor MN11 and connected The source of the fifth NMOS transistor MN13; and the drain of the fifth NMOS transistor MN13 is connected to the power supply, and its gate is connected to the secondary module.

Further, the above-mentioned secondary module includes: a second PMOS tube MP2 and a second NMOS tube MN2; the gate of the second PMOS tube MP2 is connected to the output of the primary voltage regulating module, and its source is connected to the power supply; The gates of the two NMOS transistors MN2 are connected to the output of the first-level voltage regulating module, and their sources are grounded; and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the second PMOS transistor MP2 is described above. The voltage between the drain of the NMOS transistor and the drain of the second NMOS transistor MN2 is used as the reset reset voltage or the reset reset voltage.

Further, the energy storage circuit includes: an electrolytic capacitor; one end of the electrolytic capacitor is connected to a power supply, and the other end thereof is connected to a second node voltage.

Compared with the prior art, the beneficial effects of this creation are:

At the start of this creation, the voltage of the first node rises with the rise of the power supply to trigger the forward conduction of the primary voltage regulation module. After the primary voltage regulation module is forwarded, the energy storage module starts to store energy, so that The voltage of the second node is gradually reduced to trigger the reverse conduction output of the secondary module to output the reset voltage; this creation sets the energy storage module as an electrolytic capacitor, and the reset time can be set by adjusting the size of the electrolytic capacitor value; this creation Set resistor R1 and resistor R2 to divide the power supply, and then adjust the input voltage value by changing the resistance of resistor R1 and resistor R2. In this creation, the first-stage voltage adjustment module is set to the first PMOS tube MP1, the first The three NMOS transistors MN12, the fourth NMOS transistor MN11, and the fifth NMOS transistor MN13 can increase the reset voltage without being affected by the characteristics of the transistor in the semiconductor process.

In order to facilitate a deeper, clearer and more detailed understanding and understanding of the structure, use and characteristics of this creation, here are some preferred embodiments, which are explained in detail with the drawings:

As shown in Figure 3-4, this creation schematically illustrates a power-on reset circuit for a carrier chip, which includes: a voltage divider module, a primary voltage regulation module, an energy storage module, and a secondary module; The voltage dividing module is used to divide the power supply and transmit the first node voltage V1 to the first-level voltage regulating module; one end of the energy storage module is connected to the power supply and the other end is connected to the first-level voltage regulating module. The second node voltage V2 between the group and the second-level modules is connected. When the power is turned on, the first node voltage V1 rises to trigger the first-level voltage regulation module to turn on; after the first-level voltage regulation module is turned on The energy storage module starts to store energy, so that the second node voltage V2 gradually decreases, so as to trigger the second-level module to turn on and output the power-on reset voltage.

The voltage dividing module includes: a resistor R1 and a resistor R2; a power supply source is grounded through the resistor R1 and the resistor R2 in order, and the voltage between the resistor R1 and the resistor R2 is used as the first node voltage V1.

The first-level voltage adjustment module includes: a first PMOS tube MP1, a third NMOS tube MN12, a fourth NMOS tube MN11, and a fifth NMOS tube MN13; the gate of the first PMOS tube MP1 is connected to the first node voltage V1, Its source is connected to the power supply; the gate of the third NMOS tube MN12 is connected to the first node voltage V1, and its drain is connected to the secondary module; the gate of the fourth NMOS tube MN11 is connected to the first The node voltage V1 has its source grounded; the source of the third NMOS transistor MN12 is connected to the drain of the fourth NMOS transistor MN11 and connected to the source of the fifth NMOS transistor MN13; and the drain of the fifth NMOS transistor MN13 Connected to the power supply, its gate is connected to the secondary module; the drain of the first PMOS transistor MP1 and the drain of the third NMOS transistor MN12 are both connected to the secondary module.

The secondary module includes: the second PMOS tube MP2 and the second NMOS tube MN2; the gate of the second PMOS tube MP2 is connected to the output of the primary voltage regulating module, and the source is connected to the power supply; the second NMOS is The gate of the transistor MN2 is connected to the output of the first-level voltage regulating module, and its source is grounded; and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the drain of the second PMOS transistor MP2 is connected. The voltage between the electrode and the drain of the second NMOS transistor MN2 is used as the above-mentioned power-on reset voltage or the above-mentioned power-off reset voltage.

The energy storage circuit includes: an electrolytic capacitor; one end of the electrolytic capacitor is connected to a power supply, and the other end thereof is connected to a second node voltage V2.

The resistors R1 and R2 are not limited to designing with a passive resistor, but can also be designed with a transistor equivalent resistance.

As shown in FIG. 3 and FIG. 4, a divided voltage of the resistor R1 and the resistor R2 is used to generate a required first node voltage V1, where V1 = VDD * (R2 / (R1 + R2)). When starting up, when the voltage of the power supply VDD rises, the voltage of the first node V1 rises with the rise of the power supply VDD. Before the reset signal does not transition, the voltage of the second node voltage V2 is VDD. At this time, the fifth NMOS The tube MN13 is turned on, and the node voltage VB is VDD-Vthmn13. When the power supply VDD continues to rise and the voltage of the first node voltage V1 is greater than Vthmn12 + VB, the third NMOS transistor MN12 can be turned on and turned on, and the second node voltage V2 becomes ground. After passing through the second PMOS tube MP2 in the two-level module (composed of the second PMOS tube MP2 and the second NMOS tube MN2), a power-on reset signal is generated at this time. Therefore, through this creation, we can change the high input level Vih of the reset circuit to Vthmn12 + VB. With this method, the reset voltage can be increased again without being affected by the transistor characteristics Vth in the semiconductor process. When the high input level Vih is set higher, the reset time will become higher. At this time, by reducing the capacitance value of the electrolytic capacitor at the second node voltage V2 point, the area of the integrated circuit can be effectively reduced. To achieve the effect of reducing costs.

In this creation, the voltage of the first node V1 rises with the rise of the power supply to trigger the forward conduction of the primary voltage regulation module. After the primary voltage regulation module is forwarded, the energy storage module starts to store energy. The second node voltage V2 is gradually decreased to trigger the reverse conduction output of the secondary module to output the power-on reset voltage; this creation sets the energy storage module as an electrolytic capacitor, and the reset time can be set by adjusting the size of the electrolytic capacitor value; In this creation, a resistor R1 and a resistor R2 are set to divide the power supply, and then the input voltage value can be adjusted by changing the resistance values of the resistors R1 and R2.

The above-mentioned embodiments are only for the convenience of explaining the creation and are not limited. Without departing from the spirit of the creation, various simple deformations and modifications made by those skilled in this industry in accordance with the scope of the patent application for creation and the new description should still be applied. Included in the scope of the following patent applications.

MP1‧‧‧The first PMOS tube
MP2‧‧‧Second PMOS tube
MN2‧‧‧Second NMOS tube
MN11‧‧‧The fourth NMOS tube
MN12‧‧‧The third NMOS tube
MN13‧‧‧The fifth NMOS tube
R1, R2‧‧‧ resistance
V1‧‧‧ first node voltage
V2‧‧‧Second node voltage

1 is a schematic diagram of a conventional power-on reset circuit;
FIG. 2 is a timing diagram of a conventional power-on reset circuit; FIG.
FIG. 3 is a power-on reset circuit diagram of the present invention; and FIG. 4 is a timing chart of the power-on reset circuit of the present invention.

Claims (5)

A power-on reset circuit for a carrier chip includes:
Voltage divider module, primary voltage regulator module, energy storage module and secondary module; the above voltage divider module is used to divide the voltage of the power supply and transmit the first node voltage to the primary voltage regulator module ;
One end of the energy storage module is connected to a power supply, and the other end is connected to a second node voltage between the primary voltage regulation module and the secondary module;
When the power is turned on, the voltage of the first node rises with the rise of the power supply to trigger the conduction of the first-level voltage regulating module;
After the primary voltage regulating module is turned on, the energy storage module starts to store energy, so that the voltage of the second node is gradually reduced, so as to trigger the secondary module to turn on and output the power-on reset voltage. The power-on reset circuit for a carrier chip according to item 1 of the claim, wherein the voltage dividing module includes: a resistor R1 and a resistor R2;
The power supply is grounded via the resistor R1 and the resistor R2 in order, and the voltage between the resistor R1 and the resistor R2 is used as the first node voltage. According to the second item of the request item, the power-on reset circuit for a carrier chip, wherein the first-level voltage adjustment module includes a third NMOS tube MN12, a fourth NMOS tube MN11, and a fifth NMOS tube MN13;
The gate of the third NMOS transistor MN12 is connected to the first node voltage, and its drain is connected to the secondary module;
The gate of the fourth NMOS transistor MN11 is connected to the first node voltage, and the source is grounded;
The source of the third NMOS transistor MN12 is connected to the drain of the fourth NMOS transistor MN11 and then connected to the source of the fifth NMOS transistor MN13; and the drain of the fifth NMOS transistor MN13 is connected to the power supply and its gate is connected Into the secondary module. The power-on reset circuit for a carrier chip according to item 3 of the claim, wherein the secondary module includes: a second PMOS tube MP2 and a second NMOS tube MN2;
The gate of the second PMOS tube MP2 is connected to the output of the first-level voltage adjustment module, and its source is connected to the power supply;
The gate of the second NMOS transistor MN2 is connected to the output of the first-level voltage adjustment module, and its source is grounded; and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the second PMOS is The voltage between the drain of the tube MP2 and the drain of the second NMOS tube MN2 is used as the power-on reset voltage or the power-off reset voltage. The power-on reset circuit for a carrier chip according to item 1 of the claim, wherein the energy storage circuit includes: an electrolytic capacitor;
One end of the electrolytic capacitor is connected to a power supply, and the other end is connected to a second node voltage.