TWM569074U - Package structure of chip and sensing device - Google Patents

Abstract

A package structure of a wafer and a sensing component, comprising: a first substrate, a second substrate, an inter-substrate dielectric layer, an upper dielectric layer, and a lower dielectric layer; wherein a conductive line is formed on each of the upper and lower surfaces of the first substrate a second conductive substrate is formed on the lower surface of the second substrate, and the second substrate is embedded in the wafer; the inter-substrate dielectric layer is disposed between the first substrate and the second substrate, and the inter-substrate dielectric layer further comprises a plurality of conductive vias provide electrical connection between the wafer of the second substrate and the conductive circuit layer of the lower surface of the first substrate; the upper dielectric layer is disposed on the upper surface of the first substrate, and the conductive bump is disposed therein; the sensing component The soldering pad of the sensing component is electrically connected to the conductive bump, and the sensing region of the sensing component directly faces the first substrate and is separated from the first substrate by an appropriate distance.

Description

Wafer and sensing component package structure

This creation relates to a package structure of a wafer and a sensing element.

System-in-Package (SiP) is a kind of packaging concept. It is a kind of packaging technology developed based on System-on-Chip (SoC). Basically, SiP can be defined as: in an IC. The package contains one or more wafers, plus a package of any electronic components such as passive components, capacitors, resistors, connectors, antennas, etc.; in other words, in terms of structure, SiP can be assembled not only in one package. For a plurality of wafers, the different types of devices and circuit chips described above may be stacked in a 2D, 3D manner and integrated in one package; in terms of functionality, SiP is a system or subsystem (sub- All or most of the electronic functions of the system are configured in an integrated substrate to create a more complex and complete system.

SiP generally includes many different technologies, such as: Multi-chip Module (MCM) technology, Multi-chip Package (MCP) technology, Stack Die, PoP ( Package on Package), PiP (Package in Package), and technologies such as embedding the active/passive components in the substrate (Embedded Substrate). In terms of structural appearance, MCM belongs to 2D architecture, while MCP, Stack Die, PoP, PiP, etc. belong to 3D architecture.

Because SiP has the advantages of miniaturization, heterogeneous integration, reduced system board cost, shorter time-to-market, significantly reduced package size, weight, reduced power consumption, and improved product performance, In recent years, it has been favored by the industry. SiP can be widely used in many fields such as optical communication, sensors, and MEMS. For example, in the case of smart phones, it needs to have integrated functions, easy connection, light, short, and convenient to carry. Therefore, the IC should be More advanced processes integrate more functions, and the advantages of SiP are more competitive.

Referring to FIG. 1, FIG. 1 is a schematic view showing the arrangement of a wafer and a sensing element of the prior art. As shown in the first figure, the sensing element 11 is located above the wafer 13, and between the sensing element 11 and the wafer 13. The adhesive layer 12 is disposed, that is, the sensing element 11 is disposed on the wafer 13 through the adhesive layer 12, and the sensing portion 11a and the bonding pad 11b of the sensing element 11 are all facing upward, and therefore must pass through the wire bonding process. The pad 11b of the sensing element is electrically connected to the conductive block 10a of the substrate 10, and the bonding process and the adhesive material arrangement of the adhesive layer both increase manufacturing steps and affect manufacturing efficiency and even yield.

Moreover, the sensing component needs to be disposed on the wafer by an adhesive material. It is well known that the sensor device is susceptible to stress generated during packaging, particularly pressure and motion sensors, where the package stress is from the package. Thermal mechanical stress, thermomechanical stress can cause the sensor output signal to drift, especially with temperature. Therefore, if the adhesive material has a certain temperature, thermal stress will affect the function of the sensor, so it is necessary to provide a sense of package pressure. The package does not generate stress and is directly connected to the conductive lines on the substrate.

The main purpose of this creation is to provide a structure of a package sensor. When the sensor is a pressure sensor, it is not affected by the adhesive material stress, and the pressure sensor can directly electrically connect with the conductive line on the substrate. The pressure sensor having the sensing region has a sensing face down, and the pad of the pressure sensor is electrically connected to the solder ball or the conductive bump of the substrate without wire bonding. The sensing area and the substrate have an appropriate distance or a suitable space to accommodate the air and are not affected by the stress.

The preferred specific technical means of the present invention comprises a package structure of a wafer and a sensing component, comprising: a first substrate, a second substrate, an inter-substrate dielectric layer, and an upper dielectric layer. The lower dielectric layer and a sensing element.

A plurality of through-holes are formed in the first substrate, and a conductive circuit layer is formed on the upper and lower surfaces of the first substrate. The second substrate is provided with a plurality of substrate via holes, and the connection is a conductive circuit layer on the lower surface of the second substrate and a conductive circuit layer on the lower surface of the first substrate; a cavity is disposed in the second substrate, and a wafer is disposed in the receiving space The periphery of the accommodating space further includes a wafer isolation dielectric layer.

The inter-substrate dielectric layer is disposed between the first substrate and the second substrate, and the inter-substrate dielectric layer covers the conductive circuit layer on the lower surface of the first substrate, and the inter-substrate dielectric layer has a plurality of And a conductive via layer corresponding to the lower surface of the first substrate, the conductive vias are disposed in the via holes, and the conductive pads of the via holes provide the wafer of the second substrate and the first Electrical connection of the conductive circuit layer on the lower surface of the substrate.

The upper dielectric layer is disposed on the upper surface of the first substrate, covering the conductive circuit layer on the upper surface of the first substrate, and has a plurality of openings at the conductive circuit layer on the upper surface of the first substrate, And a portion of the surface of the conductive circuit layer exposed on the upper surface of the first substrate, the exposed portion of the surface may be provided with a conductive bump, the conductive bump and the conductive circuit layer on the upper surface of the first substrate, and the first substrate The substrate through-via and the conductive circuit layer on the lower surface of the first substrate are electrically connected, and the conductive bump comprises a solder ball or a solder ball and a ball under metallurgy layer, and the solder ball may be a tin shot or other Conductive material.

In a preferred embodiment, the sensing component is located on the upper dielectric layer, and one side of the sensing component has a sensing region and a solder pad, and the sensing component has a side of the sensing region. a space is defined between the upper dielectric layer and the upper dielectric layer, and the conductive circuit layer on the upper surface of the first substrate is coupled to the conductive bump (such as a solder ball) of the upper dielectric layer The pads of the sensing element form an electrical connection.

The sensing component can be a pressure sensor, a micro-electro-mechanical system (MEMS) sensor, a biomedical sensor, or other sensing function component.

In a preferred embodiment, the package structure of the chip and the sensing component is further provided with a cover having a receiving space, the cover is fixed on the first substrate and covers the sensing component, The sensing element can be protected from external force; if the sensing element is an element capable of sensing fluid pressure such as air, the cover body is further provided with an opening, and the gas in the cover body passes through the opening in the cover body And communicating with the gas outside the cover; because there is a space between the sensing element and the first substrate to allow air to pass, so when the pressure of the gas changes, the sensing region can effectively and sensitively detect the gas. The cover is covered by the sensing element and has the function of protecting the sensing element, and the setting of the opening of the cover can balance the pressure of the internal and external gases, and also helps to ensure the sensing performance of the sensing element.

In a preferred embodiment, the inter-substrate dielectric layer has a plurality of openings corresponding to the accommodating space of the second substrate, and the conductive bumps are pre-formed on the aluminum pad of the wafer. When placed in the accommodating space, the conductive bumps are electrically connected to the conductive circuit layer on the lower surface of the first substrate.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure of the present disclosure. The present invention may also be implemented or applied by other specific examples. The details of the present specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

The structure, the proportions, the sizes, and the like of the drawings are only used to cope with the contents disclosed in the specification for understanding and reading by those skilled in the art, and are not intended to limit the implementation of the creation. Conditions, so it is not technically meaningful, any structural modification, proportional change or size adjustment, should not affect the effect of this creation and the purpose it can achieve, should be revealed in this creation The technical content can be covered.

2 is a schematic diagram of an embodiment of a package structure of a wafer and a sensing element according to the present invention. As shown in FIG. 2, the package structure of the wafer and the sensing device of the present invention comprises: a first substrate 110, a second substrate 120, an inter-substrate dielectric layer 130, and a lower dielectric layer. 140 and an upper dielectric layer 150. The package structure is formed by stacking the above layers, and the lower dielectric layer 140, the second substrate 120, the inter-substrate dielectric layer 130, the first substrate 110, and the bottom layer. Upper dielectric layer 150.

It is to be noted that a plurality of substrate through holes 111 are further disposed in the first substrate 110, and a conductive circuit layer 112 is formed on each of the upper and lower surfaces of the first substrate 110. A plurality of substrate through holes 111 are disposed, and a conductive circuit layer 112 is formed on the lower surface of the second substrate. The second substrate 120 is further provided with a cavity 121 and is disposed in the capacitor. A wafer 122 is disposed in the space 121. The periphery of the accommodating space 121 further includes a wafer isolation dielectric layer 123. The wafer 122 is limited to the wafer isolation dielectric layer 123.

The inter-substrate dielectric layer 130 is disposed between the first substrate 110 and the second substrate 120, and further includes a plurality of via holes, wherein the conductive vias are provided with a conductive bump 124. The conductive pads are disposed. The electrical connection between the wafer 122 of the second substrate 120 and the conductive circuit layer 112 under the lower surface of the first substrate 110 is provided. In other words, the conductive circuit layer 112 on the upper and lower surfaces of the first substrate 110, the conductive circuit layer 112 on the lower surface of the second substrate 120, and the wafer 122 in the accommodating space 121 of the second substrate 120 are transparent. The substrate through-holes 111 of the substrate 110, the substrate vias 111 of the second substrate 120, and the conductive pads 124 of the inter-substrate dielectric layer 130 are electrically connected.

Moreover, the lower dielectric layer 140 covers the conductive circuit layer on the lower surface of the second substrate 120, and has a plurality of openings at the conductive circuit layer on the lower surface of the second substrate 120 to be exposed to the first a portion of the surface of the conductive circuit layer on the lower surface of the substrate, the exposed surface of the conductive circuit layer on the lower surface of the second substrate 120 may be provided with a conductive bump, the conductive bump comprising a solder ball 153 or a solder ball 153 and a The underlying metallurgy layer 152, the solder ball 153 may be a tin-lead material or other electrically conductive material; the upper dielectric layer 150 is disposed on the conductive circuit layer 112 on the upper surface of the first substrate 110, and is located on the first substrate 110. The conductive circuit layer on the upper surface has a plurality of openings to expose a portion of the surface of the conductive circuit layer 112 on the upper surface of the first substrate 110, and the exposed surface of the conductive circuit layer 112 on the upper surface of the first substrate 110 may be A conductive bump is disposed. The conductive bump comprises a solder ball 153 or a solder ball 153 and a ball under metallurgy layer 152. The solder ball 153 may be a tin-lead material or other conductive material.

It is to be noted that the package structure of the chip and the sensing component further includes a sensing component 154. The sensing component 154 is located on the upper dielectric layer 150. One side of the sensing component 154 has a sensing region. The first surface of the sensing element 154 having the sensing region 1541 is directed toward the upper dielectric layer 150 and defines a space between the sensing layer 154 and the upper dielectric layer 150, and is formed on the first substrate. The conductive bumps of the surface conductive circuit layer (for example, the solder balls 153 and the under-ball metallurgy layer 152) electrically connect the conductive circuit layer on the upper surface of the first substrate 110 to the sensing element 154 pads 1543.

The sensing component 154 is a pressure sensor, a micro-electro-mechanical system (MEMS) sensor, a biomedical sensor, a gas sensor, or other sensing function.

In a preferred embodiment, the package structure of the wafer and the sensing component further includes a cover 160 having a receiving space 161, and the cover 160 is sealingly fixed to the first substrate 110 or the upper dielectric layer 150. The cover member 154 is covered to protect the sensing element 154 from external force. If the sensing element 154 is used to sense the gas pressure, the cover 160 defines an opening 163 ( As shown in FIG. 3, the gas in the lid 160 passes through the opening 163 to communicate with the gas outside the lid 160.

Since the sensing element 154 and the first substrate 110 have a space similar to the air chamber, when the pressure of the gas changes, the sensing area 1541 can effectively and sensitively detect the change of the gas pressure; and the cover 160 The sensing element 154 is covered, and has the function of protecting the sensing element, and the opening 163 of the cover 160 is arranged to balance the internal and external gas pressures (as shown in FIG. 3), and also helps to ensure the sensing element. Sensing performance.

In a preferred embodiment, the inter-substrate dielectric layer 130 covers the conductive circuit layer 112 on the lower surface of the first substrate 110, and has a plurality of conductive circuit layers 112 on the lower surface of the first substrate 110. The conductive hole 124 is disposed on the exposed surface of the conductive circuit layer 112 on the surface of the lower surface of the first substrate 110, and the conductive pad 124 is disposed through the conductive pad 124. The aluminum pads 125 of the wafer 122 in the accommodating space 121 of the two substrates 120 are electrically connected.

The material of the first substrate 110 and the second substrate 120 may be: a polymer, a plastic, a ceramic, a metal, a Si wafer, a composite material (BT, FR4...), a glass or a soft board, and the like; The material used for the filler in the hole, the conductive layer, the conductive block or the conductive bump in the through hole, the conductive pad, etc. may be: metal or alloy material, Cu, Ag, Ni, Au, Sn, or a combination of the above metals. Such as Cu/Ni/Au, Cu/Ni/Sn, or composite conductive materials, such as silver paste, carbon glue; the upper dielectric layer 150, the lower dielectric layer 140, the inter-substrate dielectric layer 130, and the wafer isolation dielectric layer 123 and other materials can be: an insulating material, which can be PI, BCB, silicone materials, resins, composite materials, etc. with insulation, adhesion, dielectric and other characteristics.

Based on the above-described package structure of a chip and a sensing element, the present invention further provides a method of fabricating a package structure of a wafer and a sensing element. 4 is a flow chart showing an embodiment of a method for fabricating a package structure of a wafer and a sensing element. As shown in FIG. 4, a method for fabricating a package structure of a wafer and a sensing element of the present invention includes the following steps S1 to S6.

Step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a plurality of through holes, and a conductive circuit layer formed on the upper and lower surfaces of the first substrate; An upper dielectric layer is disposed on an upper surface of the substrate, the upper dielectric layer covering the conductive circuit layer on the upper surface of the first substrate, and having a plurality of openings on the conductive circuit layer on the upper surface of the first substrate And a hole exposed to a surface of the conductive circuit layer on the upper surface of the first substrate, wherein the exposed surface of the conductive circuit layer on the upper surface of the first substrate may be provided with a conductive bump, the conductive bump including a solder ball and a sub-metallurgical layer a plurality of substrate via holes are disposed in the second substrate, and a conductive circuit layer is formed on the lower surface of the second substrate and conductive bumps (solder balls and under-ball metallurgy layers) are formed on the conductive circuit layer. An accommodating space is further disposed in the second substrate, wherein the second substrate is provided with a plurality of substrate through holes, and the substrate through holes are connected to a conductive circuit layer formed on the lower surface of the second substrate At the first base Beneath the surface of the conductive wiring layer.

Step S2: performing the alignment bonding of the first substrate and the second substrate, wherein the step of bonding the first substrate and the second substrate is performed by bonding a first substrate with a viscous dielectric material. The second substrate is electrically connected to the substrate through-holes in the first substrate by reflow soldering; therefore, the viscous dielectric material is formed in the first substrate. An inter-substrate dielectric layer is formed between the substrate and the second substrate, and a plurality of via holes are formed in the dielectric layer between the substrates, and a conductive pad is disposed in the through holes.

Step S3: placing a wafer into the accommodating space of the second substrate in an inverted manner, aligning the aluminum pad of the wafer with the conductive bump of the conductive circuit layer on the lower surface of the first substrate, and reflowing to form Electrical connection.

Step S4: performing a wafer isolation dielectric layer filling process, filling a wafer isolation dielectric layer material around the wafer, such as on both sides of the wafer, to position, fix, and protect the wafer; and then, on the second substrate Forming a lower dielectric layer on the lower surface to cover the conductive circuit layer on the lower surface of the second substrate, and having a plurality of openings at the conductive circuit layer on the lower surface of the second substrate to expose to the second A portion of the surface of the conductive circuit layer on the lower surface of the substrate, and an exposed surface of the conductive circuit layer on the lower surface of the second substrate may be provided with conductive bumps.

Step S5: the sensing component is flipped on the upper surface of the first substrate, and is aligned with the conductive bumps on the conductive circuit layer on the upper surface of the first substrate (or solder balls, and there is a sub-metallurgical layer under the solder balls), and The sensing element is electrically connected to the conductive circuit layer of the first substrate by a reflow process.

Step S6: The cover member is covered by a cover body, and the cover body is fixed on the first substrate. If the sensing element can sense the gas pressure, the cover body is opened. The hole, the gas in the cover body communicates with the outside air only through the opening on the cover body.

In summary, the embodiment of the present invention discloses a package structure of a wafer and a sensing component, and specifically describes a method for fabricating the package structure of the wafer and the sensing component, and first completes the first substrate and the second substrate separately. And realigning the bonding, the second substrate and the first substrate are sequentially stacked on the bottom plate on the bottom plate separately from the substrate, and finally the aluminum pad is connected to the substrate line by a redistribution process.

The above description is only a preferred embodiment for explaining the present creation, and is not intended to impose any form of restriction on the creation, so that any modification or change related to the creation under the same creative spirit is provided. , should still be included in the scope of this creative intent.

(known technology)

10‧‧‧Substrate

10a‧‧‧Electrical block

11‧‧‧Sensor components

11a‧‧‧Sense Department

11b‧‧‧ solder pads

13‧‧‧ wafer

12‧‧‧Adhesive layer

(this creation)

110‧‧‧First substrate

111‧‧‧Substrate through hole

112‧‧‧ Conductive circuit layer

120‧‧‧second substrate

121‧‧‧ accommodating space

122‧‧‧ wafer

123‧‧‧Wet isolation dielectric layer

124‧‧‧Electrical mat

125‧‧‧Aluminum pad

130‧‧‧Inter-substrate dielectric layer

140‧‧‧lower dielectric layer

150‧‧‧Upper dielectric layer

152‧‧‧ under the ball metallurgy

153‧‧‧ solder balls

154‧‧‧Sensor components

1541‧‧‧Sense area

1543‧‧‧ solder pads

160‧‧‧ cover

161‧‧‧ accommodating space

163‧‧‧Opening

S1~S6‧‧‧Steps

FIG. 1 is a schematic view showing the arrangement of a wafer and a sensing element of the prior art. 2 is a schematic diagram of an embodiment of a package structure of a wafer and a sensing element according to the present invention. FIG. 3 is a schematic diagram of another embodiment of a package structure of a wafer and a sensing element according to the present invention. 4 is a flow chart of an embodiment of a method for fabricating a package structure of a wafer and a sensing element.

Claims (5)

A package structure of a chip and a sensing device, comprising: a first substrate, a second substrate, an inter-substrate dielectric layer, an upper dielectric layer, a lower dielectric layer, and a sensing element; wherein the first a plurality of substrate through holes are disposed in the substrate, and a conductive circuit layer is formed on each of the upper and lower surfaces; a plurality of substrate through holes are disposed in the second substrate, and a conductive circuit layer is formed on the lower surface thereof. An accommodating space is further disposed in the second substrate, wherein a chip is disposed in the accommodating space, and the periphery of the accommodating space further includes a wafer isolation dielectric layer; the inter-substrate dielectric layer is disposed on the first substrate The second substrate further includes a plurality of conductive vias, wherein the conductive vias respectively provide a conductive pad, and the conductive pads provide electrical properties of the conductive substrate of the second substrate and the lower surface of the first substrate. The upper dielectric layer has a plurality of openings on the upper surface of the first substrate, and a conductive bump is disposed in the openings, the conductive bump includes at least one solder ball; and the sensing component is Located on the upper dielectric layer One side of the sensing component has a sensing region and a solder pad, and a side of the sensing component having the sensing region faces a space between the upper dielectric layer and the upper dielectric layer. The solder pad of the sensing component is electrically connected to the conductive bump in the opening of the upper dielectric layer, and is electrically connected to the conductive circuit layer on the upper surface of the first substrate. The package structure of the wafer and the sensing element according to claim 1, wherein the sensing element is a pressure sensor, a MEMS sensor, a biomedical sensor or a gas sensor. The package structure of the wafer and the sensing device of claim 1, further comprising a cover having an accommodating space, the cover being fixed on the first substrate and covering the sensing component . The package structure of the wafer and the sensing device of claim 1, further comprising a cover having an accommodating space, the cover being fixed on the first substrate and covering the sensing component The cover body further has an opening, and the gas in the cover body communicates with the gas outside the cover body through the opening in the cover body. The package structure of the wafer and the sensing device of claim 1, wherein the conductive bump disposed in the upper dielectric layer further comprises a sub-metallurgical layer, and the under-metallurgical layer is disposed on the The solder ball is electrically connected to the conductive circuit layer on the upper surface of the first substrate and to the solder ball and the conductive circuit layer on the upper surface of the first substrate.