TWM567953U - Semiconductor package structure with spaced protrusions - Google Patents

Abstract

A semiconductor package structure having spacer protrusions is provided with at least two spacer protrusions on a substrate; a first wafer is disposed on the spacer protrusions and electrically connected to the substrate; and a second wafer is disposed on the substrate The substrate and the accommodating space surrounded by the spacers are electrically connected to the substrate; and a molding body covering the spacers, the first wafer and the second on the substrate The wafer fills the accommodating space; thereby reducing circuit wiring of the overall package structure, maintaining the strength of the semiconductor package structure, reducing the number of lead wires, and reducing the amount of lead used.

Description

Semiconductor package structure with spaced convex portion

This creation relates to the technical field of semiconductor packaging. In particular, the semiconductor package structure can reduce the circuit wiring of the overall package structure, maintain the strength of the semiconductor package structure, reduce the number of lead wires, and reduce the amount of lead used.

Conventional semiconductor packaging structures can be divided into two types: the first is a structure in which wafers are stacked on a substrate and then packaged; the second is a structure in which multiple wafers are arranged on a substrate and then packaged.

FIG. 1 shows a conventional packaging structure of a chip stack. This packaging structure is a method in which at least a first wafer B and a second wafer C are stacked on a substrate A, and then each wafer is wired D to the substrate A for electrical connection. Therefore, this package structure has a large number of lead times, and the circuit wiring of the overall package structure is more complicated.

Figure 2 shows another conventional packaging structure in which at least two wafers B and C are arranged on a substrate A. This structure will increase the area of the substrate and cause the overall package because multiple wafers are placed on the substrate. The structure size has increased, so for short and thin electronic products, it needs to be further overcome to reduce the size of the semiconductor package structure.

In addition, FIG. 3 shows the semiconductor device package structure disclosed in Taiwan Patent Publication No. 200623290. A groove A1 is formed on the upper surface of a substrate A. The groove A1 is built into a first chip B (passive component) and The first chip B is electrically connected to the substrate A, and then a second chip C (semiconductor element) is placed across the upper surface B of the substrate A above the groove A1, so that the package packaging structure can be compared with the conventional stacking package. Significantly reduce the overall package thickness to increase packaging efficiency.

However, the semiconductor package structure disclosed in Taiwan Patent Publication No. 200623290 is because the groove A1 is formed on the substrate A, so that the position of the substrate A in the groove A1 is reduced due to the reduced thickness; and because the first wafer B and the The second wafer C is disposed inside the groove A1 and outside the groove A1 respectively, so that wiring is complicated.

One of the objectives of this creation is to provide a semiconductor package structure that can reduce the complexity of circuit wiring of a package structure in the form of multiple wafer stacks.

Another purpose of this creation is to provide a semiconductor package structure that can maintain the strength of the package structure while reducing the overall thickness of the semiconductor package.

The technical package of the semiconductor package structure provided with spaced convex portions provided in this creation includes: a substrate; at least two spaced convex portions provided on the substrate; a first wafer provided on the spaced convex portions and connected with the spaced convex portions. The substrate is electrically connected; a second chip is disposed in an accommodating space surrounded by the substrate and the spaced convex portions, and is electrically connected to the substrate; and a plastic package covering the substrate on the substrate The space convex portion, the first wafer and the second wafer fill the accommodation space.

In an embodiment of the semiconductor package structure with a space convex portion, the space convex portion may be an independent component to be mounted on the substrate.

In another embodiment of the semiconductor package structure with a space convex portion, the space convex portion may be a rib formed on the substrate.

In an embodiment of the semiconductor package structure with spaced convex portions, the spaced convex portions may include two spaced convex portions and are disposed on opposite sides.

In another embodiment of the semiconductor package structure with spaced-apart protrusions, the spaced-apart protrusions may include four and are disposed at four corners of a rectangle.

In another embodiment of the semiconductor package structure with spaced-apart protrusions, the plan view of the spaced-apart protrusions may have a geometric shape.

Preferably, the geometric shape may be an L shape, and two spaced-apart convex portions adjacent to each other are symmetrically arranged.

Preferably, the spacer protrusions in the packaging structure of this creation are non-conductive insulating materials.

In one embodiment of the semiconductor packaging structure with spaced convex portions of the present invention, the non-conductive insulating material may be a Die Attach Film (DAF).

In another embodiment of the semiconductor package structure with spaced convex portions, the non-conductive insulating material may be an engineering plastic material.

The semiconductor package structure provided with spacer protrusions provided by this creation has the following advantages and effects: 1. This creation is by setting at least two spacer protrusions on the substrate, and directly placing a wafer on the spacer protrusions and communicating with the substrate. Sexual connection can reduce the complexity of circuit wiring of the overall packaging structure. 2. The spacer protrusions provided on the substrate can be ribs. The ribs can enhance the strength of the semiconductor package structure. 3. It can reduce the number of lead wires and the amount of lead material used.

The following explains the other purposes and functions of this creation in conjunction with the drawings, so that you can have a thorough understanding of this creation.

FIG. 4 shows a first embodiment of the semiconductor package structure with spaced convex portions of the present invention; as shown in FIG. 4, the semiconductor package structure with spaced convex portions provided by this material may include a substrate 1 and two spaced convex portions. The part 2, a first wafer 3, and a second wafer 4; wherein the substrate 1 is a circuit board on which necessary circuits are arranged. The spaced convex portion 2 is an independent element and is fixed and fixed to the surface of the substrate 1. For example, the spaced convex portion 2 can be fixed and fixed on the substrate 1 by using an adhesive. In the first embodiment of the present invention, The two spaced convex portions 2 may be disposed on symmetrical sides of the upper surface of the substrate 1, so that an accommodation space S is formed between the two spaced convex portions 2 and the substrate 1. The spaced convex portions 2 may preferably be non-conductive. Insulating materials such as Die Attach Film (DAF), engineering plastic materials, etc.

The first wafer 3 and the second wafer 4 may be passive components or other semiconductor components, respectively. First, the second wafer 4 is set in an accommodation space S surrounded by the substrate 1 and the spaced convex portions 2, and the second wafer 4 is electrically connected to a circuit on the substrate 1, for example, electrically connected by soldering; Then, the first wafer 3 is mounted and fixed on the spaced convex portions 2, for example, the first wafer 3 is adhered and fixed on the spaced convex portions 2 with an adhesive, and then performed between the first wafer 3 and the circuit on the substrate 1. Make a lead so that the first wafer 3 and the substrate 1 are electrically connected. Finally, the combined substrate 1, the spaced convex portion 2, the first wafer 3 and the second wafer 4 are put into a mold for a packaging process. In the packaging process, a liquid insulating plastic sealing material is injected into the mold. The mold flows to fill the containing space S, and at the same time, the upper surface of the substrate 1 is covered with each of the spaced protrusions 2, the first wafer 3 and the second wafer 4. After the molding material solidifies, a solid molding body 5 is formed to protect it. The first chip 3, the second chip 4, the lead 6 and the circuit are completed inside, and the whole package is completed.

FIG. 5 shows a second embodiment of the semiconductor package structure with spaced convex portions of the present invention; as shown in FIG. 5, the semiconductor package structure with spaced convex portions provided by the present invention may include a substrate 1 and two spaced convex portions The part 2, a first wafer 3, and a second wafer 4; wherein the substrate 1 is a circuit board on which necessary circuits are arranged. The spaced convex portions 2 are raised ribs that directly form a protruding structure on the upper surface of the substrate 1 when the substrate 1 is manufactured. In the second embodiment of the present invention, the two spaced convex portions 2 are arranged on the upper surface of the substrate 1. The two sides are symmetrical, so that an accommodation space S is formed between the two spaced protrusions 2 and the substrate 1. Similarly, the spaced protrusions 2 may preferably be made of a non-conductive insulating material, for example, a thin film die-bonding material ( Die Attach Film (DAF), engineering plastic materials, etc.

In the second embodiment of the present invention, the first wafer 3 and the second wafer 4 may be passive components or other semiconductor components, respectively. First, the second wafer 4 is set in an accommodation space S surrounded by the substrate 1 and the spaced convex portions 2, and the second wafer 4 is electrically connected to a circuit on the substrate 1, for example, electrically connected by soldering; Then, the first wafer 3 is mounted and fixed on the spaced convex portions 2, for example, the first wafer 3 is adhered and fixed on the spaced convex portions 2 with an adhesive, and then performed between the first wafer 3 and the circuit on the substrate 1. Make a lead so that the first wafer 3 and the substrate 1 are electrically connected. Finally, the combined substrate 1, the spaced convex portion 2, the first wafer 3 and the second wafer 4 are put into a mold for a packaging process. In the packaging process, a liquid insulating plastic sealing material is injected into the mold. The mold flows to fill the containing space S, and at the same time, the upper surface of the substrate 1 is covered with each of the spaced protrusions 2, the first wafer 3 and the second wafer 4. After the molding material solidifies, a solid molding body 5 is formed to protect it. The first chip 3, the second chip 4, the lead 6 and the circuit are completed inside, and the whole package is completed.

FIG. 6 shows a third embodiment of the semiconductor package structure with spaced convex portions of the present invention. As shown in FIG. 6, the semiconductor package structure with spaced convex portions provided by this material may include a substrate 1 and four spaced convex portions. The part 2, a first wafer 3, and a second wafer 4; wherein the substrate 1 is a circuit board on which necessary circuits are arranged. The four spaced convex portions 2 may be independent components, and are fixed and fixed to the surface of the substrate 1. For example, the spaced convex portions 2 may be fixed and fixed on the substrate 1 by using an adhesive; The portion 2 may also be a rib that directly forms a protruding structure on the upper surface of the substrate 1 when the substrate 1 is manufactured. In the third embodiment of the present invention, the four spaced convex portions 2 are arranged on one of the upper surfaces of the substrate 1. The positions of the four corners of the rectangle form an accommodation space S between the four spaced protrusions 2 and the substrate 1. Similarly, the spaced protrusions 2 may preferably be made of a non-conductive insulating material, such as a film Die Attach Film (DAF), engineering plastic materials, etc. Preferably, the planar view of the spaced convex portions 2 may have a geometric shape, such as an L shape, and two spaced convex portions 2 adjacent to each other are symmetrically arranged.

In the third embodiment of the present invention, the first wafer 3 and the second wafer 4 may be passive elements or other semiconductor elements, respectively. First, the second wafer 4 is set in an accommodation space S surrounded by the substrate 1 and the spaced convex portions 2, and the second wafer 4 is electrically connected to a circuit on the substrate 1, for example, electrically connected by soldering; Then, the first wafer 3 is mounted and fixed on the spaced convex portions 2, for example, the first wafer 3 is adhered and fixed on the spaced convex portions 2 with an adhesive, and then performed between the first wafer 3 and the circuit on the substrate 1. Make a lead so that the first wafer 3 and the substrate 1 are electrically connected. Finally, the combined substrate 1, the spaced convex portion 2, the first wafer 3 and the second wafer 4 are put into a mold for a packaging process. In the packaging process, a liquid insulating plastic sealing material is injected into the mold. The mold flows to fill the containing space S, and at the same time, the upper surface of the substrate 1 is covered with each of the spaced protrusions 2, the first wafer 3 and the second wafer 4. After the molding material solidifies, a solid molding body 5 is formed to protect it. The first chip 3, the second chip 4, the lead 6 and the circuit are completed inside, and the whole package is completed.

This creation uses the aforementioned semiconductor package structure with spaced convex portions. Since at least two spaced convex portions 2 are provided on the substrate 1, a wafer is soldered to the substrate 1, and the other wafer is directly disposed at the spaces. The bumps 2 are electrically connected to the substrate, so the complexity of the circuit wiring of the overall package structure can be reduced, the number of times of wiring can be reduced, and the amount of lead material used can be reduced. Furthermore, the thickness of the substrate 1 is not affected. Destruction or reduction, and the mounting of the spaced protruding portion 2 can strengthen the ribs, so that the strength of the semiconductor package structure can be enhanced.

The above is only a preferred embodiment for explaining this creation, and is not based on any restrictions on this creation. Therefore, any change in any form should still be included in the scope of protection of this creation.

1‧‧‧ substrate

2‧‧‧ space convex

3‧‧‧ the first chip

4‧‧‧Second Chip

5‧‧‧Plastic body

6‧‧‧ Lead

S‧‧‧ accommodation space

A‧‧‧ substrate

A1‧‧‧Groove

B‧‧‧First Chip

C‧‧‧Second Chip

D‧‧‧Leader

FIG. 1 is a schematic diagram showing a conventional package structure of a stacked wafer form; FIG. 2 is a schematic diagram showing a conventional package structure in which two wafers are arranged on a substrate; FIG. 3 is a semiconductor device package structure of Taiwan Patent Publication No. 200623290 Schematic diagram; FIG. 4 shows the first embodiment of the semiconductor package structure with spaced convex portions, where the spaced convex portions are independent components and mounted on the substrate; The second embodiment of the semiconductor package structure, wherein the spacer protrusions are ribs formed on the substrate; and FIG. 6 shows a third embodiment of the semiconductor package structure with spacer protrusions, which includes four L-shaped spaced convex portions are arranged at the four corners of a rectangle, and two spaced convex portions adjacent to each other are arranged symmetrically.

Claims (10)

A semiconductor package structure with spaced convex portions includes: a substrate; at least two spaced convex portions provided on the substrate; a first chip provided on the spaced convex portions and electrically connected to the substrate; A second chip is disposed in an accommodating space surrounded by the substrate and the spaced-apart convex portions, and is electrically connected to the substrate; and a plastic package, which covers the spaced-convex convex portions, the first A wafer and the second wafer fill the accommodation space. The semiconductor package structure with a spaced convex portion according to item 1 of the scope of application for a patent, wherein the spaced convex portion is an independent component to be mounted on the substrate. The semiconductor package structure with a spaced convex portion according to item 1 of the scope of patent application, wherein the spaced convex portion is a rib formed on the substrate. According to any one of claims 1 to 3 in the scope of the patent application, the semiconductor package structure with spaced convex portions includes two spaced convex portions and is disposed on opposite sides. According to any one of claims 1 to 3 of the scope of the patent application, the semiconductor package structure with spaced convex portions includes four spaced convex portions and is arranged at four corners of a rectangle. According to the semiconductor package structure with spaced convexities as described in item 5 of the scope of the patent application, wherein the spaced convex protrusions have a geometric shape in a plan view. According to the sixth aspect of the patent application, the semiconductor package structure having a spaced convex portion, wherein the geometric shape is an L shape, and two spaced convex portions adjacent to each other are symmetrically arranged. According to any one of claims 1 to 3 in the scope of the patent application, the semiconductor package structure having a spaced convex portion is a non-conductive insulating material. According to the semiconductor package structure with a spaced convex portion according to item 8 of the scope of the patent application, wherein the non-conductive insulating material is a thin film die attach material (Die Attach Film, DAF). According to the semiconductor package structure with a spaced convex portion according to item 8 of the scope of patent application, the non-conductive insulating material is an engineering plastic material.