TWM542244U - Three dimensional integrated circuit - Google Patents

Abstract

A three-dimensional integrated circuit (3DIC) structure comprises a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form the 3DIC device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.

Description

Three-dimensional integrated circuit [Reciprocal reference of related applications]

The disclosure of the present invention is intended to claim the benefit of the following provisional patent application, the entire disclosure of which is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety in

This creation is generally related to the manufacture of integrated circuit devices. More specifically, the present disclosure provides a final device for stacking and interconnecting three-dimensional devices that use heterogeneous and non-uniform layers, such as integrated circuits that are manufactured.

For example, an integrated circuit can include, for example, a memory device, a processor device, a digital signal processing device, a specific application device, a controller device, a communication device, and other devices.

According to the present creation, the technique is generally related to the manufacture of an integrated circuit device. In particular, this creation provides for the use of heterogeneous and non-uniform layers for stacking and interconnecting (eg, for manufacturing) A device for a three-dimensional device of an integrated circuit). For example, an integrated circuit can include, for example, a memory device, a processor device, a specific application device, a controller device, a communication device, and other devices.

The present invention provides a first substrate having a dielectric structure and a conductive structure. The ion system is implanted into the first substrate. The ions pass through the dielectric structure and the electrically conductive structure to define a cleavage plane on the first substrate. The first substrate is cleaved at the cleavage plane to obtain a cleave layer having a dielectric structure and a conductive structure. The cleavage layer is formed as one of a plurality of stacked integrated circuit layers of the three-dimensional integrated circuit device.

This creation provides three-dimensional stacking and interconnection of heterogeneous and non-uniform layers, such as integrated circuits that are manufactured. The technology involves substantially reducing intermediate layer separation and increasing the available intermediate layer connection density, resulting in increased signal bandwidth and system functionality.

In one example, the device includes a first substrate having a dielectric structure, a conductive structure, and a first interconnect structure. The first substrate includes a cleavage plane located on a side opposite to one of the first interconnect structures. The device further includes an oxide bonding layer and a three-dimensional integrated circuit device including the second interconnect structure bonded to the first substrate and in communication with the first interconnect structure to form a plurality of stacked integrated circuit layers (stacked IC layers) The second substrate. The first substrate is one of the IC layers stacked, and the second substrate is another layer of the IC layer.

100‧‧‧First substrate

102‧‧‧Transition device interconnection layer

104‧‧‧Transformer transistor layer

106‧‧‧Intermediate metal connection

108‧‧‧Open face

110‧‧‧ coolant flow path

112‧‧‧(first substrate) "bottom"

200‧‧‧Second substrate/lower device layer

202‧‧‧ below device interconnection layer

204‧‧‧The lower transistor layer

212‧‧‧(second substrate) "top"

300‧‧‧CVD oxide bonding layer

302‧‧‧ Bonding mat

400‧‧‧ Conversion substrate

401‧‧‧ patterned photoresist layer

402‧‧‧Uniformly patterned photoresist layer

403‧‧‧Metal interconnect layer

404‧‧‧Transistor layer

406‧‧‧Intermediate metal connection

410‧‧‧Intermediate coolant flow path

412‧‧‧Conversion device "bottom"

414‧‧‧Conversion device "top"

500‧‧‧High thermal conductivity thermal diffusion layer

P‧‧‧Proton Planting

S‧‧‧H profile

Figure 1 is a simplified cross-sectional view of the creation, with the "bottom" of the conversion device engaging the "top" layer of the lower device.

2 is an illustration of a heterostructure comprising a transistor device layer, an upper network of metal and low dielectric constant material, and an intermediate layer coolant channel for implantation through an additional patterned photoresist layer.

3 is a simplified cross-sectional view showing a patterned high heat transfer layer incorporating a coolant passage in place.

Figure 4 is a simplified cross-sectional view showing the top-to-top metal layer joined by the converter layer and the lower device layer in a three-dimensional integrated circuit stack.

According to the present creation, the technique is generally related to the manufacture of an integrated circuit device. In particular, the present disclosure provides means for stacking and interconnecting three-dimensional devices that use heterogeneous and non-uniform layers, such as integrated circuits that are manufactured. For example, an integrated circuit can include, for example, a memory device, a processor device, a digital signal processing device, a specific application device, a controller device, a communication device, and other devices.

In one example, this creation establishes and extends the performance of two major technical areas. Layer transitions for forming homogeneous layer junction stacks (such as the current use of Silicon Insulator (SOI) wafers), and by using a complex interposer and a sparse array of metal holes for inter-device connections A three-dimensional stack of electronic devices is formed.

In one example, the present invention provides stacking and interconnecting of different electrical and electromechanical layers with simplified bonding, and interconnect structures having physical dimensions 10 times or less from currently available interposer/germanium perforation methods. And to provide a greatly increased number of intermediate device electrical connection paths, so that the data conversion frequency band and three-dimensional device functions are greatly expanded. This creation also provides sensitive device protection from UV radiation associated with the use of high-energy proton beam lines and provides an intermediate layer network for the construction of coolant flow channels for stacking from a large number of start-up, operational 3D devices. Hot removal. Further details of this creation can be found in the present specification and the following.

Embodiments are compatible with various IC fabrication methods, including fabrication of complementary metal oxide semiconductor (CMOS) and random access memory (RAM).

Spreading in millions of electron volts allows passage through the entire device layer (10μms) Carry out thicker planting. Therefore, the entire CMOS device layer can be converted instead of a partial layer.

Particular embodiments may utilize variations in face-to-back stacking and face-to-face stacking engagement with corresponding interconnect depths, locations, densities.

In some embodiments, the total device layer components can be thinned (without intervening layers) and reduced RC losses, even through a connected high density intermediate device.

In various embodiments, the stress from the Cu/Si stress can be reduced by connecting to the "disabled wiring" region where the area is further reduced.

Figure 1 is a simplified cross-sectional view of one embodiment of the present invention. A heterogeneous layer comprising a transistor formed of a semiconductor material (usually germanium) and a plurality of dense metals (usually copper and various other metals for wires or holes) separated by a low dielectric constant electrically insulating material The device layer is separated from the semiconductor wafer after being formed by hydrogen implantation and corresponding cleavage. During proton implantation, the conversion device structure is covered with a uniform photoresist layer of sufficient thickness and protective properties to protect the device layer from UV radiation damage caused by recombination in the proton beam plasma. As shown in FIG. 1, the conversion device layer is also plated with a patterned second photoresist layer to adjust the depth of the proton beam and along the network path of the coolant flow path 110 to remove heat from a plurality of complete three-dimensional device stacks. The face 108 is finally opened. The electrically conductive structure includes a transistor junction in the substrate and a metal interconnect network in contact with the transistor layer.

After the upper device layer is fixed on the temporary bonding operation wafer, the lower surface of the switching device is cleaved to remove the implant damage in the region of the cleavage surface 108, and the thickness of the conversion device substrate layer is adjusted. A CVD oxide layer is then deposited on the lower surface to provide an effective joint surface and an electrically insulating passivation surface for the coolant flow path 110, if any. The lower device face is then etched and filled with metal, electrically connected to the converter interconnect layer 102 via a substrate and a deposited oxide layer having a thickness on the order of 1 μm or more to form an intermediate layer. The intermediate layer metal line in the upper switching device layer is terminated by a metal bonding pad having a bonding surface that is flush with the deposited oxide bonding layer.

A similar deposited oxide is formed on the top surface of the lower device to provide effective bonding. The perforated network is etched and filled with metal to provide electrical connection to the underlying device interconnect layer 202. The lower metal wire is terminated by a metal bond pad that is flush with the underlying oxide surface.

The two sets of metal bond pads are aligned with a precision joint and bonded to anneal to complete a two layer stack (with coolant flow path 110) as shown in FIG.

FIG. 2 illustrates the patterned photoresist layer 401 and the device layer after the layer is transferred to the lower device layer 200. In FIG. 2, the heterostructure comprises a transistor device layer, the upper network of the metal providing the integrated circuit interconnection and the low dielectric constant material is plated with a uniform photoresist layer, wherein the resistance characteristics and thickness are selected to provide sensitivity The IC layer and interface are suitably protected from exposure to ultraviolet light (wavelength less than 400 nm) radiation due to the composite effect under proton accelerated beamline plasma. The barrier and thickness of the uniform photoresist layer can also be selected to adjust the range of proton beams to the desired depth below the IC device transistor and depletion layer.

In FIG. 2, the second patterned photoresist layer is added to the uniform photoresist layer, and the barrier and thickness of the second photoresist layer are selected to regionally adjust the proton implantation depth to provide non-planar material sputtering. surface. After the photoresist layer is removed and temporarily bonded to the support layer, when the switching device layer is bonded to the lower device layer 200, the non-planar sputter surface provides a network channel reflecting the upper photoresist layer pattern to the coolant flow in the completed IC device In order to remove heat from the operation of the device in the stack.

Although FIG. 2 uses an absorbing material as a photoresist, it is not essential. In other embodiments, the absorbent material can be other materials including, but not limited to, oxides and/or nitrides.

As also shown in Figures 1-2, the intermediate layer metal vias, the transfer pads, and the oxide bonding interface are added to the lower region of the upper switching device layer before the upper switching device layer is bonded to the lower device layer 200.

In general, high performance logic devices generate heat in the high switching active area of the logic core. These switching heat sources are well known designs in complex system single-chip and central processing unit devices. problem. Data storage in memory devices is generally degraded as temperature increases, so the integrated stacking of logic and memory layers suffers from these thermal issues. As the density and dispersion of three-dimensional device stacks increase, thermal control becomes more important.

Although advantageous in thermal bonding efficiency, the use of an oxide layer as a thermal conversion layer in the bonding stack may be limited due to the relatively low thermal conductivity of SiO ₂ . The use of a high heat transfer rate, electrically insulating material as an intermediate layer structure can increase heat transfer from the local device heat source zone.

Accordingly, in certain embodiments it is preferred to add a structural high thermal conductivity layer between the heat generating device layers to promote heat diffusion and remove heat from the device stack. In particular, the use of high energy proton implantation, low heat accumulation layer splitting and switching engagement promotes the diffusion of heat from the "hot spot" of the local device structure and effectively removes thermal energy from the device by using a local coolant flow.

The following are the thermal conductivity of several common semiconductors and insulating films (unit: W/m-K)

Si: 130 (W/m-K)

SiO ₂ : 1.3 (W/mK)

SiC: 120 (W/m-K)

Ge: 58 (W/m-K)

GaAs: 52 (W/m-K)

Al ₂ O ₃ : 30 (W/mK)

The thickness of the intermediate thermal diffusion layer is approximately equal to 0.5 to 2 μm, and effective heat flow can be expected. Figure 3 shows a simplified cross-sectional view of a high thermal conductivity layer comprising a coolant channel in place.

The integrated circuit device including the semiconductor, dielectric, and metal material dispersion layers can generate substantial internal stress at the time of manufacture. Unresolved, these stresses can be high to warp the entire thickness of the germanium wafer having a thickness greater than 700 microns into various concave, convex, or complex potato wafer shapes. These deformations can be large enough to cause problems in the micro-diameter lithography optics at the time of device fabrication.

Stress-induced deformation on a wafer size combination can pose a challenge to bonding to a planar substrate surface if a stressed device layer on a separate thin (eg, a few microns) substrate is placed on a planar surface in an unsupported manner. Because of these effects, the thin device layers can be attached to the hard-bonded structure before they are separated from the original substrate wafer, maintaining the planar bonding interface to which the stress layer is attached.

Even if a hard temporary joint support is used to form the stressed layer into a planar form suitable for bonding, the uncompensated stress in the complex joint stack can cause joint failure and degradation of the IC device due to subsequent manufacturing steps and thermal stresses during operation of the device.

Thus, embodiments may provide an increased stress compensation layer on the back side of the stress device thin conversion layer to facilitate bonding, including improved interlayer handling and bond pad alignment, and compensate for the deleterious effects of subsequent manufacturing and device operation thermal cycling.

The backside stress compensating material may be selected from materials having complementary thermal expansion characteristics to the device layer and having a thickness sufficient to counteract the deformation effects of stresses within the device structure.

When the conversion device layer is attached to the temporary bonding structure, the stress compensation layer can be formed by direct layer conversion to the back side of the conversion device layer. In some cases, the stress compensation layer can be deposited by CVD or other methods.

Note that the planar, stress-compensated, and conversion layers provide the required geometry for achieving high-level bond pad alignment at wafer level bonding, which is a consideration for wafer-level bonding for successful 3D integrated circuit fabrication.

Particular embodiments may utilize a single crystal layer to convert to a chemical or mechanical "weak" separation layer. In particular, it is permissible to attach a layer of high purity, single crystal germanium material to the temporary support layer, which is sufficiently strong to survive the thermal, chemical and mechanical stresses of the IC or other device manufacturing process, but is sufficiently "weak" The separation path is formed under direct chemical or mechanical action.

Examples of such weak temporary separation layers may include, but are not limited to, (1) an oxide layer formed by thermal growth, CVD deposition, or by direct oxygen implantation followed by heat treatment, which may be subjected to a selective etching chemical reaction ( For example, HF bombardment covers the SiO ₂ layer), forming a separation path under the coating; and (2) various forms of polycrystalline germanium or porous form of the substrate material that are susceptible to forming a separation path under selective etching or mechanical bombardment. The form of direct mechanical bombardment may include, but is not limited to, (1) stress assisted fracture formation by lateral orientation forces on the dispersion wedge tool; and (2) injection into a mechanically weak layer (eg, porous substrate by laterally positioned flow) Dynamic attack of the material area).

Some forms of chemically or mechanically weakly dispersed layers may lack the high order crystalline germanium interface required to facilitate the fabrication of high purity and high quality crystalline germanium epilayers for high performance semiconductor devices.

High energy proton implantation is utilized to form a hydrogen-rich layer for mechanical, room temperature separation along a well-defined cleaved surface. Embodiments can be used to separate and bond the entire device structure, including the complete formation of the transistor layer, and the multilayer metal interconnect network for subsequent fabrication of a suitably separated temporary separation layer from the device integrated fabrication. This can be followed by separation of the self-supporting substrate.

Embodiments can also be used to separate and bond a uniform, high purity and crystalline layer formed in an electrical, mechanical or optical device, which can then be separated from the carrier substrate.

Embodiments may also provide proton implantation that can be used for separation and layer switching stacking of highly sensitive CMOS device structures. As previously mentioned, the embodiment utilizes high energy proton implantation to form a hydrogen-rich open face at a few microns below the bond thickness and to stop the power effect of the photoresist or CVD dielectric top layer combined with the multilayer metal interconnect network and the transistor layer.

The radiation damage effect of the high-dose, high-energy proton beam through the metal interconnect and the transistor layer is at a manageable level and can be recovered by a standard annealing cycle at the appropriate temperature. Moreover, embodiments may include an implementation of the problem of radiation damage effects in the dielectric layer of the avoidance device when particular consideration is given to a particular radiation damage effect.

One problem associated with possible radiation damage when implanting high-dose, high-energy protons into the metal interconnect network layer associated with the CMOS device layer is the breakdown of the various dielectric layers. Bad effect. The joint failure effect can result from an electron blocking event from the passage of a high energy proton beam or by ultraviolet-radiation of ion-electron relaxation and a recombination event in the accelerator beam line thereafter.

When high-dose, high-energy proton implants are performed at a particular point in time during CMOS device fabrication, the radiation effects from the proton beam can be substantially avoided. At one point in the fabrication of the CMOS device, the high temperature (eg, greater than 500 ° C) associated with the doping activation of the CMOS junction can be completed, and the interlayer oxide is deposited in the sensitive gate stack and subsequently bonded to the intermediate dielectric in the metal interconnect network. prior to.

At the time of this CMOS fabrication, the main material of the device wafer is a wafer having a polysilicon filling a lateral insulating region on the doped junction, and a substrate wafer. Among the main tantalum materials, the only substantial, long-term radiation damage effect is related to the lattice damage caused by the atomic core blocking component of proton deceleration.

The lattice damage event for a high-energy proton beam can be located near the peak of the proton beam profile. According to an embodiment, the peak may be located a few microns below the CMOS junction of the transistor layer and to provide a hydrogen capture critical location for positioning of the cleave plane during layer separation. The separation of a few microns between the CMOS transistor layer and its associated carrier depletion layer, and the proton induced lattice damage in the region separated by the subsequent layer may be sufficient to avoid the risk of harmful device effects in the proton lattice damage layer.

In many advanced CMOS devices, the gate stacking region is defined by a temporary film and a substituted structure. After the high temperature thermal cycle is completed, the replacement structure will be filled with a high dielectric constant "high-k" gate oxide and multiple layers. The final device structure of the metal gate electrode is replaced. After the "replacement gate" fabrication cycle, the final gate material properties and intermediate metal layer ("low-k") dielectric constraints are used for final CMOS device fabrication with thermal cycling below 500 °C.

Performing high-dose proton implantation at the time before the "replacement gate" is manufactured avoids the risk of dielectric damage to the gate and intermediate metal layers of the final device and is not exposed to thermal cycling at 500 ° C or higher; exposure to the above In the thermal cycle, it is possible to separate the non-thermal points required at the high temperature in the layer separation. Spontaneous layer separation is caused before completion and after the conversion device layer is completed.

Utilizing the device according to an embodiment may allow the intermediate layer band to be adjusted by the stacking order and the thickness of the intermediate layer. In particular, the primary goal of a three-dimensional integrated circuit is to provide an optional path to increase the bandwidth used for signal processing communication between devices.

Bandwidth is generated by the data signal frequency and is usually estimated by the CPU clock frequency and the number of external communication channels. As far as its history is concerned, the development of integrated circuits has focused on increasing the cycle frequency of CPUs and other data processing chips, which may result in an increase in the use of wafer power. The number of communication channels has been limited by the density of bond pads around the planar device.

Estimating the density of the intermediate layer communication lines, the development of three-dimensional integrated circuit stacks has increased the number of vertical channels possible. A convenient measurement of the density of the intermediate layer connections is the reciprocal square of the dispersion (or "pitch") of the communication pins. Specifically, the input and output (IO) density = 1 / (pin pitch) ² .

The minimum metal channel or "pin" pitch depends on various device considerations. One factor is the aspect ratio (AR) of the intermediate layer metal channel: the ratio of the metal wire diameter to the length of the through hole to be filled. A conventional "Through Silicon Via" (TSV) structure can have an appearance ratio of about 5 to 20. This is a typical design rule that is significantly higher than the high density metallization perforation for IC devices (appearance ratio is typically less than 2).

A device that affects the bulk density of a conventional TSV structure is an internal stress generated by a differential thermal expansion device of a micron-sized copper column and a crucible device material. Unwanted local stresses in the immediate vicinity of the copper perforation lines can result in a design rule defining a micron-sized "wire-free" region in which the active circuit components are excluded from the adjacent copper via transition pads. This can affect circuit density, performance and performance.

Thus, certain embodiments may provide one or more programs to locally increase the intermediate layer metal to density and the corresponding communication bandwidth between adjacent device layers. Use high-energy, high-dose proton implants, through a substantially complete metal interconnect network and fully form a CMOS transistor layer for The non-thermal layer separates and joins to the three-dimensional integrated circuit stack to form a hydrogen-rich region, providing a few microns (for device layers over the insulating layer of buried oxide or other device types with minimal carrier depletion layer thickness) Or less will be separated by the middle layer. This embodiment allows for substantially less intermediate layer separation than the typical tens of microns of typical existing TSV and interposer stacks. The thinner intermediate device layer and the removal of the interposer and associated adhesive layer provided by the embodiments allow for a shorter and thinner intermediate metal signal connection and greatly reduce the existing thermal stress caused by a few micrometer thick copper TSV channels. "Dead zone" effect.

When high intermediate layer bandwidth is required (eg, from the connection of the CMOS image sensor layer to the signal processing device), some embodiments may utilize various layer switching techniques to align and bond the top layer of the metal interconnect network of the conversion device to the three dimensional integrated circuit. An intermediate layer connection channel of the top layer of the metal network of the lower device layer in the stack.

With this particular procedure, the intermediate layer communication channel density can be expected to be similar to the pin density in the top metal layer in the two device layers (on the order of a few micrometers or less of the pin pitch). This "top-to-top" layer bonding produces an intermediate layer connection density that is 100 to 1000 times higher than existing 2.5D or 3D wafer stacking techniques, and correspondingly increases bandwidth.

4 is a simplified cross-sectional view showing the top-to-top metal layer in which the converter layer and the lower device layer 200 are joined in a three-dimensional integrated circuit stack. This method provides an intermediate layer metal connection 106 channel density and a corresponding increase in bandwidth, similar to the via density of the top metal layer of a CMOS device.

According to an embodiment, a specific example of a three-dimensional integrated circuit structure may be characterized by an IO density (unit: pins/cm ² ) of approximately 1.0E+06 to 1.0E+08, and a pitch pitch range (unit: nm). It is about 1.0E+02 to 1.0E+04. In one embodiment, for a TSV depth of 1 μm, the aspect ratio (depth: minimum width or diameter) may be 10 to 1, and the diameter of the pupil perforation is approximately 0.1 to 1 μm.

As described above, according to an embodiment, proton implantation forms a three-dimensional integrated circuit structure, Energy can be performed at 1 MeV, including energy of approximately 300 keV to 5 MeV, 500 keV to 3 MeV, 700 keV to 2 MeV, or 800 keV to 1 MeV.

It should be noted that in such a high energy range, the layer conversion for the insulating layer overlay wafer fabrication is characterized in that the implantation characteristics of hydrogen ions may have an energy variation between 40 keV. The primary description is the ratio of the "half width" of the proton beam profile of the reactive dispersion (<ΔX>) to the depth of the "projection range" beam profile (<X>).

An example of comparing <ΔX>/<X> is as follows: proton implantation energy 40keV: <△X>/<X>=0.196 0.2

Proton planting energy 1MeV: <△X>/<X>=0.048 0.05

Therefore, the 1 MeV proton beam profile is approximately 4 times sharper than the 40 keV beam profile.

Although the above is a complete description of the specific embodiments, various modifications, variations and equivalent arrangements are possible. Therefore, the scope of the present invention as defined by the scope of the appended claims is not limited by the foregoing description and description.

100‧‧‧First substrate

102‧‧‧Transition device interconnection layer

104‧‧‧Transformer transistor layer

106‧‧‧Intermediate metal connection

108‧‧‧Open face

110‧‧‧ coolant flow path

112‧‧‧(first substrate) "bottom"

200‧‧‧Second substrate/lower device layer

202‧‧‧ below device interconnection layer

204‧‧‧The lower transistor layer

212‧‧‧(second substrate) "top"

300‧‧‧CVD oxide bonding layer

302‧‧‧ Bonding mat

Claims (10)

An integrated circuit comprising: a first substrate having a dielectric structure, a conductive structure, and a first interconnect structure, the first substrate comprising a cleavage surface opposite to one side of the first interconnect structure; An oxide bonding layer; and a second substrate including a second interconnect structure bonded to the first substrate and in communication with the first interconnect structure to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit layers, The first substrate is one of the stacked integrated circuit layers, and the second substrate is another layer of the stacked integrated circuit layers, wherein the oxide bonding layer is disposed on the first substrate and the first substrate Between the two substrates. The integrated circuit of claim 1, wherein the second interconnect structure is bonded to the split surface. The integrated circuit of claim 1, wherein the second interconnect structure is bonded to the first interconnect structure. The integrated circuit of claim 1, wherein the three-dimensional integrated circuit device has an input/output density (unit: pins/cm ² ) of approximately 1.0E+06 to 1.0E+08, and a pitch pitch range (Unit: nm) is approximately 1.0E+02 to 1.0E+04. The integrated circuit of claim 1, wherein at least one region of the cleavage plane defines an array of coolant flow paths. The integrated circuit of claim 1, wherein the first substrate comprises a meandering perforation having an appearance ratio (depth: a minimum width of the diameter) of about 10 to 1, and the diameter of the perforated perforation is about 0.1 to 1 μm. . The integrated circuit of claim 1, wherein the split surface is rich in hydrogen. The integrated circuit of claim 7, wherein the hydrogen has a discrete proton range ratio of less than or equal to 0.1. The integrated circuit of claim 1, wherein the cleavage surface comprises implant destruction. The integrated circuit of claim 1 further comprising a high thermal conduction layer.