TWM528477U - computer system - Google Patents

Abstract

A computer system includes a CPU, a power circuit, a boot-up control circuit and a monitor circuit. The power circuit supplies electricity to the CPU. The boot-up control circuit receives an ON signal generated from a power switch which is triggered, and then the boot-up control circuit performs BIOS codes, so as to generate a power control signal and a device-ready signal. The power control signal is for enabling the power circuit. After the monitor circuit receives the ON signal over a predetermined time and does not receive the device-ready signal, the monitor circuit sends a reset signal to the boot-up control circuit, so as to reset the boot-up control circuit.

Description

computer system

This creation is about a computer system, in particular a computer system with a startup monitoring circuit that ensures that the system is properly turned on.

In today's computer system, the boot process is performed by the user pressing the power button and then sending a start signal. The embedded controller (EC) receives the start signal and then starts to execute the basic output input system (Basic). The input/output system (BIOS) code, and then the embedded controller executes a boot sequence according to the code to send a control signal to a power circuit (such as a power chip) and a processor (such as a central processor). . Then the processor reads the data of the storage medium (for example, a hard disk) and then starts the operating system to complete the booting process of the entire computer system.

However, during the boot process, the embedded controller may malfunction due to unexpected reasons, and the computer system cannot complete the boot process. The reasons may include: the embedded controller performs the basic output input system code. A crash occurs, a sequence error occurs during execution of the boot sequence, an interference signal generated by a hardware component, and the like. Today's embedded controllers have a reset function when they encounter an error. The basic output input system code can be refreshed and then re-started, but the embedded controller may still make the reset function for the aforementioned reasons. It is also impossible to successfully complete the computer system. sequence. Therefore, a computer system that can ensure that the embedded controller correctly executes the basic output input system code and starts up normally is a subject worth studying today.

In view of this, the present invention proposes a portable electronic device having a dual system chip to solve the above problems.

The present invention discloses a computer system including a central processing unit, a power supply circuit, a start control circuit, and a monitoring circuit. The power circuit is for providing power to the central processor. The startup control circuit executes a basic input/output system code after receiving a power-on button of the computer system to generate a power-on control signal and a device ready signal, and the power control signal is used to generate a power control signal and a device ready signal. Start the power circuit. The monitoring circuit is configured to send a reset signal to the start control circuit after the monitoring circuit receives the start signal and does not receive the device ready signal after receiving the power-on signal, thereby resetting the start control Circuit.

The present invention provides a computer system, a computer system, wherein the startup control circuit of the computer system includes a watchdog timer, which can reset the startup control circuit when the startup control circuit executes an error in the BIOS code, and the computer system further includes a monitoring circuit, when the watchdog timer cannot reset the startup control circuit and activates the control circuit to execute the BIOS code or the power-on sequence has an error, the monitoring circuit can send a reset signal to the startup control circuit, so that the startup control circuit is heavy After the installation, the BIOS code and the power-on sequence can be executed normally, and the computer system is normally turned on. Therefore, in the prior art, the reset function of the embedded controller cannot solve the problem that the system is normally turned on when it fails.

100‧‧‧ computer system

102‧‧‧Central processor

104‧‧‧Storage device

106‧‧‧Power circuit

108‧‧‧Start control circuit

1081‧‧‧Watchdog Timer

110‧‧‧Monitoring circuit

112‧‧‧Power button

114‧‧‧Power unit

ON‧‧‧Start signal

PWR‧‧‧ power control signal

DevRdy‧‧‧Device Ready Signal

Reset‧‧‧Reset signal

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.

The following description is an embodiment of the present creation. Its purpose is to exemplify the general principles of this creation and should not be considered as a limitation of this creation. The scope of this creation is subject to the definition of the scope of patent application.

It should be noted that the disclosure below provides a number of embodiments or examples for practicing the different features of the present teachings. The specific component examples and arrangements described below are intended to be illustrative of the spirit of the present invention and are not intended to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or characters in various examples. However, the re-use is for the purpose of providing a simplified and clear description, and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. In addition, the description of one of the features described in the following description is connected to, coupled to, and/or formed on another feature, etc., and may include a plurality of different embodiments, including direct contact of the features, or other additional Features are formed between the features and the like such that the features are not in direct contact.

Please refer to FIG. 1 , which is a block diagram of a computer system 100 according to an embodiment of the present invention. The computer system 100 can be any desktop or portable electronic device, including but not limited to a handheld computer, a tablet computer, a mobile phone, and a mobile internet device ( Mobile Internet Device, MID), Personal Digital Assistant (PDA), sales office Electronics at the point of sale or other similar devices, and including combinations of two or more of the above devices, however, those skilled in the art will appreciate that the present teachings are not limited thereto.

The computer system 100 can include a central processing unit 102, a storage device 104, a power supply circuit 106, a startup control circuit 108, a monitoring circuit 110, a power button 112, and a power supply unit 114. It should be understood that computer system 100 is only one example of various computer systems that may have more or fewer components than the illustrations, or have different component configurations.

The information used by the central processing unit 102 is stored in the storage device 104, and the storage device 104 can be a long-term storage device. The storage device 104 stores data required for the operation of the central processing unit 102 and other information required by the computer system 100. For example, the storage device 104 stores image data, multimedia files (such as music or video files), preference information (such as multimedia playback preferences), wireless connection information (for example, information for the computer system 100 to establish a wireless connection, wireless) Links such as phone connections, subscription information (for example, for periodic recording of podcasts, TV shows or other multimedia information subscribed to by users), telephone information (such as phone numbers) and any other suitable information. The storage device 104 can be a non-volatile memory such as a read only memory (ROM), a flash memory, a hard disk, an optical computer readable medium, or a magnetic computer readable medium. , solid state computer readable media and any combination thereof.

The power circuit 106 is a Power Integrated Circuit for providing power to various devices and components in the computer system 100, such as the central processing unit 102, the storage device 104, and the startup control circuit. 108, monitoring circuit 110, memory (not shown), wireless module (not shown), liquid crystal display (not shown), etc., so that each device and component can operate normally.

The startup control circuit 108 is an embedded controller (EC), which can be used to execute a basic input/output system (BIOS, hereinafter referred to as BIOS). The BIOS is a firmware used to ensure that various components and devices within a computer system (such as computer system 100) are effectively activated. When the computer system 100 is powered on for the first time, the BIOS performs a set of settings specifically designed for the BIOS. In general, the BIOS recognizes, initializes, and tests the hardware components and devices of a computer system.

For example, the BIOS will first start a power on self test (POST) and then load the operation system (Operation system). The BIOS provides the user with an interface to set various parameters. For example, the user can adjust the parameters of the BIOS to change the operating clock of the central processor 102, the speed of the bus on the motherboard, and other parameters that affect the performance of the computer system 100. Finally, the BIOS will transfer control of the computer system 100 to the operating system. Operating systems may include, but are not limited to, Berkeley Software Distribution (BSD), Linux, OS X, Unix-like Real-time Operating System (eg, QNX), Microsoft Windows, Window Phone, and IBM z/OS. Furthermore, the BIOS settings are stored in a non-volatile memory (not shown), such as a non-volatile random-access memory (NVRAM) or a read-only memory ( Read-only memory, ROM).

The monitoring circuit 110 can be a counter circuit (counter Circuit) for monitoring whether a signal to start the control circuit 108 is received. For example, the monitoring circuit 110 can be configured to send a control signal to the startup control circuit 108 when the computer system 100 is powered on for more than a predetermined time without receiving the signal from the startup control circuit 108. The power button 112 is a switch on the computer system 100. When the user presses the power button 112, the power button 112 generates a power-on signal ON for transmission to the start control circuit 108 and the monitoring circuit 110, respectively. The power unit 114 is a button cell battery that provides DC power to the start control circuit 108, the monitoring circuit 110, and the power circuit 106 when the user does not press the power button 112. That is, the power supply unit 114 can cause the startup control circuit 108, the monitoring circuit 110, and the power supply circuit 106 to maintain their corresponding settings, such as various power-on settings in the BIOS.

Next, the procedure when the computer system 100 is turned on will be described. When the user presses the power button 112, the power button 112 generates a power-on signal ON, and simultaneously sends it to the startup control circuit 108 and the monitoring circuit 110. After the startup control circuit 108 receives the power-on signal ON, a basic input/output system code (BIOS code) is executed to generate a power control signal PWR. The power control signal PWR is used to activate the power circuit 106. The power circuit executes a power sequence according to the power control signal to activate the central processing unit 102 and related components (such as a memory, a display screen, a keyboard, a touchpad, etc.), and the central processing unit 102 The data of the storage device 104 is accessed after startup to execute the operating system. When the power-on sequence is completed, the startup control circuit 108 generates a device ready signal DevRdy for transmission to the monitoring circuit 110.

Furthermore, the startup control circuit 108 can include a watchdog timer 1081 for performing the basic input and output system when the startup control circuit 108 is executed. When an error occurs in the system code, the startup control circuit 108 is reset. However, during the startup of the computer system 100, various unexpected errors may still occur, causing the watchdog timer 1081 to still fail to reset the boot control circuit 108, such as a BIOS code error or due to a fault on the motherboard of the computer system 100. The voltage on some electronic components is unstable, causing an error in the power-on sequence. In this case, the startup control circuit 108 does not transmit the device ready signal DevRdy to the monitoring circuit 110.

When the monitoring circuit 110 receives the power-on signal ON after the predetermined time has elapsed and the device ready signal DevRdy has not been received, for example, more than 10 microseconds, the monitoring circuit 110 sends a reset signal Reset to the start control. Circuit 108 is used to reset startup control circuit 108. After the startup control circuit 108 receives the reset signal Reset, the BIOS code is re-executed. Therefore, the monitoring circuit 110 can send the reset signal Reset to reset the startup control circuit 108 when the watchdog timer 1081 cannot reset the startup control circuit 108, and can enable the computer system 100 to normally complete the booting process.

In contrast, if the monitoring circuit 110 receives the power-on signal ON and receives the device ready signal DevRdy within the predetermined time, the monitoring circuit 110 does not send the reset signal Reset to the startup control circuit 108. Therefore, the computer system 100 will normally execute the boot process.

Compared to the prior art, the present invention provides a computer system 100 in which the boot control circuit 108 of the computer system 100 includes a watchdog timer 1081 that can be activated when the boot control circuit 108 executes an error in the BIOS code. In addition, the computer system 100 further includes a monitoring circuit 110. When the watchdog timer 1081 cannot reset the startup control circuit 108 and activates the control circuit 108 to execute the BIOS code or the power-on sequence error occurs. The monitoring circuit 110 can send a reset signal to the startup control circuit 108, so that the BIOS code and the power-on sequence can be normally executed after the startup control circuit 108 is reset, so that the computer system 100 is normally powered on. Therefore, in the prior art, the reset function of the embedded controller cannot solve the problem that the system is normally turned on when it fails.

The above is an overview feature of the embodiment. Those of ordinary skill in the art should readily be able to use the present invention as a basis for design or adaptation to perform the same purpose and/or achieve the same advantages of the embodiments described herein. It should be understood by those of ordinary skill in the art that the same configuration should not depart from the spirit and scope of the present invention, and various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present invention. The illustrative methods are merely illustrative of the steps, but are not necessarily performed in the order presented. The steps may be additionally added, substituted, changed, and/or eliminated, as appropriate, and are consistent with the spirit and scope of the disclosed embodiments.

100‧‧‧ computer system

102‧‧‧Central processor

104‧‧‧Storage device

106‧‧‧Power circuit

108‧‧‧Start control circuit

1081‧‧‧Watchdog Timer

110‧‧‧Monitoring circuit

112‧‧‧Power button

114‧‧‧Power unit

ON‧‧‧Start signal

PWR‧‧‧ power control signal

DevRdy‧‧‧Device Ready Signal

Reset‧‧‧Reset signal

Claims (10)

A computer system comprising: a central processing unit; a power supply circuit for supplying power to the central processing unit; and a startup control circuit for performing after receiving a power-on signal of one of the computer systems being triggered to generate a power-on signal a basic input/output system code for generating a power control signal and a device ready signal, wherein the power control signal is used to activate the power circuit; and a monitoring circuit for receiving the power signal after the monitoring circuit receives the power signal When the device ready signal is not received for a predetermined time, the monitoring circuit sends a reset signal to the start control circuit to reset the start control circuit. The computer system of claim 1, further comprising a power supply unit for supplying power to the startup control circuit and the monitoring circuit. The computer system of claim 2, wherein the power unit is a button cell battery. The computer system of claim 1, wherein the monitoring circuit does not send the reset signal to the start control when the monitoring circuit receives the power-on signal and receives the device ready signal within the predetermined time. Circuit. The computer system of claim 1, wherein the monitoring circuit is a counter circuit. The computer system of claim 1, wherein the startup control circuit includes a watchdog timer for resetting when the startup control circuit executes the basic input/output system code and an error occurs. The start control circuit. The computer system of claim 1, wherein the predetermined time is less than 10 microseconds. The computer system of claim 1, wherein the computer system further comprises a storage device, the power circuit is configured to perform a power-on sequence according to the power control signal, thereby starting the central processor, and the central processor The data of the storage device is accessed after startup to execute an operating system. The computer system of claim 8, wherein the startup control circuit sends the device ready signal to the monitoring circuit after the power-on sequence is completed, and when the startup control circuit executes the power-on sequence When an error occurs, the start control circuit does not send the device ready signal to the monitoring circuit. The computer system of claim 1, wherein the startup control circuit is an embedded controller for executing the basic input/output system.