TWM521809U - Solar cell structure with doped polysilicon contact - Google Patents

Abstract

A solar cell structure includes a semiconductor substrate having a front side and a rear side, at least a passivation layer on the rear side, and a doped polysilicon contact on the passivation layer. The passivation layer is composed of silicon dioxide and has a thickness that is not greater than 2 nm. The doped polysilicon contact is in direct contact with the passivation layer. The doped polysilicon contact has a thickness ranging between 5 and 100 nm.

Description

Solar cell structure with doped polysilicon electrode

The present invention relates to the field of solar cell technology, and more particularly to a solar cell structure having a doped polysilicon electrode.

It is known that the working principle of solar cells is to use solar radiation energy and semiconductor materials to generate electrical energy. The main materials include semiconductor materials such as single crystal germanium, polycrystalline germanium, amorphous germanium germanium or III-V compound. A semiconductor material or the like, and a conductive paste used as an electrode, for example, a silver paste or an aluminum paste.

Generally, the solar cell manufacturing method first performs wafer surface cleaning and roughening treatment, and then performs a diffusion process to form a phosphor glass layer and an impurity emitter region on the surface of the wafer, and remove the phosphor glass layer by an etching process. Then, an anti-reflection layer is formed, and then the electrode pattern is printed on the metal paste web on the front and back sides of the battery by screen printing technology, and then sintered at a high temperature to form an electrode. Finally, string welding is performed to connect the battery cells in series.

In addition, the industry has also proposed a Heterojunction with Intrinsic Thin Layer (HIT) solar cell, which uses an amorphous germanium film to reduce the surface recombination rate of the carrier and further improve the photoelectric conversion efficiency of the solar cell. The currently mass-produced HIT solar cells have a conversion efficiency of 22%, which is superior to N-type single crystal cells (21%) and P-type polycrystalline cells (20.5%).

Although the above HIT solar cell has the characteristics of high conversion efficiency, low carrier loss rate, and high temperature characteristics, in the preparation of such a solar cell, the subsequent sintering temperature needs to be controlled at a relatively low temperature to avoid the recrystallization of the amorphous germanium. Crystallization, thus limiting the flexibility of the process.

The primary purpose of this creation is to provide an improved solar cell structure that addresses the deficiencies and shortcomings of the prior art.

According to the present invention, a solar cell structure includes a semiconductor substrate having a front surface and a back surface; at least one passivation layer disposed on the back surface of the semiconductor substrate; and a doped polysilicon electrode disposed on the passivation layer on. Wherein, the passivation layer comprises cerium oxide and has a thickness of not more than 2 nm. The doped polysilicon electrode is in direct contact with the passivation layer, and the doped polysilicon electrode has a thickness of 5 to 100 nm.

The above described objects, features and advantages of the present invention will become more apparent from the following description. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the present invention.

Referring to FIG. 1 , it is a schematic cross-sectional view of a solar cell structure having a doped polysilicon electrode according to an embodiment of the present invention.

As shown in Fig. 1, the solar cell structure 1 includes a semiconductor substrate 10, for example, an N-type or P-type doped crystalline germanium substrate or a crystalline germanium wafer having a thickness of, for example, about 60 to 200 μm, but is not limited thereto. On the front surface (light receiving surface) S1 of the semiconductor substrate 10, a pyramidal structure 101 is formed by a surface roughening process. Typically, a wafer surface cleaning process is performed before (or after) the formation of the pyramidal structure 101 to remove contaminants.

According to the present embodiment, on the pyramid-shaped structure 101 of the front surface S1 of the semiconductor substrate 10, a composite layer 108 is provided, for example, including a passivation layer 110 and an anti-reflection layer 112, wherein the passivation layer 110 may be ruthenium dioxide, thickness The anti-reflection layer 112 may be not less than 2 nm, and the anti-reflection layer 112 may be tantalum nitride, hafnium oxynitride or aluminum oxide, but is not limited thereto. According to the present creative embodiment, the front metal electrode 120 may be disposed on the anti-reflective layer 112. Further, a doping region 12 such as an N-type or P-type doping region may be further provided on the front surface S1 of the semiconductor substrate 10.

According to the present embodiment, on the back surface S2 of the semiconductor substrate 10, a passivation layer 210, for example, cerium oxide, having a thickness of not more than 2 nm is provided. On the passivation layer 210, an N-type or P-type doped polysilicon electrode 212 is provided, for example, having a thickness of 5 to 100 nm. The doped polysilicon electrode 212 is in direct contact with the passivation layer 210. A back metal electrode 220 may be additionally disposed on the doped polysilicon layer 212.

According to the present embodiment, the solar cell structure 1 includes a doped polysilicon electrode 212, and a heterojunction structure is formed on the back surface S2 thereof. In contrast, no amorphous silicon is formed on the front surface S1. Floor.

2 to 7 are schematic cross-sectional views showing a method of fabricating a solar cell structure having a doped polysilicon electrode according to the present embodiment.

First, as shown in FIG. 2, a semiconductor substrate 10 such as an N-type or P-type doped crystalline germanium substrate or a crystalline germanium wafer is provided. Further, a surface cleaning process and a surface texture process of the semiconductor substrate 10 are performed by a chemical etching process, and a roughened (or pyramidal) structure 101 is formed on the front surface S1 and the back surface S2 of the semiconductor substrate 10.

As shown in FIG. 3, the back surface S2 of the semiconductor substrate 10 can then be polished by a chemical solvent to form a flat surface. Next, a doping region 12 may be formed on the front surface S1. The doping region 12 can be formed by using a diffusion furnace to provide diffusion of phosphorous chloride oxide (POCl ₃ ) gas, and then using a wet etching method such as hydrofluoric acid (HF) to remove the semiconductor substrate 10 . Phosphorus glass (PSG) on the surface (not shown).

As shown in FIG. 4, a passivation layer 110 and a passivation layer 210 are formed on the front surface S1 and the back surface S2 of the semiconductor substrate 10, respectively. For example, the passivation layer 110 and the passivation layer 210 may be cerium oxide, aluminum oxide, cerium nitride, cerium oxynitride, or the like, and have a thickness of not more than 2 nm. For example, if the passivation layer 110 and the passivation layer 210 are cerium oxide, they can be formed at a high temperature of 700 to 800 degrees by using a high temperature furnace tube, or can be cleaned and grown by using a chemical solvent. The passivation layer 110 and the passivation layer 210 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD) if they are alumina, tantalum nitride, hafnium oxynitride or the like.

Next, as shown in FIG. 5, an anti-reflection layer 112, for example, tantalum nitride or hafnium oxynitride, is further deposited on the passivation layer 110 of the front surface S1 of the semiconductor substrate 10 by plasma enhanced chemical vapor deposition (PECVD). , but not limited to this. The anti-reflection layer 112 may have a thickness of 80 to 100 nm.

As shown in FIG. 6, next to the passivation layer 210 on the back surface S2 of the semiconductor substrate 10, an atmospheric pressure chemical vapor deposition (APCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a low pressure chemical vapor phase By deposition (LPCVD) or organometallic chemical vapor deposition (MOCVD), a doped polysilicon contact 212 is grown which may be N-doped or P-doped. The thickness of the doped polysilicon electrode 212 is, for example, between 5 and 100 nm.

Finally, as shown in FIG. 7, the front surface metal electrode 120 and the back surface metal electrode 220 are formed on the front surface S1 and the back surface S2 of the semiconductor substrate 10, respectively. The front metal electrode 120 and the back metal electrode 220 may be formed by screen printing or electroplating, but are not limited thereto. It should be noted that the above various process steps and sequences are merely illustrative, and the technical means and methods used are merely examples, and the material of each film layer is not limited to the above description.

The above descriptions are only preferred embodiments of the present invention, and all changes and modifications made by the scope of the patent application of the present invention should be covered by the present invention.

1‧‧‧Solar cell structure
10‧‧‧Semiconductor substrate
12‧‧‧Doped area
101‧‧‧ Pyramidal structure
108‧‧‧Composite layer
110‧‧‧ Passivation layer
112‧‧‧Anti-reflective layer
120‧‧‧Front metal electrode
210‧‧‧ Passivation layer
212‧‧‧Doped polycrystalline germanium electrode
220‧‧‧Back metal electrode
S1‧‧‧Front (glossy)
S2‧‧‧Back

1 is a schematic cross-sectional view showing a structure of a solar cell having a doped polysilicon electrode according to the present embodiment. 2 to 7 are schematic cross-sectional views showing a method of fabricating a solar cell structure having a doped polysilicon electrode according to the present embodiment.

1‧‧‧Solar cell structure

10‧‧‧Semiconductor substrate

12‧‧‧Doped area

101‧‧‧ Pyramidal structure

108‧‧‧Composite layer

110‧‧‧ Passivation layer

112‧‧‧Anti-reflective layer

120‧‧‧Front metal electrode

210‧‧‧ Passivation layer

212‧‧‧Doped polycrystalline germanium electrode

220‧‧‧Back metal electrode

S1‧‧‧Front (glossy)

S2‧‧‧Back

Claims (8)

A solar cell structure comprising: a semiconductor substrate having a front surface and a back surface; at least one passivation layer disposed on the back surface of the semiconductor substrate; and a doped polysilicon electrode disposed on the passivation layer. The solar cell structure of claim 1, wherein the semiconductor substrate further has a doped region on the front side. The solar cell structure of claim 2, wherein the doped region is provided with a composite layer. The solar cell structure of claim 3, wherein the composite layer comprises cerium oxide, cerium nitride, cerium oxynitride or aluminum oxide. The solar cell structure of claim 1, wherein the passivation layer comprises hafnium oxide. The solar cell structure of claim 1, wherein the passivation layer has a thickness of not more than 2 nm. The solar cell structure of claim 1, wherein the doped polysilicon electrode is in direct contact with the passivation layer. The solar cell structure according to claim 1, wherein the doped polysilicon electrode has a thickness of 5 to 100 nm.