TWM519756U - USB chipset - Google Patents

Abstract

A USB chipset coupled between an first device and a second device and including a data processing unit and a transmitter is provided. The data processing unit generates a plurality of transmission information according to first information provided by the first device. The transmitter transmits the transmission information to the second device and includes a transforming module, a first output driving module, a second output driving module and a transmitting selecting module. The transforming module receives the transmission information in parallel and serially transmits the transmission information. The first output driving module is coupled to a first pin set. The second output driving module is coupled to a second pin set. The transmitting selecting module is coupled between the transforming module and the first and second output driving modules.

Description

USB chipset

This creation is about a USB chipset, especially a USB chipset that is built into the USB Type-C specification for a built-in selection module.

With the advancement of technology, there are more and more types of electronic devices. The electronic device can transmit data to and from a host device through a communication interface. In many of the current communication interfaces, the Universal Serial Bus (USB) interface is most commonly used. However, conventional USB chips utilize an output pin set and an input pin set to transmit and receive data.

In order to improve the flexibility of USB chip transfer and reception data, the purpose of this creation is to provide a USB chipset that can switch between two sets of output pins and input pins to transmit and receive data in response to the USB Type-C specification connector. To achieve the above objective, the present invention provides a USB chipset coupled between a first device and a second device, and includes a data processing unit and a transmitting unit. The data processing unit generates a plurality of transmission information according to the first information provided by the first device. The sending unit provides the transmission information to the second device, and includes a conversion module, a first output driving module, a second output driving module, and a transmitting end selection module. The conversion module receives the transmission information side by side and outputs the transmission information in series. The first output driving module is coupled to a first pin group. The second output driving module is coupled to a second pin group. The transmitting end selection module is coupled between the conversion module and the first and second output driving modules.

The present invention further provides a USB chipset including a data processing unit, a transmitting unit, a first pin group and a second pin group. The data processing unit generates a plurality of transmission information according to a first information provided by the first device. The transmitting unit processes the transmitted information to generate an output signal. The first and second pin sets are used to transmit an output signal to a second device.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and the detailed description is as follows:

100‧‧‧ operating system

110‧‧‧External devices

120‧‧‧USB chipset

130‧‧‧Host device

P ₁ ~P ₅ ‧‧‧ Pin set

121‧‧‧Data Processing Unit

124‧‧‧Detection unit

SR‧‧‧Processing signals

ST‧‧‧Transfer information

S _D ‧‧‧Detection signal

250, 260‧‧‧ pre-drive module

SE ₁ ~SE ₈ ‧‧‧Enhanced signal

SI‧‧‧ input signal

SD ₁ , SD ₂ ‧ ‧ differential signal

SS ₁ , SS ₂ ‧‧‧ set value

342, 345‧‧‧Differential pair

343, 346‧‧‧ Current Module

V _OP1 , V _OP2 ‧‧‧ operating voltage

TXP1, TXN1, TXP2, TXN2, CC1, CC2, RXP1, RXN1, RXP2, RXN2‧‧‧ pins

122, 200A, 200B, 200C‧‧‧ sending unit

123, 300A, 300B, 300C, 300D, 300E‧‧‧ receiving units

210A, 210B, 210C‧‧‧ conversion module

341, 344‧‧‧ Current conversion voltage module

220A, 220B, 220C‧‧‧transmitter selection module

320A, 320B, 320C, 320D, 320E‧‧‧ Receiver selection module

230A, 240A, 230B, 240B, 230C, 240C‧‧‧ Output Driver Module

311~314‧‧‧Terminal impedance matching module

330A, 330B, 331C, 332C, 330D, 330E‧‧‧ level adjustment module

340A, 340B, 340C, 331D, 332D, 340D, 341E, 342E‧‧‧ Variable Gain Adjustment Module

331B, 332B, 331E, 332E‧‧‧ level adjusters

348, 349‧‧‧variable resistance unit

Figure 1 is a schematic diagram of the operating system of the author.

2A~2C are diagrams of possible embodiments of the transmitting unit of the present invention.

Figures 3A-3E are possible embodiments of the receiving unit of the present invention.

Figure 1 is a schematic diagram of the operating system of the author. As shown, the operating system 100 includes an external device 110, a USB chipset 120, and a host device 130. The external device 110 receives information from the host device 130 or provides information to the host device 130 via the USB chipset 120. Similarly, the host device 130 also receives information from the external device 110 or provides information to the external device 110 via the USB chipset 120. In the embodiment of Fig. 1, the USB chip set 120 is located in the host device 130, but is not limited thereto. The USB chipset 120 can also be located in an external device 110 (not shown).

This creation does not limit the type of USB chip 120. In one possible embodiment, the USB chipset 120 is a USB 3.0 or USB 3.1 chipset. As shown, the chip set 120 has pin groups P ₁ -P ₅ for coupling to the external device 110. The pin group P ₁ includes pins TXP1 and TXN1 for transmitting an output signal to the external device 110. The pin set P ₂ includes pins TXP2 and TXN2 for transmitting an output signal to the external device 110. Pin set P ₃ includes pins CC1, CC2. The pin set P ₄ includes pins RXP1 and RXN1 for receiving an input signal from the external device 110. The pin set P ₅ includes pins RXP2 and RXN2 for receiving an input signal from the external device 110.

In this embodiment, the chipset 120 includes a data processing unit 121, a transmitting unit 122, a receiving unit 123, and a detecting unit 124. The data processing unit 121 generates a plurality of transmission information ST according to a piece of information provided by the host device 130. The transmitting unit 122 converts the transmission information ST for generating an output signal and transmits it to the external device 110 through the pin group P ₁ or P ₂ . In a possible embodiment, the transmitting unit 122 has a demultiplexer (not shown) for transmitting an output signal to the external device 110 through the pin group P ₁ or P ₂ .

The receiving unit 123 receives an input signal provided by the external device 110 through the pin group P ₄ or P ₅ and processes the input signal to generate a processing signal SR. The data processing unit 121 generates corresponding reception information to the host device 130 based on the processing signal SR. In a possible embodiment, the receiving unit 123 has a multiplexer (not shown) for receiving input signals from the pin set P ₄ or P ₅ .

The detecting unit 124 detects the voltage level of the pin group P ₃ for controlling the demultiplexer of the transmitting unit 122 and the multiplexer of the receiving unit 123. In the present embodiment, the transmission unit 122 according to the detection signal S _D 124 produced by the detecting unit, selecting and pin _{set. 1} P ₂ P sends one of the output signal. The receiving unit 123 selects one of the pin groups P ₄ and P ₅ to receive an input signal provided by the external device 110 according to the detection signal S _D .

FIG. 2A is a possible embodiment of the transmitting unit 122. In this embodiment, the sending unit 200A includes a conversion module 210A, a transmitter selection module 220A, and output driver modules 230A and 240A. The conversion module 210A receives the plurality of pieces of transmission information ST in parallel, and outputs the transmission information ST in a differential manner. In a possible embodiment, the conversion module 210A is a serializer.

The transmitting end selection module 220A provides the output of the conversion module 210A to the output driving module 230A or 240A according to the detection signal S _D . In a possible embodiment, the transmitter selection module 220A is a demultiplexer, but is not intended to limit the creation. In other embodiments, the emitter selection module 220A is comprised of a transistor or a switch.

When the transmitting end selection module 220A provides the output of the conversion module 210A to the output driving module 230A, the output driving module 230A increases the driving capability of the output information of the conversion module 210A to generate an enhanced signal SE ₁ , and enhanced signal SE ₁ through the output pin group P _1. Similarly, when the transmitting terminal selection module 220A provides the output of the conversion module 210A to the output driving module 240A, the output driving module 240A increases the driving capability of the output information of the conversion module 210A to generate an enhanced signal SE. _2, and the enhanced signal SE ₂ P ₂ through the output pin set.

Figure 2B is another possible embodiment of the transmitting unit of the present creation. Figure 2B is similar to Figure 2A, except that Figure 2B has a pre-driver 250B. The pre-drive module 250B is coupled to the transmitter selection module 220B is between the conversion module 210B. The pre-driver module 250B increases the driving capability of the output signal of the conversion module 210B to generate an enhanced signal SE. In a possible embodiment, the enhanced signal SE is a differential signal. Since the operation principle of the conversion module 210B is similar to that of the conversion module 210A, it will not be described again.

The transmitting end selection module 220B provides the enhanced signal SE to the output driving module 230B or 240B according to the detection signal S _D . When the transmitting end selection module 220B supplies the enhanced signal SE to the output driving module 230B, the output driving module 230B further increases the driving capability of the enhanced signal SE to generate an enhanced signal SE ₃ and transmits the enhanced signal SE ₃ through the pin group P _{1 .} The enhancement signal SE _{3 is} output. Similarly, when the transmitting end selection module 220B supplies the enhanced signal SE to the output driving module 240B, the output driving module 240B increases the driving capability of the enhanced signal SE to generate an enhanced signal SE ₄ and transmits the enhanced signal SE ₄ P ₂ outputs an enhancement signal SE ₄ .

Figure 2C is another possible embodiment of the transmitting unit of the present invention. The transmitting end selection module 220C is coupled between the conversion module 210C and the pre-drive modules 250 and 260. Since the operation principle of the conversion module 210C is similar to that of the conversion module 210A, it will not be described again. In this embodiment, the transmitting end selection module 220C provides the output of the conversion module 210C to the pre-drive module 250 or 260 according to the detection signal S _D . In a possible embodiment, the transmitter selection module 220C is a demultiplexer.

When the pre-drive module 250 receives the output of the conversion module 210C, the driving capability of the output signal of the conversion module 210C is increased to generate an enhancement signal SE ₅ . The output driving module 230C further boosts the driving capability of the enhanced signal SE ₅ to generate the enhanced signal SE ₇ and provides the enhanced signal SE ₇ to the external device 110 through the pin group P ₁ . Similarly, when the pre-drive module 260 receives the output of the conversion module 210C, the driving capability of the output signal of the conversion module 210C is increased to generate an enhancement signal SE ₆ . The output driving module 240C further boosts the driving capability of the enhanced signal SE ₆ to generate the enhanced signal SE ₈ and provides the enhanced signal SE ₈ to the external device 110 through the pin group P ₂ .

The 3A~3D diagram is a possible embodiment of the receiving unit of the present creation. In FIG. 3A, the receiving unit 300A includes a terminal impedance matching module 311-314, a receiving end selecting module 320A, a quasi-adjusting module 330A, and a variable gain tuning module 340A. . The terminal impedance matching modules 311-314 are disposed before the receiving end selection module 320A, and are respectively coupled to the pins RXP1, RXN1, RXP2, and RXN2 for matching the impedances of the pins RXP1, RXN1, RXP2, and RXN2.

The receiving end selection module 320A transmits the signal on the pin group P ₄ or P ₅ as an input signal SI to the level adjusting module 330A according to the detecting signal S _D . In a possible embodiment, the receiving end selection module 320A is a multiplexer, but is not intended to limit the creation. In other embodiments, the receiving end selection module 320A is comprised of a transistor.

The level adjustment module 330A is configured to adjust the voltage level of the common mode of the input signal SI. In a possible embodiment, the level adjustment module 330A is a high pass filter or a level shifter. The variable gain adjustment module 340A adjusts the output of the level adjustment module 330A for generating the processing signal SR to the data processing unit 121. In a possible embodiment, the processed signal SR is a differential signal. In a possible embodiment, the variable gain adjustment module 340A can be an equalizer or a variable gain amplifier, but is not intended to limit the creation.

Figure 3B is another possible embodiment of the receiving unit of the present invention. FIG. 3B is similar to FIG. 3A except that the receiving end selection module 320B of FIG. 3B is coupled between the level adjusting module 330B and the variable gain adjusting module 340B. In this embodiment, the level adjustment module 330B has level adjusters 331B and 332B.

The level adjuster 331B is coupled to the pin group P ₄ and adjusts the common mode voltage level of the signal on the pin group P ₄ to generate a differential signal SD ₁ . The level adjuster 332B is coupled to the pin group P ₅ and adjusts the common mode voltage level of the signal on the pin group P ₅ to generate a differential signal SD ₂ . The receiving end selection module 320B provides the differential signal SD ₁ or SD ₂ to the variable gain adjustment module 340B according to the detection signal S _D . In a possible embodiment, the receiving end selection module 320B is a multiplexer. The variable gain adjustment module 340B adjusts the output of the receiver selection module 320B to generate a processing signal SR.

In FIG. 3C, the receiving unit 300C includes a plurality of terminal impedance matching modules 311 to 314, level adjusting modules 331C and 332C, a receiving end selecting module 320C, and a variable gain adjusting module 340C. The level adjustment module 331C is coupled to the pin group P ₄ and adjusts the common mode voltage level of the signal on the pin group P ₄ according to a set value SS ₁ to generate a differential signal SD ₁ . The level adjustment module 332C is coupled to the pin group P ₅ and adjusts the common mode voltage level of the signal on the pin group P ₅ according to a set value SS ₂ to generate a differential signal SD ₂ . In one possible embodiment, the level adjustment modules 331C and 332C use the set values SS ₁ and SS ₂ as the common mode voltages of the differential signals SD ₁ and SD ₂ .

The variable gain adjustment module 340C adjusts the output of the level adjustment module 331C or 332C for generating the processing signal SR. In one possible example, the variable gain adjustment module 340C according to the level of the common mode voltage differential signal SD SD ₁ and _2, the decision whether to adjust the differential signal SD ₁ and SD _2. Taking the differential signal SD ₁ as an example, when the level of the common mode voltage of the differential signal SD ₁ is equal to a predetermined value, the variable gain adjustment module 340C does not adjust the differential signal SD ₁ . Conversely, when the level of the common mode voltage of the differential signal SD ₁ is not equal to the preset value, the variable gain adjustment module 340C adjusts the differential signal SD ₁ .

In this embodiment, the variable gain adjustment module 340C includes current conversion voltage modules 341, 344, differential pairs 342, 345, variable resistance units 348, 349, and current modules 343, 346, but is not intended to be limiting. This creation. As shown, the current conversion voltage module 341, the differential pair 342, and the current module 343 are connected in series between the operating voltages V _OP1 and V _OP2 . The current module 343 is configured to provide at least two fixed currents. The differential pair 342 processes the differential signal SD ₁ according to the current generated by the current module 343 for generating a differential current output. The current conversion voltage module 341 generates a first differential voltage as the processing signal SR according to the differential current output generated by the differential pair 342. The variable resistance unit 348 is coupled between the differential pair 342 and the current module 343, and changes its resistance value according to the frequency of the output signal of the differential pair 342. In one embodiment, current module 343 includes two sets of current sources. One end of each current source is coupled to the differential pair 342, and the other end receives the operating voltage V _OP2 . In a possible embodiment, the operating voltage V _OP2 is a ground voltage.

Similarly, the current conversion voltage module 344, the differential pair 345, and the current module 346 are connected in series between the operating voltages V _OP1 and V _OP2 . The current module 346 is configured to provide at least two fixed currents. The differential pair 345 processes the differential signal SD ₂ according to the current generated by the current module 346 for generating a differential current output. The current conversion voltage module 344 generates a second differential voltage as the processing signal SR according to the differential current output generated by the differential pair 345. The variable resistance unit 349 is coupled between the differential pair 345 and the current module 346, and changes its resistance value according to the frequency of the output signal of the differential pair 345. The variable resistance units 348, 349 can be implemented by other active components or passive components. In an embodiment, the current module 346 includes two sets of current sources. One end of each current source is coupled to the differential pair 345, and the other end receives the operating voltage V _OP2 . In a possible embodiment, the operating voltage V _OP2 is a ground voltage.

The receiving end selection module 320C provides the set values SS ₁ and SS ₂ to the level adjusting modules 331C and 332C according to the detecting signal S _{D for} indirectly not starting the differential pair 342 or 345. In the present embodiment, the receiving end selection module 320C uses one of the voltages V1 and V2 as the set value SS ₁ and the other of the voltages V1 and V2 as the set value SS ₂ according to the detection signal S _D . In a possible embodiment, the receiving end selection module 320C is a multiplexer.

In the 3D diagram, the receiving end selection module 320D is disposed in the variable gain adjustment module 340D. Since the characteristics of the level conversion module 330D in the 3D drawing are similar to those of the level conversion module 330B in FIG. 3B, they will not be described again.

In this embodiment, the variable gain adjustment module 340D includes current conversion voltage modules 341, 344, differential pairs 342, 345, variable resistance units 348, 349, current modules 343 and 346, and a receiving end selection mode. Group 320D. The current conversion voltage module 341, the receiving end selection module 320D, the differential pair 342 and the current module 343 are connected in series between the operating voltages V _OP1 and V _OP2 for performing gain variation on the differential signal SD ₁ . The differential pair 342 processes the differential signal SD ₁ . The current module 343 is coupled between the differential pair 342 and the operating voltage V _OP2 . The current conversion voltage module 341 is coupled between the operating voltage V _OP1 and the selection module 320D.

The receiving end selection module 320D turns on the path between the current conversion voltage module 341 and the differential pair 342 or turns on the path between the current conversion voltage module 344 and the differential pair 345 according to the detection signal S _D . When the path between the current conversion voltage module 341 and the differential pair 342 is turned on, the current conversion voltage module 341 converts the output signal of the differential pair 342 into a voltage format from the current format for generating the processing signal SR. The variable resistance unit 348 is coupled between the differential pair 342 and the current module 343, and changes its resistance value according to the frequency of the output signal of the differential pair 342. In one embodiment, current module 343 includes two sets of current sources. One end of each current source is coupled to the differential pair 342, and the other end receives the operating voltage V _OP2 . In a possible embodiment, the operating voltage V _OP2 is a ground voltage. Similarly, the current conversion voltage module 344, the receiving end selection module 320D, the differential pair 345 and the current module 346 are connected in series between the operating voltages V _OP1 and V _OP2 for performing gain variation on the differential signal SD ₂ . The differential pair 345 processes the differential signal SD ₂ . The current module 346 is coupled between the differential pair 345 and the operating voltage V _OP2 . The current conversion voltage module 344 is coupled between the operating voltage V _OP1 and the receiving end selection module 320D. When the path between the current conversion voltage module 344 and the differential pair 345 is turned on, the current conversion voltage module 344 converts the output signal of the differential pair 345 into a voltage format from the current format for generating the processing signal SR. The variable resistance unit 349 is coupled between the differential pair 345 and the current module 346, which changes its resistance value with the frequency of the output signal of the differential pair 345. The variable resistance units 348, 349 can be implemented by active or passive components. In an embodiment, the current module 346 includes two sets of current sources. One end of each current source is coupled to the differential pair 345, and the other end receives the operating voltage V _OP2 . In a possible embodiment, the operating voltage V _OP2 is a ground voltage.

In this embodiment, the receiving end selection module 320D is used to turn on the path between the current conversion voltage module 341 and the differential pair 342 or the path between the current conversion voltage module 344 and the differential pair 345, but not Used to limit this creation. In other embodiments, the receiving end selection module 320D is used to turn on the path between the differential pair 342 and the current module 343 or the path between the differential pair 345 and the current module 346. In other embodiments, the receiving end selection module 320D is configured to turn on a path between the current conversion voltage module 341 and the operating voltage V _OP1 or a path between the current converting voltage module 344 and the operating voltage V _OP1 . In other embodiments, the receiving end selection module 320D is configured to turn on a path between the current module 343 and the operating voltage V _OP2 or a path between the current module 346 and the operating voltage V _OP2 .

Figure 3E is another possible embodiment of the receiving unit of the present creation. In the embodiment, the receiving end selection module 320E is disposed between the variable gain amplifying modules 341E and 342E and the data processing unit 121. As shown, the level conversion module 330E has level converters 331E and 332E for adjusting the level of the common mode voltage of the signals on the pin groups P ₄ and P ₅ , respectively, and adjusting the adjusted differential signals. The variable gain adjustment modules 341E and 342E are provided separately.

The variable gain adjustment modules 341E and 342E perform gain change adjustment on the output signals of the level shifters 331E and 332E, respectively. The receiving end selection module 320E uses the output signal of the variable gain adjustment module 341E or 342E as the processing signal SR according to the detection signal S _D . In a possible embodiment, the receiving end selection module 320E is a multiplexer.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary language of the art to which this invention belongs. Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached.

100‧‧‧ operating system

110‧‧‧External devices

120‧‧‧USB chipset

130‧‧‧Host device

P ₁ ~P ₅ ‧‧‧ Pin set

121‧‧‧Data Processing Unit

122‧‧‧Send unit

123‧‧‧ Receiving unit

124‧‧‧Detection unit

SR‧‧‧Processing signals

ST‧‧‧Transfer information

S _D ‧‧‧Detection signal

TXP1, TXN1, TXP2, TXN2, CC1, CC2, RXP1, RXN1, RXP2, RXN2‧‧‧ pins

Claims (20)

A USB chipset is coupled between a first device and a second device, and includes: a data processing unit coupled to the first device, and generating a plurality of first information according to the first device Transmitting information; a transmitting unit coupled to the data processing unit for providing the transmission information to the second device, and comprising: a conversion module coupled to the data processing unit for receiving the transmissions in parallel Information, and outputting the transmission information in series; a first output driving module coupled to a first pin group; a second output driving module coupled to a second pin group; and a transmitting end The selection module is coupled between the conversion module and the first and second output driving modules. The USB chipset of claim 1 further includes a pre-driver module coupled between the conversion module and the transmitter selection module, and adding an output signal of the conversion module. To generate an enhanced signal, the transmitting end selection module provides the enhanced signal to the first or second output driving module. The USB chipset of claim 1, further comprising: a first pre-drive module coupled between the transmitter selection module and the first output driver module; and a second pre- The driving module is coupled between the transmitting end selection module and the second output driving module, and the transmitting end selecting module provides the output signal of the conversion module to the first or second pre-driving module . The USB chipset of claim 1, wherein the transmitter selection module is a demultiplexer. The USB chipset of claim 1 further includes a detecting unit that generates a detection signal according to a voltage level of the third pin group, and the transmitting terminal selecting module is configured according to the detecting signal. And selectively transmitting a signal to the first or second output driving module. The USB chipset as described in claim 1 further includes a detecting unit that generates a detection signal according to a voltage level of a third pin group. The USB chipset of claim 6, further comprising: a receiving unit, comprising: a receiving end selection module coupled to a fourth pin group and a fifth pin group for The detection signal selectively outputs a signal on the fourth or fifth pin group; and a quasi-adjustment module is configured to adjust a common mode voltage level of an output signal of the receiving end selection module. The USB chipset of claim 7, wherein the level adjustment module is a high pass filter. The USB chipset of claim 6, further comprising: a receiving unit, comprising: a quasi-adjusting module coupled to a fourth pin group and a fifth pin group, and adjusting the a common mode voltage level of the signals on the fourth and fifth pin groups for generating a first differential signal and a second differential signal; and a receiving end selection module for selectively selecting according to the detection signal The first or second differential signal is provided to a variable gain adjustment module. The USB chipset of claim 6, further comprising: a receiving unit, comprising: a first level adjusting module coupled to a fourth pin set, and adjusting the first set value according to a first set value The common mode voltage level of the signal on the fourth pin group is used to generate a first differential signal; a second level adjustment module is coupled to a fifth pin group, and according to a second set value Adjusting a common mode voltage level of the signal on the fifth pin group to generate a second differential signal; and a receiving end selection module coupled to the first and second level adjustment modules, And providing the first and second set values to the first and second level adjustment modules according to the detection signal. The USB chipset of claim 10, further comprising: a variable gain adjustment module coupled to the first and second level adjustment modules, when the common differential voltage of the first differential signal When the level is equal to a preset value, the variable gain adjustment module does not adjust the first differential signal, and when the common mode voltage level of the first differential signal is not equal to the preset value, the variable gain The adjustment module adjusts the first differential signal. The USB chipset of claim 6, further comprising: a receiving unit, comprising: a quasi-adjusting module coupled to a fourth pin group and a fifth pin group, and adjusting the a common mode voltage level of the signals on the fourth and fifth pin groups for generating a first differential signal and a second differential signal; and a variable gain adjustment module for selectively adjusting the first Or a second differential signal. The USB chipset of claim 12, wherein the variable gain adjustment module comprises: a first differential pair coupled to the level adjustment module for receiving and processing the first differential And generating a first output signal group; a first current module coupled between the first differential pair and a first operating voltage; a first variable resistance unit coupled to the first difference And the first current conversion voltage module is coupled between a second operating voltage and a receiving end selection module, and converts the first output signal group to generate a a first processing signal; a second differential pair coupled to the level adjustment module for receiving the second differential signal and generating a second output signal group; a second current module coupled to Between the second differential pair and the first operating voltage; a second variable resistor unit coupled to the second differential pair and the second current module; and a second current converting voltage module coupled Connected between the second operating voltage and the receiving terminal selection module, and converts the second output signal The receiving end selection module is configured to selectively cause the first current conversion voltage module to convert the first output signal group according to the detection signal or to enable the first The two current conversion voltage modules convert the second output signal group. Such as the USB chipset described in claim 13 of the patent scope, wherein the data processing The unit generates a receiving information to the second device according to the first or second processing signal. The USB chipset of claim 6, further comprising: a receiving unit, comprising: a quasi-adjusting module coupled to a fourth pin group and a fifth pin group, and adjusting the The common mode voltage level of the signals on the fourth and fifth pin groups is used to generate a first differential signal and a second differential signal; the complex variable gain adjustment module adjusts the first and second differences The motion signal is used to generate a first processing signal and a second processing signal; and a receiving end selection module is configured to selectively transmit the first or second processing signal to the data processing unit according to the detection signal. The USB chipset of claim 15, wherein the data processing unit generates a receiving information to the second device based on the first or second processing signal. A USB chipset, comprising: a data processing unit, generating a plurality of transmission information according to a first information provided by a first device; and a transmitting unit processing the transmission information for generating an output signal; a set of feet for transmitting the output signal to a second device; and a second set of pins for transmitting the output signal to the second device. The USB chipset of claim 17, further comprising: a third pin set coupled to the second device; and a detecting unit for detecting a voltage level of the third pin set, For generating a detection signal, wherein the transmitting unit transmits the first signal according to the detection signal Or the second pin group sends the output signal. The USB chipset of claim 18, further comprising: a fourth pin set coupled to the second device for receiving a first input signal; a fifth pin set coupled to the a second device for receiving a second input signal; and a receiving unit that processes the first or second input signal according to the detection signal and provides the processing result to the data processing unit. The USB chip set of claim 19, wherein the transmitting unit has a demultiplexer, the receiving unit having a multiplexer.