TWM514108U - Chip conducting member - Google Patents

Chip conducting member Download PDF

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Publication number
TWM514108U
TWM514108U TW104213755U TW104213755U TWM514108U TW M514108 U TWM514108 U TW M514108U TW 104213755 U TW104213755 U TW 104213755U TW 104213755 U TW104213755 U TW 104213755U TW M514108 U TWM514108 U TW M514108U
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Taiwan
Prior art keywords
wafer
body portion
wafer via
electrode
signal transmission
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Application number
TW104213755U
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Chinese (zh)
Inventor
Ching-Tien Chao
Meng-Hui Lin
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Advanced Power Electronics Corp
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Priority to TW104213755U priority Critical patent/TWM514108U/en
Priority to CN201520654968.6U priority patent/CN204857710U/en
Publication of TWM514108U publication Critical patent/TWM514108U/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

晶片導通件Wafer via

本新型係關於一種晶片導通件，尤其係關於一種電性連接於晶片與一外部電性接點的晶片導通件。The present invention relates to a wafer via, and more particularly to a wafer via electrically connected to a wafer and an external electrical contact.

晶片的封裝結構對於其效能來說至關重要。一般來說，晶粒自晶圓切割下來之後需要對其進行封裝製程，以保護晶片免於各種物理損壞或化學腐蝕。同時更設置對應的引腳，以讓使用者可以便利地藉由封裝結構來使用晶片或對其進行測詴。The package structure of the wafer is critical to its performance. Generally, after the die is cut from the wafer, it needs to be packaged to protect the wafer from various physical or chemical corrosion. At the same time, the corresponding pins are set to allow the user to conveniently use or measure the wafer by the package structure.

目前較常見的作法係將晶粒設置於一基座上後，再以打線的方式佈線於晶粒於基座上，讓導線連接於晶粒的電極與基座的電性接點之間。但是由於導線的線寬有其限制，使得以導線形成之傳輸結構的阻抗偏大，而無法降低傳輸損耗。At present, the more common method is to place the die on a pedestal, and then wire the wire on the pedestal, and connect the wire between the electrode of the die and the electrical contact of the pedestal. However, since the line width of the wire has a limitation, the impedance of the transmission structure formed by the wire is too large, and the transmission loss cannot be reduced.

鑑於上述，本新型旨在揭露一種晶片導通件以取代以往用導線連接於晶片電極與外部接點之間的作法。In view of the above, the present invention is directed to a wafer via that replaces conventional bonding between a wafer electrode and an external contact.

本新型提供了一種晶片導通件。所述的晶片導通件用以連接於晶片的第一電極與至少一外部電性接點之間。晶片導通件包含本體部、訊號傳輸部與連接部。本體部具有第一電極接觸面與至少一貫孔。第一電極接觸面用以覆蓋至少部分的第一電極。訊號傳輸部連接本體部。至少一連接部連接訊號傳輸部，用以連接至少一外部電性接點。其中本體部、訊號傳輸部與至少一連接部共同形成上表面，而上表面相對於第一電極接觸面。The present invention provides a wafer via. The wafer via is connected between the first electrode of the wafer and the at least one external electrical contact. The wafer via member includes a body portion, a signal transmission portion, and a connection portion. The body portion has a first electrode contact surface and at least a consistent aperture. The first electrode contact surface is for covering at least a portion of the first electrode. The signal transmission unit is connected to the body portion. At least one connecting portion is connected to the signal transmitting portion for connecting at least one external electrical contact. The main body portion, the signal transmission portion and the at least one connecting portion together form an upper surface, and the upper surface is in contact with the first electrode.

在本新型的一實施例中，第一電極接觸面具有第一溝槽，而至少一貫孔暴露於第一溝槽。而當晶片導通件設置於晶片上時，晶片導通件覆蓋第一電極但暴露出晶片的第二電極。且訊號傳輸部具有傾斜段，傾斜段的延伸軸向與本體部的延伸平面夾有夾角。傾斜段的側邊連接至少一連接部。此外，訊號傳輸部更具有第二溝槽。同時晶片導通件具有多個連接部，所述的多個連接部用以分別耦接至少一外部電性接點。並且，晶片導通件更包含多個定位部，定位部用以連接容置架中的容置框。In an embodiment of the invention, the first electrode contact surface has a first trench and at least a consistent aperture is exposed to the first trench. When the wafer via is disposed on the wafer, the wafer via covers the first electrode but exposes the second electrode of the wafer. And the signal transmission portion has an inclined section, and the extending axial direction of the inclined section is at an angle with the extending plane of the body portion. The side of the inclined section is connected to at least one connecting portion. In addition, the signal transmission portion further has a second groove. The plurality of connecting portions are respectively coupled to the at least one external electrical contact. Moreover, the wafer conducting member further comprises a plurality of positioning portions, and the positioning portion is configured to connect the receiving frame in the receiving frame.

綜上所述，本新型提供了一種晶片導通件。晶片導通件係以本體部電性連接晶片的電極，且以至少一連接部電性連接外部的電性接點。因此，相較於以往用佈線連接晶片電極與外部電性接點的方式，本新型所提供之晶片導通件大幅降低了晶片電極與外部電性接點之間的傳輸阻抗。此外，晶片導通件能連接於容置框架，而得以讓廠商更有效率地組裝晶片導通件於晶片電極及外部電性接點，進而改善了封裝製程。In summary, the present invention provides a wafer via. The wafer conductive member electrically connects the electrodes of the wafer with the body portion, and electrically connects the external electrical contacts with the at least one connecting portion. Therefore, the wafer via member provided by the present invention greatly reduces the transmission impedance between the wafer electrode and the external electrical contact compared to the conventional method of connecting the wafer electrode to the external electrical contact by wiring. In addition, the wafer vias can be connected to the receiving frame, which allows the manufacturer to more efficiently assemble the wafer vias to the wafer electrodes and external electrical contacts, thereby improving the packaging process.

以上關於本新型的內容及以下關於實施方式的說明係用以示範與闡明本新型的精神與原理，並提供對本新型的申請專利範圍更進一步的解釋。。The above description of the present invention and the following description of the embodiments are intended to illustrate and clarify the spirit and principles of the present invention and to provide a further explanation of the scope of the present invention. .

以下在實施方式中敘述本新型之詳細特徵，其內容足以使任何熟習相關技藝者瞭解本新型之技術內容並據以實施，且依據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本新型相關之目的及優點。以下實施例係進一步說明本新型之諸面向，但非以任何面向限制本新型之範疇。The detailed features of the present invention are described in the following embodiments, which are sufficient for any person skilled in the art to understand the technical contents of the present invention and implement it according to the content, the scope of the patent application and the drawings. The related objects and advantages of the present invention can be easily understood by those skilled in the art. The following examples are intended to further illustrate the aspects of the present invention, but are not intended to limit the scope of the present invention.

請一併參照圖1A至圖1D，圖1A係本新型一實施例中晶片導通件相對於外部電性接點的爆炸示意圖，圖1B係本新型圖1A中晶片導通件的立體示意圖，圖1C係本新型圖1A中晶片導通件的俯視示意圖，圖1D係本新型圖1A中晶片導通件的仰視示意圖。1A to FIG. 1D, FIG. 1A is a schematic view showing the explosion of the wafer conduction member with respect to the external electrical contact in the embodiment of the present invention, and FIG. 1B is a perspective view of the wafer conduction member of the novel FIG. 1A, FIG. 1C. A schematic top view of the wafer via in the novel FIG. 1A, and FIG. 1D is a bottom view of the wafer via of the novel FIG. 1A.

在圖1A中繪示有晶片導通件1、晶片2與一外部電性接點3。如圖1A所示，晶片導通件1用以電性連接於晶片2與外部電性接點3之間。其中晶片2具有第一電極22與第二電極24。外部電性接點3例如為晶片封裝製程所使用之導線架上的電性接點，但並不以此為限。A wafer via 1, a wafer 2 and an external electrical contact 3 are shown in FIG. 1A. As shown in FIG. 1A, the wafer via 1 is electrically connected between the wafer 2 and the external electrical contact 3. The wafer 2 has a first electrode 22 and a second electrode 24. The external electrical contact 3 is, for example, an electrical contact on the lead frame used in the chip packaging process, but is not limited thereto.

如圖1A至圖1D所示，晶片導通件1具有本體部12、訊號傳輸部14、連接部16a、16b與定位部18a、18b、18c。為方便後續行文說明，本體部12係定義有第一側邊S1、第二側邊S2與第五側邊S5，而訊號傳輸部14定義有第三側邊S3、第四側邊S4與第六側邊S6。其中第一側邊S1更定義有第一段S11與第二段S12，而第四側邊S4定義有第一段S41與第二段S42。其中，第一側邊S1之長度的第一段S11為第五側邊S5之長度的百分之六十四。第二側邊S2之長度約為第五側邊S5之長度的百分之八十三。第三側邊S3之長度約為第五側邊之長度的百分之二十二。第四側邊S4的第一段S41之長度約等於第二段S42之長度。上述僅為一示範例，實際上各側邊的長度比例並不以此為限。As shown in FIGS. 1A to 1D, the wafer via 1 has a body portion 12, a signal transmission portion 14, connection portions 16a, 16b, and positioning portions 18a, 18b, 18c. For convenience of the following description, the main body portion 12 defines a first side S1, a second side S2 and a fifth side S5, and the signal transmitting portion 14 defines a third side S3, a fourth side S4 and a Six sides S6. The first side S1 is further defined with a first segment S11 and a second segment S12, and the fourth side S4 is defined with a first segment S41 and a second segment S42. The first segment S11 of the length of the first side S1 is sixty-four percent of the length of the fifth side S5. The length of the second side S2 is about eighty-three percent of the length of the fifth side S5. The length of the third side S3 is about twenty-two percent of the length of the fifth side. The length of the first segment S41 of the fourth side S4 is approximately equal to the length of the second segment S42. The above is only an example, and the length ratio of each side is not limited thereto.

訊號傳輸部14連接於本體部12與連接部16a、16b之間。連接部16a、16b係自訊號傳輸部14的第六側邊S6延伸而出。定位部18a係位於連接部16a、16b之間，定位部18b、18c係分別位於本體部12的第一側邊S1與第二側邊S2。然在其他實施例中，定位部18b、18c也可以位於第五側邊S5上，定位部18a也不必然位於連接部16a、16b之間。本體部12、訊號傳輸部14與連接部16a、16b共同形成上表面P1。上述僅為舉例示範，實際上晶片導通件1的各部件的相對位置並不以此為限。The signal transmission unit 14 is connected between the main body portion 12 and the connection portions 16a and 16b. The connecting portions 16a and 16b extend from the sixth side S6 of the signal transmitting portion 14. The positioning portion 18a is located between the connecting portions 16a and 16b, and the positioning portions 18b and 18c are respectively located at the first side S1 and the second side S2 of the body portion 12. However, in other embodiments, the positioning portions 18b, 18c may also be located on the fifth side S5, and the positioning portion 18a is not necessarily located between the connecting portions 16a, 16b. The main body portion 12 and the signal transmission portion 14 together with the connection portions 16a and 16b form an upper surface P1. The above is merely an example, and the relative positions of the components of the wafer via 1 are not limited thereto.

如圖1A所示，本體部12用以覆蓋並電性連接至少部分的第一電極22。更詳細地來說，本體部12具有第一電極接觸面P2。第一電極接觸面P2係相對於上表面P1。本體部12以第一電極接觸面P2電性連接晶片2的第一電極22，且以第一電極接觸面P2覆蓋至少部分的第一電極22，藉以增大耦接面積並降低傳輸阻抗。第一電極接觸面P2例如為晶片導通件1的完整底面或者是部份的底面。As shown in FIG. 1A, the body portion 12 is used to cover and electrically connect at least a portion of the first electrode 22. In more detail, the body portion 12 has a first electrode contact surface P2. The first electrode contact surface P2 is opposed to the upper surface P1. The body portion 12 is electrically connected to the first electrode 22 of the wafer 2 with the first electrode contact surface P2, and covers at least a portion of the first electrode 22 with the first electrode contact surface P2, thereby increasing the coupling area and reducing the transmission impedance. The first electrode contact surface P2 is, for example, a complete bottom surface of the wafer via 1 or a partial bottom surface.

本體部12還具有貫孔124a、124b，而第一電極接觸面P2上設置有一第一溝槽126。貫孔124a、124b暴露於第一溝槽126與上表面P1。由於在實務上，晶片導通件1係例如以導電膠加熱固定於晶片2上。而在加熱過程當中，導電膠會受熱而產生揮發氣體。貫孔124a、124b與第一溝槽126即是用來提供氣體流道以散發這些揮發氣體。另一方面，貫孔124a、124b與第一溝槽126更可暴露晶片導通件1的內部底部，藉此增加散熱面積並提高散熱效果。在本實施例中，第一溝槽126係暴露於第一側邊S1與第二側邊S2。在另一實施例中，第一溝槽126係暴露於第一側邊S1與第五側邊S5。在更一實施例中，第一溝槽126係僅暴露於第一側邊S1。此外，如圖所示，第一溝槽126的長度約等於第五側邊S5的長度，第一溝槽126的寬度則約為第五側邊S5之長度的百分之十二點五。貫孔124a、124b的形狀類似於一橢圓形，其長軸之長度相當於第一溝槽126的長度，而其短軸之長度約為第一溝槽126的寬度。上述僅為舉例說明，但並不以此為限。The body portion 12 further has through holes 124a, 124b, and the first electrode contact surface P2 is provided with a first groove 126. The through holes 124a, 124b are exposed to the first groove 126 and the upper surface P1. Since in practice, the wafer via 1 is thermally fixed to the wafer 2, for example, with a conductive paste. During the heating process, the conductive paste is heated to generate volatile gases. The through holes 124a, 124b and the first groove 126 are used to provide a gas flow path to dissipate these volatile gases. On the other hand, the through holes 124a, 124b and the first groove 126 may expose the inner bottom of the wafer via 1 , thereby increasing the heat dissipation area and improving the heat dissipation effect. In the present embodiment, the first trench 126 is exposed to the first side S1 and the second side S2. In another embodiment, the first trench 126 is exposed to the first side S1 and the fifth side S5. In a further embodiment, the first trench 126 is only exposed to the first side S1. Further, as shown, the length of the first trench 126 is approximately equal to the length of the fifth side S5, and the width of the first trench 126 is approximately 12.5% of the length of the fifth side S5. The shape of the through holes 124a, 124b is similar to an elliptical shape, the length of the major axis being equivalent to the length of the first groove 126, and the length of the minor axis being about the width of the first groove 126. The above is only an example, but is not limited thereto.

訊號傳輸部14電性連接於本體部12與連接部16a、16b之間，用以橋接本體部12與連接部16a、16b。訊號傳輸部14的材質例如為銅、銀、金等導體，但並不以此為限制。在此實施例中，訊號傳輸部14具有第二溝槽142。第二溝槽142係配合外部電性接點3所在之結構體的起伏而設置，此外第二溝槽142也用以增加散熱面積而能提高散熱效果。在此實施例中，第二溝槽142露出於第三側邊S3與第四側邊S4。換句話說，第二溝槽142的寬度約為第五側邊S5的百分之十七，第二溝槽142的長度約為第五側邊S5的長度。上述僅為舉例示範，實際上並不對第二溝槽142與各側邊的相對關係加以限制。The signal transmitting portion 14 is electrically connected between the main body portion 12 and the connecting portions 16a and 16b for bridging the main body portion 12 and the connecting portions 16a and 16b. The material of the signal transmission unit 14 is, for example, a conductor such as copper, silver or gold, but is not limited thereto. In this embodiment, the signal transmission portion 14 has a second groove 142. The second trench 142 is disposed to match the undulation of the structure in which the external electrical contact 3 is located. In addition, the second trench 142 is also used to increase the heat dissipation area to improve the heat dissipation effect. In this embodiment, the second groove 142 is exposed on the third side S3 and the fourth side S4. In other words, the width of the second groove 142 is about 17% of the fifth side S5, and the length of the second groove 142 is about the length of the fifth side S5. The above is merely an example and does not actually limit the relative relationship between the second groove 142 and each side.

連接部16a、16b用以電性連接外部電性接點3。更詳細地來說，連接部16a、16b分別以各自的接觸面電性連接外部電性接點3，因而提高了耦接面積，降低了傳輸阻抗。此外，連接部16a、16b係彼此分離，以提高所能承受的應力。更詳細地來說，連接部16a、16b的長度例如約為第六側邊S6的百分之四十，連接部16a、16b的寬度例如約為第六側邊S6的百分之六，而連接部16a、16b彼此的間隔距離例如約為第六側邊S6之長度的百分之二十二。連接部16a、16b的材質例如為銅、銀、金等導體。上述僅為舉例示範，實際上並不以此為限制。值得注意的是，晶片導通件1可以具有任意個連接部，在此並不加以限制。而在此及以下的實施例中係舉連接部16a、16b為例進行說明，惟在此並不加以限制。The connecting portions 16a and 16b are used to electrically connect the external electrical contacts 3. In more detail, the connecting portions 16a, 16b are electrically connected to the external electrical contacts 3 by their respective contact faces, thereby increasing the coupling area and reducing the transmission impedance. Further, the connecting portions 16a, 16b are separated from each other to increase the stress that can be withstood. In more detail, the length of the connecting portions 16a, 16b is, for example, about forty percent of the sixth side S6, and the width of the connecting portions 16a, 16b is, for example, about six percent of the sixth side S6. The distance between the connecting portions 16a, 16b is, for example, about twenty-two percent of the length of the sixth side S6. The material of the connecting portions 16a and 16b is, for example, a conductor such as copper, silver or gold. The above is merely an example and is not actually limited thereto. It should be noted that the wafer via 1 may have any number of connections, which is not limited herein. In the following and the following embodiments, the connecting portions 16a and 16b are described as an example, but are not limited thereto.

晶片導通件1藉由定位部18a、18b、18c設置於輔助治具當中，以提升封裝製程的效率。請接著參照圖2以對定位部進行說明，圖2係本新型另一實施例中晶片導通件連接於容置架上的示意圖。在圖2中繪示有晶片導通件4a、4b、4c與容置架5。容置架5具有容置框52a、52b、52c，容置框52a、52b、52c分別對應於晶片導通件4a、4b、4c。晶片導通件4a、4b、4c分別以其定位部連接於容置框52a、52b、52c。因此，於製程中能以容置架5使晶片導通件4a、4b、4c精確地與排列好的晶片2a、2b、2c與外部電性接點3a、3b、3c一一對應，以進行後續上膠加熱固定的步驟。然後在設置晶片導通件4a、4b、4c於晶片2a、2b、2c與外部電性接點3a、3b、3c之間後，再裁切晶片導通件4a、4b、4c的各定位部，以使晶片導通件4a、4b、4c與容置架5分離。藉此，得以在封裝製程中，以有效率的方式快速、大量且精準地組裝晶片導通件4a、4b、4c於晶片2a、2b、2c與外部電性接點3a、3b、3c之間。The wafer via 1 is disposed in the auxiliary fixture by the positioning portions 18a, 18b, and 18c to improve the efficiency of the packaging process. Referring to FIG. 2, the positioning portion will be described. FIG. 2 is a schematic view showing the wafer conduction member connected to the receiving frame in another embodiment of the present invention. The wafer vias 4a, 4b, 4c and the accommodating frame 5 are shown in FIG. The accommodating frame 5 has accommodating frames 52a, 52b, 52c, and the accommodating frames 52a, 52b, 52c correspond to the wafer conducting members 4a, 4b, 4c, respectively. The wafer vias 4a, 4b, 4c are respectively connected to the accommodating frames 52a, 52b, 52c by their positioning portions. Therefore, in the process, the wafer vias 4a, 4b, 4c can be accurately matched with the aligned wafers 2a, 2b, 2c and the external electrical contacts 3a, 3b, 3c by the accommodating frame 5 for subsequent operation. Glue and heat the fixed step. Then, after the wafer vias 4a, 4b, 4c are disposed between the wafers 2a, 2b, 2c and the external electrical contacts 3a, 3b, 3c, the positioning portions of the wafer vias 4a, 4b, 4c are then cut to The wafer vias 4a, 4b, 4c are separated from the accommodating frame 5. Thereby, the wafer vias 4a, 4b, 4c are quickly and massively and accurately assembled between the wafers 2a, 2b, 2c and the external electrical contacts 3a, 3b, 3c in an efficient manner in the packaging process.

請再參照圖1A至圖1D。根據上述，定位部18a、18b、18c可以具有相同的形狀或不同的形狀，此係為所屬技術領域具有通常知識者可以根據晶片導通件1、晶片2與外部電性接點3的相對位置來進行設計。在此實施例中，定位部18a、18b、18c係分別為矩形，其長度例如為第五側邊S5的六分之一，但不以此為限制。Please refer to FIG. 1A to FIG. 1D again. According to the above, the positioning portions 18a, 18b, 18c may have the same shape or different shapes, which may be based on the relative positions of the wafer via 1, the wafer 2 and the external electrical contacts 3. Design. In this embodiment, the positioning portions 18a, 18b, and 18c are respectively rectangular, and the length thereof is, for example, one sixth of the fifth side S5, but is not limited thereto.

請再參照圖1A至圖1D以說明本新型所揭露之晶片導通件的其他細部結構。如圖1A至圖1D所示，本體部12之第一側邊S1的第二段S12向內凹陷。在此實施例中，第二段S12係向內凹陷形成一弧角，以減少電流損耗。而訊號傳輸部14之第三側邊S3自第一側邊S1的第二段S12延伸而出。因此，當晶片導通件1以本體部12覆蓋並電性連接第一電極22的時候，晶片導通件1暴露出第二電極24，且不與第二電極24接觸。藉此，第二電極24得以藉由打線製程電性連接其他的外部電性接點。Please refer to FIG. 1A to FIG. 1D again to illustrate other detailed structures of the wafer via member disclosed in the present invention. As shown in FIGS. 1A to 1D, the second section S12 of the first side S1 of the body portion 12 is recessed inward. In this embodiment, the second segment S12 is recessed inwardly to form an arc angle to reduce current loss. The third side S3 of the signal transmission portion 14 extends from the second segment S12 of the first side S1. Therefore, when the wafer via 1 is covered by the body portion 12 and electrically connected to the first electrode 22, the wafer via 1 exposes the second electrode 24 and is not in contact with the second electrode 24. Thereby, the second electrode 24 can be electrically connected to other external electrical contacts by a wire bonding process.

訊號傳輸部14之第四側邊S4凸出於本體部12的第二側邊S2。具體地來說，第四側邊S4的第一段S41與第二段S42及第二側邊S2分別夾有一夾角。在本實施例中，第一側邊S1、第二側邊S2、第三側邊S3與第四側邊S4的延伸方向彼此不重疊，但各側邊的相對關係並不以此為限。The fourth side S4 of the signal transmission portion 14 protrudes from the second side S2 of the body portion 12. Specifically, the first segment S41 of the fourth side S4 and the second segment S42 and the second side S2 respectively have an included angle. In this embodiment, the extending directions of the first side S1, the second side S2, the third side S3, and the fourth side S4 do not overlap each other, but the relative relationship of the sides is not limited thereto.

此外於本實施例中，訊號傳輸部14具有傾斜段144。傾斜段144的延伸軸向相交於本體部12的延伸平面，且傾斜段144相對於本體部12的一側邊連接連接部16a、16b。因此連接部16a、16b不與本體部12共平面。在本實施例中，連接部16a、16b與本體部12的延伸平面所間隔之距離大約相同於本體部12的厚度。而在一實施例中，本體部12、訊號傳輸部14與連接部16a、16b係為一體成形。此外，定位部18a、18b、18c除了用以定位之外，更可以在組裝過程中保持晶片導通件1的平衡而使作業更容易。Further, in the present embodiment, the signal transmission portion 14 has an inclined section 144. The extending axial direction of the inclined section 144 intersects the extending plane of the body portion 12, and the inclined section 144 connects the connecting portions 16a, 16b with respect to one side of the body portion 12. Therefore, the connecting portions 16a, 16b are not coplanar with the body portion 12. In the present embodiment, the distance between the connecting portions 16a, 16b and the plane of extension of the body portion 12 is approximately the same as the thickness of the body portion 12. In one embodiment, the body portion 12, the signal transmission portion 14, and the connecting portions 16a, 16b are integrally formed. Further, in addition to positioning, the positioning portions 18a, 18b, and 18c can maintain the balance of the wafer conduction member 1 during assembly to make the work easier.

綜上所述，本新型提供了一種晶片導通件。晶片導通件係以第一電極連接面電性連接晶片的電極，且以至少一連接部電性連接外部的電性接點。由於第一電極連接面與連接部具有一定的面積，因此相較於以往用打線連接晶片電極與外部電性接點的傳統做法，本新型所提供之晶片導通件大幅提升了與晶片電極及外部電性接點的耦接面積，藉此降低了訊號的傳輸阻抗。此外，更能輔以容置框架，而能更快速、精準且大量組裝晶片導通件於晶片電極及外部電性接點，增加了封裝製程的效率，相當具有實用性。In summary, the present invention provides a wafer via. The wafer vias are electrically connected to the electrodes of the wafer by the first electrode connection surface, and are electrically connected to the external electrical contacts by at least one connection portion. Since the first electrode connection surface and the connection portion have a certain area, the wafer conduction member provided by the present invention greatly improves the wafer electrode and the external portion compared with the conventional method of connecting the wafer electrode and the external electrical contact by wire bonding. The coupling area of the electrical contacts, thereby reducing the transmission impedance of the signal. In addition, the frame can be assembled more quickly, accurately and in a large amount by assembling the wafer vias on the wafer electrodes and external electrical contacts, which increases the efficiency of the packaging process and is quite practical.

雖然本新型以前述之實施例揭露如上，然其並非用以限定本新型。在不脫離本新型之精神和範圍內，所為之更動與潤飾，均屬本新型之專利保護範圍。關於本新型所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the present invention. The changes and refinements of the present invention are within the scope of the patent protection of the present invention without departing from the spirit and scope of the present invention. Please refer to the attached patent application for the scope of protection defined by this new model.

1、4a、4b、4c‧‧‧晶片導通件
12‧‧‧本體部
124a、124b‧‧‧貫孔
126‧‧‧第一溝槽
14‧‧‧訊號傳輸部
142‧‧‧第二溝槽
144‧‧‧傾斜段
16a、16b‧‧‧連接部
18a、18b、18c‧‧‧定位部
2‧‧‧晶片
22‧‧‧第一電極
24‧‧‧第二電極
3‧‧‧外部電性接點
5‧‧‧容置架
52a、52b、52c‧‧‧容置框
P1‧‧‧上表面
P2‧‧‧第一電極接觸面
S1‧‧‧第一側邊
S11‧‧‧第一側邊的第一段
S12‧‧‧第一側邊的第二段
S2‧‧‧第二側邊
S3‧‧‧第三側邊
S4‧‧‧第四側邊
S41‧‧‧第四側邊的第一段
S42‧‧‧第四側邊的第二段
S5‧‧‧第五側邊1, 4a, 4b, 4c‧‧‧ wafer passers
12‧‧‧ Body Department
124a, 124b‧‧‧through holes
126‧‧‧First trench
14‧‧‧Signal Transmission Department
142‧‧‧Second trench
144‧‧‧Sloping section
16a, 16b‧‧‧ Connections
18a, 18b, 18c‧‧‧ Positioning Department
2‧‧‧ wafer
22‧‧‧First electrode
24‧‧‧second electrode
3‧‧‧External electrical contacts
5‧‧‧Rack
52a, 52b, 52c‧‧‧ accommodating frame
P1‧‧‧ upper surface
P2‧‧‧first electrode contact surface
S1‧‧‧ first side
The first paragraph of the first side of S11‧‧
Second paragraph of the first side of S12‧‧
S2‧‧‧ second side
S3‧‧‧ third side
S4‧‧‧ fourth side
S41‧‧‧ the first paragraph of the fourth side
Second paragraph of the fourth side of S42‧‧
S5‧‧‧ fifth side

圖1A 係本新型一實施例中晶片導通件相對於外部電性接點的爆炸示意圖。 圖1B 係本新型圖1A 中晶片導通件的立體示意圖。 圖1C 係本新型圖1A 中晶片導通件的俯視示意圖。 圖1D 係本新型圖1A 中晶片導通件的仰視示意圖。 圖2 係本新型另一實施例中晶片導通件連接於容置架上的示意圖。1A is a schematic exploded view of a wafer via in relation to an external electrical contact in an embodiment of the present invention. Figure 1B is a perspective view of the wafer via of Figure 1A of the present invention. Figure 1C is a top plan view of the wafer via of Figure 1A of the present invention. Figure 1D is a bottom plan view of the wafer via of Figure 1A of the present invention. 2 is a schematic view showing another embodiment of the present invention in which a wafer via is connected to a receiving frame.

1‧‧‧晶片導通件1‧‧‧Wafer vias

12‧‧‧本體部12‧‧‧ Body Department

124a、124b‧‧‧貫孔124a, 124b‧‧‧through holes

126‧‧‧第一溝槽126‧‧‧First trench

14‧‧‧訊號傳輸部14‧‧‧Signal Transmission Department

142‧‧‧第二傳輸部142‧‧‧Second transmission department

144‧‧‧傾斜段144‧‧‧sloping section

16a、16b‧‧‧連接部16a, 16b‧‧‧ Connections

18a、18b、18c‧‧‧定位部18a, 18b, 18c‧‧‧ Positioning Department

P1‧‧‧上表面P1‧‧‧ upper surface

P2‧‧‧第一電極接觸面P2‧‧‧first electrode contact surface

S1‧‧‧第一側邊S1‧‧‧ first side

S11‧‧‧第一側邊的第一段The first paragraph of the first side of S11‧‧

S12‧‧‧第一側邊的第二段Second paragraph of the first side of S12‧‧

S2‧‧‧第二側邊S2‧‧‧ second side

S3‧‧‧第三側邊S3‧‧‧ third side

S4‧‧‧第四側邊S4‧‧‧ fourth side

S41‧‧‧第四側邊的第一段S41‧‧‧ the first paragraph of the fourth side

S42‧‧‧第四側邊的第二段Second paragraph of the fourth side of S42‧‧

S5‧‧‧第五側邊S5‧‧‧ fifth side

S6‧‧‧第六側邊S6‧‧‧ sixth side

Claims (18)

一種晶片導通件，用以連接於一晶片的一第一電極與至少一外部電性接點之間，該晶片導通件包含：一本體部，具有一第一電極接觸面與至少一貫孔，該第一電極接觸面用以覆蓋至少部分的該第一電極；一訊號傳輸部，連接該本體部；以及至少一連接部，連接該訊號傳輸部，用以連接該至少一外部電性接點；其中該本體部、該訊號傳輸部與該至少一連接部共同形成一上表面，該上表面相對於該第一電極接觸面。A wafer conducting member is connected between a first electrode of a wafer and at least one external electrical contact, the wafer conducting member comprising: a body portion having a first electrode contact surface and at least a consistent hole, The first electrode contact surface is configured to cover at least a portion of the first electrode; a signal transmission portion is coupled to the body portion; and at least one connection portion is connected to the signal transmission portion for connecting the at least one external electrical contact; The body portion, the signal transmission portion and the at least one connection portion together form an upper surface, the upper surface being opposite to the first electrode contact surface. 如請求項1所述的晶片導通件，其中該第一電極接觸面具有一第一溝槽，該至少一貫孔暴露於該第一溝槽。The wafer via of claim 1, wherein the first electrode contact mask has a first trench, the at least consistent aperture being exposed to the first trench. 如請求項2所述的晶片導通件，其中該第一溝槽暴露於該本體部具有的其中兩側。The wafer via of claim 2, wherein the first trench is exposed to both sides of the body portion. 如請求項3所述的晶片導通件，其中該第一溝槽暴露於該本體部的相對兩側。The wafer via of claim 3, wherein the first trench is exposed on opposite sides of the body portion. 如請求項3所述的晶片導通件，其中當該晶片導通件設置於該晶片上時，該晶片導通件覆蓋該第一電極但暴露出該晶片的一第二電極。The wafer via of claim 3, wherein the wafer via covers the first electrode but exposes a second electrode of the wafer when the wafer via is disposed on the wafer. 如請求項5所述的晶片導通件，其中該本體部具有一第一側邊，部份的該第一側邊向內凹陷。The wafer via of claim 5, wherein the body portion has a first side, and a portion of the first side is recessed inward. 如請求項6所述的晶片導通件，其中該本體部更具有一第二側邊，該訊號傳輸部具有一第三側邊與一第四側邊，該第二側邊相對於該第一側邊，該第三側邊自該第一側邊凹陷的一端延伸而出，該第四側邊凸出於該第二側邊。 The wafer conductive member of claim 6, wherein the body portion further has a second side, the signal transmitting portion has a third side and a fourth side, the second side being opposite to the first side a side edge extending from an end of the first side recess, the fourth side protruding from the second side. 如請求項7所述的晶片導通件，其中該第一側邊、該第二側邊、該第三側邊與該第四側邊的延伸方向彼此不重疊。 The wafer via member according to claim 7, wherein the extending direction of the first side, the second side, the third side, and the fourth side does not overlap each other. 如請求項6所述的晶片導通件，其中該第一側邊向內凹陷形成一弧角。 The wafer via of claim 6, wherein the first side is recessed inward to form an arc angle. 如請求項6所述的晶片導通件，其中該訊號傳輸部具有一傾斜段，該傾斜段的延伸軸向與該本體部的延伸平面夾有一夾角，該傾斜段的一側邊連接該至少一連接部。 The wafer conducting member according to claim 6, wherein the signal transmitting portion has an inclined portion, the extending axial direction of the inclined portion is at an angle with the extending plane of the body portion, and one side of the inclined portion is connected to the at least one Connection. 如請求項10所述的晶片導通件，其中該連接部不與該本體部共平面。 The wafer via of claim 10, wherein the connection is not coplanar with the body portion. 如請求項10所述的晶片導通件，其中該訊號傳輸部更具有一第二溝槽。 The wafer via member of claim 10, wherein the signal transmission portion further has a second trench. 如請求項12所述的晶片導通件，該第二溝槽更露出於該訊號傳輸部的相對兩側邊。 The wafer vias of claim 12, wherein the second trenches are further exposed on opposite sides of the signal transmission portion. 如請求項12所述的晶片導通件，更包含有多個連接部，該些連接部用以分別耦接該至少一外部電性接點。 The wafer via member of claim 12, further comprising a plurality of connecting portions, wherein the connecting portions are respectively coupled to the at least one external electrical contact. 如請求項14所述的晶片導通件，更包含多個定位部，該些定位部分別自該本體部或該訊號傳輸部延伸而出，且該些定位部用以連接一容置架中的一容置框。The method of claim 14, further comprising a plurality of positioning portions extending from the body portion or the signal transmitting portion, and the positioning portions are configured to be connected to a receiving frame A box. 如請求項15所述的晶片導通件，其中一該定位部係位於其中二該連接部之間。The wafer via member of claim 15, wherein one of the positioning portions is located between the two of the connecting portions. 如請求項16所述的晶片導通件，其中另二該定位部係位於該本體部所具有的其中兩側邊。The wafer via member of claim 16, wherein the other of the positioning portions is located on both sides of the body portion. 如請求項17所述的晶片導通件，其中該本體部、該訊號傳輸部與該至少一連接部係一體成形。The wafer via member according to claim 17, wherein the body portion, the signal transmission portion and the at least one connection portion are integrally formed.
TW104213755U 2015-08-25 2015-08-25 Chip conducting member TWM514108U (en)

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