TWM494307U - Rapid multi-port signal measurement device - Google Patents
Rapid multi-port signal measurement device Download PDFInfo
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Description
本創作係有關於一種多埠訊號的量測裝置,尤指一種適於量測多埠射頻訊號之快速量測裝置。This creation is about a multi-signal measurement device, especially a fast measurement device suitable for measuring multi-turn RF signals.
隨著科技的蓬勃發展,改變了現代人的生活方式,人們現今對於行動通訊的品質要求亦隨之不斷地增加。為了達到更佳品質的行動通訊,設計良好的通訊系統、天線與射頻元件都扮演著其中相當重要的角色。而除了設計之外,待測樣本的測試也是其中極為重要的一環,除了測試所設計出來的射頻元件其頻寬與輻射能量、功率輸出等要求是否有達到標準外,更是影響射頻元件操作品質重要的因素之一。With the rapid development of technology and the changing of the modern people's way of life, people's current quality requirements for mobile communication have also increased. In order to achieve better quality mobile communications, well-designed communication systems, antennas and RF components play a very important role. In addition to the design, the test of the sample to be tested is also an extremely important part. In addition to the RF component designed by the test, whether the bandwidth, radiant energy, power output and other requirements meet the standards, it also affects the operation quality of the RF component. One of the important factors.
其中,當測試晶片具有多個訊號輸出,而訊號分析器只有單一個的時候,為了量測且分析各個輸出埠其個別之功率輸出時,習知技術遂提出將射頻開關與方向耦合器以零件式方式組合的作法進行量測,量測步驟包括:先將射頻開關切換至欲量測的一輸出埠後,啟動訊號分析器進行量測、分析和記錄測試訊號,之後,再將射頻開關切換至欲量測的另一輸出埠,再次啟動訊號分析器進行量測、分析和記錄測試訊號,持續重複以上流程,直到所有待量測的輸出埠都量測完畢。Wherein, when the test chip has multiple signal outputs, and the signal analyzer has only one single, in order to measure and analyze each output and its individual power output, the conventional technology proposes to use the RF switch and the directional coupler as parts. The method of combining the methods is performed. The measuring step includes: first switching the RF switch to an output port to be measured, then starting the signal analyzer to measure, analyze, and record the test signal, and then switching the RF switch. To the other output to be measured, start the signal analyzer again to measure, analyze and record the test signal, and repeat the above process until all the outputs to be measured are measured.
然而,值得注意的是,利用此種習知裝置之量測流程,訊號 分析器都必須等待射頻開關切換至每一待量測之輸出埠後,方可啟動,進而完成訊號的量測與分析。而每利用訊號分析器量測一個輸出埠,都必須花費一次啟動儀器的時間,導致測試時間變長,降低測試效率。However, it is worth noting that the measurement process using such a conventional device, the signal The analyzer must wait for the RF switch to switch to each output to be measured before it can be started to complete the measurement and analysis of the signal. Each time an output analyzer is used to measure an output, it takes time to start the instrument, resulting in longer test times and lower test efficiency.
有鑑於此,本創作人係有感於上述缺失之可改善,且依據多年來從事此方面之相關經驗,悉心觀察且研究之,並配合學理之運用,而提出一種設計新穎且有效改善上述缺失之本創作,其係揭露一種可快速量測多埠訊號之量測裝置,其具體之架構及實施方式將詳述於下。In view of this, the creator feels that the above-mentioned deficiencies can be improved, and based on years of experience in this field, carefully observe and study, and with the use of academics, propose a novel design and effectively improve the above-mentioned defects. In this creation, a measuring device capable of quickly measuring a plurality of signals is disclosed, and the specific structure and implementation manner thereof will be described in detail below.
為解決習知技術存在的問題,本創作之一目的係在於提供一種快速量測多埠訊號之裝置,其係為了改善習見量測裝置測試時間過長,且測試效率過低等問題。In order to solve the problems existing in the prior art, one of the aims of the present invention is to provide a device for quickly measuring multi-signal signals, which is to improve the test time of the measuring device and the test efficiency is too low.
本創作之又一目的係在於提供一種快速量測多埠訊號之裝置,其係利用一控制主機同時控制射頻開關與訊號分析器量測的動作,一次擷取所有輸出埠的輸出訊號,並利用擷取到的訊號進行分析,以產生一連續性的連續訊號,解析出待測晶片各個輸出埠之功率輸出。Another object of the present invention is to provide a device for quickly measuring multi-turn signals, which uses a control host to simultaneously control the measurement of the RF switch and the signal analyzer, and simultaneously extracts the output signals of all the output ports and utilizes them. The captured signals are analyzed to generate a continuous continuous signal that resolves the power output of each output of the wafer to be tested.
本創作之再一目的係在於提供一種快速量測多埠訊號之裝置,其亦適於量測一個以上的待測晶片,利用提供多個測試模組,其中每一測試模組係耦接於每一待測晶片,控制主機亦可據以產生多個對應於該些待測晶片之連續訊號,增加實務上應用之可行性。A further object of the present invention is to provide a device for quickly measuring a plurality of signals, which is also suitable for measuring more than one wafer to be tested, and providing a plurality of test modules, wherein each test module is coupled to For each chip to be tested, the control host can also generate a plurality of consecutive signals corresponding to the chips to be tested, thereby increasing the feasibility of practical application.
是以,根據本創作所揭示之快速量測多埠訊號之裝置,係包括有一控制主機與至少一測試模組,其中測試模組係耦接控制主機與待測晶片,且待測晶片具有一輸入埠與複數個輸出埠。Therefore, the apparatus for quickly measuring a multi-signal signal according to the present invention includes a control host and at least one test module, wherein the test module is coupled to the control host and the wafer to be tested, and the wafer to be tested has a Enter 埠 and a number of outputs 埠.
根據本創作之實施例,所述之測試模組更包括有一訊號產生器、一開關模組與一訊號分析器。其中,訊號產生器與開關模組係耦接控制主機與待測晶片之間,訊號分析器係耦接於開關模組與控制主機之間。故,控制主機可控制訊號產生器產生一測試訊號予待測晶片之一輸入埠,使得待測晶片之每一輸出埠係產生對應之一輸出訊號。According to an embodiment of the present invention, the test module further includes a signal generator, a switch module and a signal analyzer. The signal generator and the switch module are coupled between the control host and the chip to be tested, and the signal analyzer is coupled between the switch module and the control host. Therefore, the control host can control the signal generator to generate a test signal to one of the input chips of the chip to be tested, so that each output of the chip to be tested generates a corresponding one of the output signals.
之後,控制主機係控制開關模組對每一輸出埠進行切換,使得訊號分析器可依據每一輸出埠之開關順序依序擷取各個輸出訊號,並在取得所有輸出訊號後傳回控制主機進行分析。After that, the control host controls the switch module to switch each output port, so that the signal analyzer can sequentially capture each output signal according to the switching sequence of each output port, and return to the control host after obtaining all the output signals. analysis.
根據本創作之實施例,控制主機係依據該些輸出埠之輸出訊號產生一連續性的連續訊號。所述的連續訊號係包括在同一時間軸上每一輸出埠之輸出訊號。According to an embodiment of the present invention, the control host generates a continuous continuous signal according to the output signals of the output ports. The continuous signal includes output signals of each output port on the same time axis.
再者,本創作所揭示之量測裝置,更可包括一個以上所述之測試模組,當測試模組之數量為複數個時,則控制主機耦接每一測試模組,以達到同時量測複數個待測晶片之目的。Furthermore, the measuring device disclosed in the present invention may further include one or more test modules. When the number of test modules is plural, the control host is coupled to each test module to achieve simultaneous quantities. The purpose of measuring a plurality of chips to be tested.
底下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本創作之目的、技術內容、特點及其所達成之功效。The purpose of the present invention, the technical content, the features, and the effects achieved by the present invention will be more readily understood by the specific embodiments and the accompanying drawings.
1‧‧‧待測晶片1‧‧‧Samps to be tested
10‧‧‧控制主機10‧‧‧Control host
20‧‧‧測試模組20‧‧‧Test module
202‧‧‧訊號產生器202‧‧‧Signal Generator
204‧‧‧開關模組204‧‧‧Switch Module
206‧‧‧訊號分析器206‧‧‧Signal Analyzer
第1圖係為根據本創作實施例快速量測多埠訊號之裝置的示意圖。Fig. 1 is a schematic diagram of a device for quickly measuring a multi-turn signal according to the present embodiment.
第2圖係為根據本創作實施例之待測晶片的示意圖。Fig. 2 is a schematic view of a wafer to be tested according to the present embodiment.
第3圖係為根據本創作實施例之量測流程示意圖。Figure 3 is a schematic diagram of the measurement flow according to the present creative embodiment.
第4圖係為根據本創作實施例控制主機產生之連續訊號的示意圖。Figure 4 is a schematic diagram of controlling successive signals generated by a host in accordance with the present creative embodiment.
第5圖係為利用本創作與現有技術進行量測之總量測時間的結果數據比較圖。Fig. 5 is a comparison of result data of the total measurement time measured by the present creation and the prior art.
第6圖係為根據本創作另一實施例快速量測多埠訊號之裝置的示意圖。Figure 6 is a schematic diagram of an apparatus for rapidly measuring a plurality of signals according to another embodiment of the present creation.
第7A圖係為根據第6圖實施例控制主機輸出之一連續訊號的示意圖。Figure 7A is a schematic diagram of controlling one of the continuous signals output by the host according to the embodiment of Figure 6.
第7B圖係為根據第6圖實施例控制主機輸出之另一連續訊號的示意圖。Figure 7B is a schematic diagram of another continuous signal that controls the output of the host in accordance with the embodiment of Figure 6.
第7C圖係為根據第6圖實施例控制主機輸出之又一連續訊號的示意圖。Figure 7C is a schematic diagram of another continuous signal that controls the output of the host in accordance with the embodiment of Figure 6.
以上有關於本創作的內容說明,與以下的實施方式係用以示範與解釋本創作的精神與原理,並且提供本創作的專利申請範圍更進一步的解釋。有關本創作的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。The above description of the content of the present invention is used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention. The features, implementations, and effects of the present invention are described in detail below with reference to the preferred embodiment.
為了便於理解本創作之精神與原理,請參第1圖所示,其係為根據本創作實施例快速量測多埠訊號之裝置的示意圖。本創作所揭示之量測裝置係用以量測至少一待測晶片1之多埠訊號,該待測晶片1具有一輸入埠Vin與複數個輸出埠V1,V2,V3...Vn-1,Vn。In order to facilitate the understanding of the spirit and principle of the present invention, please refer to FIG. 1 , which is a schematic diagram of a device for quickly measuring multi-signal signals according to the present embodiment. The measuring device disclosed in the present invention is for measuring at least one signal of the wafer 1 to be tested, the wafer 1 to be tested has an input 埠Vin and a plurality of outputs 埠V1, V2, V3...Vn-1 , Vn.
根據本創作所揭示之量測裝置,包括有一控制主機10與至少一測試模組20。測試模組20係電性耦接於控制主機10與待測晶片1之間,並且測試模組20包括:一訊號產生器202、一開關模組204以及一訊號分析器206。其中,訊號產生器202例如可為一向量訊號產生器(Vector Signal Generator,VSG),訊號分析器206例如可為一向量訊號分析器(Vector Signal Analyzer,VSA)。訊號產生器202與開關模組204係各自耦接於控制主機10與待測晶片1之間,訊號分析器206係耦接於開關模組204與控制主機10之間。是以,根據本創作之實施例,控制主機10係首先控制訊號產生器202提供一測試訊號(test signal),如第2圖所示,該測試訊號係輸入予待測晶片1之輸入埠Vin。之後,待測晶片1在接收測試訊號後,會在輸出埠V1,V2,V3個別產生對應之輸出訊號(output signal)A,B,C。其中,待測晶片1所接收與輸出之測試訊號及輸出訊號例如可為一射頻(Radio Frequency,RF)訊號。The measuring device disclosed in the present invention comprises a control host 10 and at least one test module 20. The test module 20 is electrically coupled between the control host 10 and the wafer 1 to be tested, and the test module 20 includes a signal generator 202, a switch module 204, and a signal analyzer 206. The signal generator 202 can be, for example, a vector signal generator (Vector Signal Generator, VSG), the signal analyzer 206 can be, for example, a Vector Signal Analyzer (VSA). The signal generator 202 and the switch module 204 are respectively coupled between the control host 10 and the wafer 1 to be tested, and the signal analyzer 206 is coupled between the switch module 204 and the control host 10. Therefore, according to the embodiment of the present invention, the control host 10 first controls the signal generator 202 to provide a test signal. As shown in FIG. 2, the test signal is input to the input of the wafer 1 to be tested 埠Vin. . After that, after receiving the test signal, the wafer to be tested 1 separately generates corresponding output signals A, B, and C at the outputs 埠V1, V2, and V3. The test signal and the output signal received and outputted by the chip 1 to be tested may be, for example, a radio frequency (RF) signal.
請一併參閱第3圖所示,其係為根據本創作實施例之量測流程示意圖,如步驟S401所示,控制主機10開始控制並啟動訊號分析器206擷取輸出訊號,之後,如步驟S402至S404所示,控制主機10係控制開關模組204依序對待測晶片1之每個輸出埠進行切換。根據本創作之實施例,如第1圖所示,開關模組204係具有複數個連接埠S1,S2,S3...Sn-1,Sn,每一連接埠係各自電性耦接於一輸出埠,以對各個輸出埠進行切換,並依序開啟每一輸出埠V1,V2...Vn。舉例而言,當輸出埠V1形成開啟狀態時,訊號分析器206係擷取到輸出訊號A;當輸出埠V1關閉,而輸出埠V2形成開啟狀態時,訊號分析器206係擷取到輸出訊號B;當輸出埠V2關閉,而輸出埠V3形成開啟狀態時,訊號分析器206係擷取到輸出訊號C。直到輸出埠Vn被開啟,而訊號分析器206擷取到所有的輸出訊號後,訊號分析器206方停止擷取訊號的動作(步驟S405)。最後,如步驟S406所示,在所有的輸出訊號都被擷取完成後,訊號分析器206係將該些輸出訊號傳回控制主機10進行分析。As shown in FIG. 3, it is a schematic diagram of the measurement process according to the present embodiment. As shown in step S401, the control host 10 starts control and starts the signal analyzer 206 to extract the output signal, and then, as in the step. As shown in S402 to S404, the control host 10 controls the switch module 204 to sequentially switch each output port of the wafer 1 to be tested. According to the embodiment of the present invention, as shown in FIG. 1, the switch module 204 has a plurality of ports 1S1, S2, S3, ..., Sn-1, Sn, each of which is electrically coupled to one of the ports. Output 埠 to switch each output ,, and turn on each output 埠V1, V2...Vn in sequence. For example, when the output 埠V1 is turned on, the signal analyzer 206 captures the output signal A; when the output 埠V1 is turned off and the output 埠V2 is turned on, the signal analyzer 206 captures the output signal. B; When the output 埠V2 is turned off and the output 埠V3 is turned on, the signal analyzer 206 captures the output signal C. Until the output 埠Vn is turned on, and the signal analyzer 206 captures all the output signals, the signal analyzer 206 stops the action of capturing the signal (step S405). Finally, as shown in step S406, after all the output signals have been retrieved, the signal analyzer 206 transmits the output signals back to the control host 10 for analysis.
其中,值得說明的是,為了解決習見機械式開關進行訊號之切換與量測時,多具有測試時間過長及切換次數過多之問題,本發明所揭示之開關模組204可選擇使用固態式開關來進行上述之切換動作,該固態式開關可例如為:二極體、金氧半場效電晶體、或雙載子接面電晶體等等。惟在可容許的測試時間與切換次數之範圍內,開關模組204仍可選擇以一般的機械式開關來據以實施,本發明所述之技術思想並不以開關模組之實施態樣為限。It should be noted that, in order to solve the problem that the mechanical switch is used for switching and measuring signals, the test module 204 can be selected to use the solid state switch. In order to perform the above switching operation, the solid state switch may be, for example, a diode, a MOS field effect transistor, or a bipolar junction transistor, or the like. However, within the range of allowable test time and number of switching times, the switch module 204 can still be implemented by using a general mechanical switch. The technical idea of the present invention is not based on the implementation of the switch module. limit.
第4圖係為根據本創作實施例控制主機分析後所產生之訊號示意圖,由第4圖可以看出,控制主機10係根據該些輸出訊號產生一連續性的連續訊號,且該連續訊號係包括在同一時間軸上每一輸出埠之輸出訊號。承以前例第2圖所示之待測晶片(具有一輸入埠Vin與三個輸出埠V1,V2,V3,且輸出埠V1之輸出訊號為A,輸出埠V2之輸出訊號為B,輸出埠V3之輸出訊號為C)而言,則該連續訊號係可在同一時間軸上依據輸出埠V1,V2,V3開啟的順序,依序顯示出輸出訊號A,B,C。FIG. 4 is a schematic diagram of signals generated after controlling the host analysis according to the present embodiment. As can be seen from FIG. 4, the control host 10 generates a continuous continuous signal according to the output signals, and the continuous signal system is Includes output signals for each output on the same time axis. The chip to be tested shown in Figure 2 of the previous example (haves an input 埠Vin and three outputs 埠V1, V2, V3, and the output signal of output 埠V1 is A, and the output signal of output 埠V2 is B, output 埠When the output signal of V3 is C), the continuous signal can display the output signals A, B, and C sequentially on the same time axis according to the order in which the outputs 埠V1, V2, and V3 are turned on.
是以,根據本創作之實施例,當待測晶片1具有n個輸出埠V1,V2,V3...Vn-1,Vn,每一輸出埠之切換時間係為B,啟動訊號分析器206擷取訊號的時間係為A時,那麼本創作所需的總量測時間係為(A+B*n),且該量測時間之單位可短至秒、毫秒(ms)甚至微秒(μs)等級。相較於現有技術,如在同一測試條件與相同的待測晶片1之情況下,則現有技術所需花費的總量測時間係會是(A*n+B*n)。由此顯見,利用本創作所揭示之量測裝置進行多埠訊號之量測時,其所需使用的量測時間相較於現有技術,可大幅地降低且更有效率。當所需量測的輸出埠數量越多時,則此效 益係越發明顯。Therefore, according to the embodiment of the present invention, when the wafer to be tested 1 has n outputs 埠V1, V2, V3...Vn-1, Vn, the switching time of each output 系 is B, and the signal analyzer 206 is activated. When the time of the signal is A, then the total measurement time required for this creation is (A+B*n), and the unit of measurement time can be as short as seconds, milliseconds (ms) or even microseconds ( Ss) grade. Compared with the prior art, as in the case of the same test condition and the same wafer 1 to be tested, the total time required for the prior art would be (A*n+B*n). It is thus apparent that the measurement time required for the measurement of the multi-signal signal by the measuring device disclosed in the present invention can be greatly reduced and more efficient than the prior art. When the quantity of output 所需 required is measured, the effect is The benefits are more obvious.
第5圖係為利用本創作與現有技術進行量測之總量測時間的結果數據比較圖,由此圖可以明顯看出,當輸出埠之數量為4埠的情況下,利用本創作所揭示之量測裝置進行多埠訊號的測量,其量測時間係可比現有技術快一倍。至於,當輸出埠的數量增加到20埠的情況下,則本創作所花費的量測時間則可比現有技術快達3倍以上。由此證明,根據本創作實施例所揭露之量測裝置,不僅可有效率地加速習見之量測速度,隨著所需量測的埠數越多,其效應係更加的顯著且優於習知技術。Figure 5 is a comparison of the result data of the total measurement time measured by the present invention and the prior art, and it can be clearly seen from the figure that when the number of output defects is 4埠, the use of the present disclosure reveals The measuring device performs multi-signal measurement, and the measuring time is twice as fast as the prior art. As for the case where the number of output defects is increased to 20 ,, the measurement time taken by the creation can be more than three times faster than the prior art. It is thus proved that the measuring device disclosed in the embodiment of the present invention can not only accelerate the measurement speed of the conventionally, but also the effect is more significant and superior to the learning. Know the technology.
除此之外,本創作所揭露之量測裝置並不以量測單一待測晶片為限。換言之,利用本創作所揭示的量測裝置,其係可更進一步地用以量測一個以上的待測晶片1,其裝置示意圖係如第6圖所示。其中,當測試模組20之數量係為複數個時,則控制主機10只要透過電性耦接於每一測試模組20,並控制每一測試模組20對各個與之連接的待測晶片1進行如步驟S401至步驟S406之量測程序,則可同時對該複數個待測晶片1進行輸出訊號的量測與分析,藉此達到快速量測並可平行擷取多埠訊號之目的。在此實施例中,當待測晶片1之數量為3個時,則控制主機可輸出對應之3個連續訊號VO1,VO2,VO3,其各自之訊號示意圖係如第7A圖、第7B圖及第7C圖所示。In addition, the measuring device disclosed in the present application is not limited to measuring a single wafer to be tested. In other words, with the measuring device disclosed in the present invention, it can be further used to measure more than one wafer 1 to be tested, and the device schematic is as shown in FIG. When the number of the test modules 20 is plural, the control host 10 is electrically coupled to each test module 20, and controls each test module 20 to be connected to each of the tested chips. 1 Performing the measurement procedure of step S401 to step S406, the measurement and analysis of the output signals of the plurality of wafers to be tested 1 can be simultaneously performed, thereby achieving the purpose of rapid measurement and parallel acquisition of multiple signals. In this embodiment, when the number of the wafers 1 to be tested is three, the control host can output the corresponding three consecutive signals VO1, VO2, and VO3, and the respective signal diagrams are as shown in FIG. 7A and FIG. 7B. Figure 7C shows.
是以,綜上所述,本創作所揭露之量測裝置,係為現今業界上創新且新穎之設計,其經證實係為迄今發展上可有效省卻習見量測多埠訊號所需時間之一種量測裝置。根據本創作之技術內容,此種量測裝置不僅首創有利用一控制主機同時控制開關模組與分析器進行量測之動作,以降低習見訊號分析器必須重複啟動之次數,藉此縮短測試時間。除此之外, 此種量測裝置更可一次性地擷取待測晶片所有的輸出訊號,並據以產生對應之一連續訊號,利用該連續訊號在同一時間軸上一次呈現所有輸出埠之輸出訊號,達到快速量測且訊號可連續且不間斷地呈現之優勢。Therefore, in summary, the measuring device disclosed in the present invention is an innovative and novel design in the industry today, which has been proven to be one of the time required to effectively eliminate the need to measure multiple signals. Measuring device. According to the technical content of the creation, the measuring device not only initiates the action of controlling the switch module and the analyzer by using a control host, but also reduces the number of times the analog signal analyzer must be repeatedly activated, thereby shortening the test time. . Other than that, The measuring device can capture all the output signals of the wafer to be tested at one time, and accordingly generate a corresponding continuous signal, and use the continuous signal to display the output signals of all the output 一次 on the same time axis, which is fast. Measurements and signals can be presented continuously and continuously.
以上所述之實施例僅係為說明本創作之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本創作之內容並據以實施,當不能以之限定本創作之專利範圍,即大凡依本創作所揭示之精神所作之均等變化或修飾,仍應涵蓋在本創作之專利範圍內。The embodiments described above are only for explaining the technical idea and characteristics of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement them according to the scope of the patent. That is, the equivalent changes or modifications made by the people in accordance with the spirit revealed by this creation should still be covered by the scope of the patent of this creation.
1‧‧‧待測晶片1‧‧‧Samps to be tested
10‧‧‧控制主機10‧‧‧Control host
20‧‧‧測試模組20‧‧‧Test module
202‧‧‧訊號產生器202‧‧‧Signal Generator
204‧‧‧開關模組204‧‧‧Switch Module
206‧‧‧訊號分析器206‧‧‧Signal Analyzer
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