TWM485601U - Control signal disturbed circuit structure - Google Patents
Control signal disturbed circuit structure Download PDFInfo
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- TWM485601U TWM485601U TW103206258U TW103206258U TWM485601U TW M485601 U TWM485601 U TW M485601U TW 103206258 U TW103206258 U TW 103206258U TW 103206258 U TW103206258 U TW 103206258U TW M485601 U TWM485601 U TW M485601U
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Description
本新型係有關於一種防治電信號受到干擾的電路結構,特別是指可以防治電路受到電磁波干擾(EMI)或射頻干擾(RFI)的困擾,及相同接地源所產生共模干擾的困擾,使電路、電源及系統的運作更正確、更正常。The present invention relates to a circuit structure for preventing electrical signals from being interfered, in particular, it can prevent the circuit from being disturbed by electromagnetic interference (EMI) or radio frequency interference (RFI), and the common mode interference generated by the same ground source, so that the circuit The power supply and system are operating correctly and more normally.
電路難免會受到各種內在因素或外來因素的干擾而影響到其運作的正確性。然而干擾類型通常按干擾模式不同,可分為共模干擾(Common-Mode Interference)和差模干擾(Differential-Mode Interference)。共模干擾和差模干擾是一種比較常用的分類方法。共摸干擾是信號對接地源的電位差,主要由電網串入、不同接地源之間的電位差及空間電磁輻射在信號線上感應的共態(同方向)電壓疊加所形成。共模電壓有時較大,特別是採用隔離性能差的電源供應器,輸送的共模電壓普遍較高。共模電壓透過不對稱電路可轉換成差模電壓,直接影響測控信號,造成原器件損壞〔這就是一些系統的輸出/輸入(I/O)模件損壞率較高的主要原因〕,這種共模干擾可為直流、亦可為交流。The circuit is inevitably affected by various internal factors or external factors, which affects the correctness of its operation. However, the interference type is usually classified into a common mode interference (Common-Mode Interference) and a differential mode interference (Differential-Mode Interference) according to the interference mode. Common mode interference and differential mode interference are a common classification method. The common touch interference is the potential difference between the signal and the ground source, which is mainly formed by the power grid stringing, the potential difference between different grounding sources and the common state (same direction) voltage induced by the space electromagnetic radiation on the signal line. The common mode voltage is sometimes large, especially with a power supply with poor isolation performance, and the common mode voltage delivered is generally higher. The common mode voltage can be converted into a differential mode voltage through an asymmetric circuit, which directly affects the measurement and control signals, causing damage to the original device (this is the main reason for the high damage rate of the output/input (I/O) modules of some systems]. Common mode interference can be either DC or AC.
差模干擾是指作用於信號兩極間的干擾電壓,主要由空間電磁場在信號間耦合感應及不平衡電路轉換共模干擾所形成的電壓,直接疊 加在信號上,直接影響測量與控制精度。習知電子裝置的電路佈署(Layout)大都是裸露於印刷電路板的表面,難以避免地會受到空間電磁場的耦合感應而造成電磁波干擾(Electromagnetic Interference,簡稱EMI)或射頻干擾(Radio Frequency Interference,簡稱RFI)的困擾。Differential mode interference refers to the interference voltage acting between the two poles of the signal. It is mainly composed of the space electromagnetic field coupled between the signals and the voltage formed by the unbalanced circuit to convert the common mode interference. Adding to the signal directly affects the measurement and control accuracy. Most of the circuit layouts of the conventional electronic devices are exposed on the surface of the printed circuit board, which is inevitably affected by the electromagnetic induction of the electromagnetic field (Electromagnetic Interference (EMI) or Radio Frequency Interference (Radio Frequency Interference). The trouble of RFI for short.
此外,由於電路的信號線、電源、系統等電子負載大都共接至相同接地源,因此容易產生共模干擾的困擾。In addition, since the electronic signals such as signal lines, power supplies, and systems of the circuit are all connected to the same ground source, it is easy to cause common mode interference.
本案之創作人有鑑於此,乃予研究創新,揭示出本新型所示之防治電信號受到干擾的電路結構。In view of this, the creators of this case have researched and innovated to reveal the circuit structure in which the prevention and control of electrical signals shown in the present invention are disturbed.
本新型之目的旨在於提供一種防治電信號受到干擾的電路結構,係包含至少兩層逐層疊接之絕緣層的電路板及附著於該電路板之至少一電迴路,且該電迴路之信號線係被遮藏於彼此疊接的任意兩層絕緣層之間,使行走於信號線之電信號不受到干擾者。The purpose of the present invention is to provide a circuit structure for preventing interference of an electrical signal, comprising: a circuit board comprising at least two layers of insulating layers connected to each other; and at least one electrical circuit attached to the circuit board, and a signal line of the electrical circuit It is hidden between any two layers of insulation layer that are overlapped with each other, so that the electrical signal traveling on the signal line is not disturbed.
本新型所揭示的防治電信號受到干擾的電路結構,係包含至少兩組電迴路及至少兩組接地源,而且每一組電迴路係各自單獨地與各自專屬的接地源相接,而且該等接地源係彼此互相隔離不相接,使行走於該信號線及電迴路之電信號均不受到干擾者。The circuit structure for preventing electrical signals from being disturbed by the present invention comprises at least two sets of electrical circuits and at least two sets of grounding sources, and each set of electrical circuits is individually connected to a respective dedicated grounding source, and the same The grounding sources are isolated from each other, so that the electrical signals traveling on the signal line and the electrical circuit are not disturbed.
本新型所揭示的防治電信號受到干擾的電路結構,係進一步包含至少一組供電於該電迴路之電源,其中該電源的接地端係各自單獨地與專屬的接地源相接,使行走於信號線及電迴路之電信號均不受到干擾者。The circuit structure for preventing electrical signals from being disturbed by the present invention further comprises at least one set of power sources for supplying power to the electric circuit, wherein the grounding ends of the power sources are individually connected to a dedicated ground source to enable walking signals. The electrical signals of the line and the electrical circuit are not subject to interference.
本新型所揭示的防治電信號受到干擾的電路結構,係配屬於一系統迴路,而且該系統迴路之接地端單獨地與各自專屬的接地源相接, 使行走於信號線、電迴路及系統迴路之電信號不受到干擾者。The circuit structure disclosed in the present invention for preventing and damaging electrical signals is assigned to a system loop, and the grounding ends of the system loops are individually connected to their respective grounding sources. The electrical signals that travel on the signal lines, electrical circuits, and system loops are not subject to interference.
本新型的可取實體,可由以下說明及所附各圖式,而得以明晰之。The preferred entities of the present invention can be clarified by the following description and the accompanying drawings.
(12)‧‧‧電路板(12)‧‧‧ boards
(13)(14)‧‧‧絕緣層(13) (14) ‧ ‧ insulation
(151)(152)(161)(162)(D-)(D+)(TX-)(TX+)(RX-)(RX+)‧‧‧信號線(151)(152)(161)(162)(D-)(D+)(TX-)(TX+)(RX-)(RX+)‧‧‧ Signal line
(GNDP)(GNDS)(GND1)(GND2)(GNDD)(GNDT)(GNDR)‧‧‧接地源(GNDP) (GNDS) (GND1) (GND2) (GNDD) (GNDT) (GNDR) ‧‧‧ Ground Source
(P)‧‧‧電源(P)‧‧‧Power
(S)‧‧‧系統迴路(S)‧‧‧System loop
第一圖:係本新型之第一實施例的立體分解圖。First Fig.: An exploded perspective view of a first embodiment of the present invention.
第二圖:係第一圖的立體組合圖。The second figure is a three-dimensional combination diagram of the first figure.
第三圖:係本新型之第二實施例的接地示意圖。Third: A schematic diagram of the grounding of the second embodiment of the present invention.
請參閱第一至三圖所示,本新型所提供之防治電信號受到干擾的電路結構,係包含至少兩層逐層疊接之絕緣層(13)(14)的電路板(12)及附著於該電路板(12)之至少一電迴路,且該電迴路之信號線(151)(152)(161)(162)(D-)(D+)(TX-)(TX+)(RX-)或(RX+)係被遮藏於彼此疊接的任意兩層絕緣層(13)(14)之間,使行走於信號線(151)(152)(161)(162)(D-)(D+)(TX-)(TX+)(RX-)或(RX+)之電信號不受到干擾者。Referring to the first to third figures, the circuit structure for preventing electrical signals from being disturbed by the present invention is a circuit board (12) comprising at least two layers of insulating layers (13) (14) laminated and connected to each other. At least one electrical circuit of the circuit board (12), and the signal line (151) (152) (161) (162) (D-) (D+) (TX-) (TX+) (RX-) of the electrical circuit or (RX+) is hidden between any two insulating layers (13) (14) that are overlapped with each other so as to walk on the signal line (151) (152) (161) (162) (D-) (D+) The electrical signal of (TX-)(TX+)(RX-) or (RX+) is not disturbed.
請參閱第三圖所示,本新型所揭示的防治電信號受到干擾的電路結構,係包含至少兩組電迴路及至少兩組接地源(GND1)及(GND2),而且每一組電迴路係各自單獨地與各自專屬的接地源(GND1)或(GND2)相接,而且該等接地源(GND1)及(GND2)係彼此互相隔離不相接,使行走於該信號線(151)(152)(161)(162)及電迴路之電信號均不受到干擾者。Referring to the third figure, the circuit structure for preventing electrical signals from being disturbed by the present invention includes at least two sets of electrical circuits and at least two sets of grounding sources (GND1) and (GND2), and each group of electrical circuits is Each of them is individually connected to a respective ground source (GND1) or (GND2), and the ground sources (GND1) and (GND2) are isolated from each other so as to be connected to the signal line (151) (152). ) (161) (162) and the electrical signals of the electrical circuit are not subject to interference.
請參閱第三圖所示,本新型所揭示的防治電信號受到干擾的電路結構,係進一步包含至少一組供電於該電迴路之電源(P),其中該電源 (P)的接地端係單獨地與專屬的接地源(GNDP)相接,使行走於信號線(151)(152)(161)(162)及電迴路之電信號均不受到干擾者。Referring to the third figure, the circuit structure for preventing electrical signals from being interfered by the present invention further comprises at least one set of power sources (P) for supplying power to the electric circuit, wherein the power source The ground terminal of (P) is individually connected to a dedicated ground source (GNDP) so that the electrical signals traveling on the signal lines (151) (152) (161) (162) and the electrical circuit are not disturbed.
本新型所揭示的防治電信號受到干擾的電路結構,係配屬於一系統迴路(S),而且該系統迴路(S)之接地端單獨地與各自專屬的接地源(GNDS)相接,使行走於信號線(151)(152)(161)(162)、電迴路及系統迴路(S)之電信號不受到干擾者。The circuit structure disclosed in the present invention for preventing electrical signals from being interfered is assigned to a system loop (S), and the grounding ends of the system loops (S) are individually connected to their respective grounding sources (GNDS) to enable walking. The electrical signals at the signal lines (151) (152) (161) (162), the electrical circuit, and the system loop (S) are not disturbed.
本新型所揭示的防治電信號受到干擾的電路結構,可於不違本新型之精神及範疇下予以修飾應用,本新型亦不予自限。The circuit structure disclosed in the present invention for preventing and damaging electrical signals can be modified and applied without departing from the spirit and scope of the present invention, and the present invention is not limited.
(12)‧‧‧電路板(12)‧‧‧ boards
(13)(14)‧‧‧絕緣層(13) (14) ‧ ‧ insulation
(D-)(D+)(TX-)(TX+)(RX-)(RX+)‧‧‧信號線(D-)(D+)(TX-)(TX+)(RX-)(RX+)‧‧‧ signal line
(GNDD)(GNDT)(GNDR)‧‧‧接地源(GNDD)(GNDT)(GNDR)‧‧‧ Ground Source
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TWI573523B (en) * | 2014-04-10 | 2017-03-01 | Joinsoon Electronic Manufacturing Co Ltd | Prevention and control of electrical signals are disturbed by the method and its circuit structure |
US10032493B2 (en) | 2015-01-07 | 2018-07-24 | Micron Technology, Inc. | Longest element length determination in memory |
US10043570B1 (en) | 2017-04-17 | 2018-08-07 | Micron Technology, Inc. | Signed element compare in memory |
US10146537B2 (en) | 2015-03-13 | 2018-12-04 | Micron Technology, Inc. | Vector population count determination in memory |
US10147467B2 (en) | 2017-04-17 | 2018-12-04 | Micron Technology, Inc. | Element value comparison in memory |
US10153008B2 (en) | 2016-04-20 | 2018-12-11 | Micron Technology, Inc. | Apparatuses and methods for performing corner turn operations using sensing circuitry |
US10409554B2 (en) | 2014-09-03 | 2019-09-10 | Micron Technology, Inc. | Multiplication operations in memory |
US10409555B2 (en) | 2014-09-03 | 2019-09-10 | Micron Technology, Inc. | Multiplication operations in memory |
US10409557B2 (en) | 2016-03-17 | 2019-09-10 | Micron Technology, Inc. | Signed division in memory |
US10540144B2 (en) | 2016-05-11 | 2020-01-21 | Micron Technology, Inc. | Signed division in memory |
US10593418B2 (en) | 2014-06-05 | 2020-03-17 | Micron Technology, Inc. | Comparison operations in memory |
US10607665B2 (en) | 2016-04-07 | 2020-03-31 | Micron Technology, Inc. | Span mask generation |
US11029951B2 (en) | 2016-08-15 | 2021-06-08 | Micron Technology, Inc. | Smallest or largest value element determination |
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- 2014-04-10 TW TW103206258U patent/TWM485601U/en unknown
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TWI573523B (en) * | 2014-04-10 | 2017-03-01 | Joinsoon Electronic Manufacturing Co Ltd | Prevention and control of electrical signals are disturbed by the method and its circuit structure |
US10593418B2 (en) | 2014-06-05 | 2020-03-17 | Micron Technology, Inc. | Comparison operations in memory |
US10409554B2 (en) | 2014-09-03 | 2019-09-10 | Micron Technology, Inc. | Multiplication operations in memory |
US10713011B2 (en) | 2014-09-03 | 2020-07-14 | Micron Technology, Inc. | Multiplication operations in memory |
US10705798B2 (en) | 2014-09-03 | 2020-07-07 | Micron Technology, Inc. | Multiplication operations in memory |
US10409555B2 (en) | 2014-09-03 | 2019-09-10 | Micron Technology, Inc. | Multiplication operations in memory |
US10593376B2 (en) | 2015-01-07 | 2020-03-17 | Micron Technology, Inc. | Longest element length determination in memory |
US10984841B2 (en) | 2015-01-07 | 2021-04-20 | Micron Technology, Inc. | Longest element length determination in memory |
US10032493B2 (en) | 2015-01-07 | 2018-07-24 | Micron Technology, Inc. | Longest element length determination in memory |
US11663005B2 (en) | 2015-03-13 | 2023-05-30 | Micron Technology, Inc. | Vector population count determination via comparsion iterations in memory |
US10146537B2 (en) | 2015-03-13 | 2018-12-04 | Micron Technology, Inc. | Vector population count determination in memory |
US10896042B2 (en) | 2015-03-13 | 2021-01-19 | Micron Technology, Inc. | Vector population count determination via comparison iterations in memory |
US10409557B2 (en) | 2016-03-17 | 2019-09-10 | Micron Technology, Inc. | Signed division in memory |
US10607665B2 (en) | 2016-04-07 | 2020-03-31 | Micron Technology, Inc. | Span mask generation |
US11437079B2 (en) | 2016-04-07 | 2022-09-06 | Micron Technology, Inc. | Span mask generation |
US10699756B2 (en) | 2016-04-20 | 2020-06-30 | Micron Technology, Inc. | Apparatuses and methods for performing corner turn operations using sensing circuitry |
US10153008B2 (en) | 2016-04-20 | 2018-12-11 | Micron Technology, Inc. | Apparatuses and methods for performing corner turn operations using sensing circuitry |
US10540144B2 (en) | 2016-05-11 | 2020-01-21 | Micron Technology, Inc. | Signed division in memory |
US11029951B2 (en) | 2016-08-15 | 2021-06-08 | Micron Technology, Inc. | Smallest or largest value element determination |
US11526355B2 (en) | 2016-08-15 | 2022-12-13 | Micron Technology, Inc. | Smallest or largest value element determination |
US10043570B1 (en) | 2017-04-17 | 2018-08-07 | Micron Technology, Inc. | Signed element compare in memory |
US10622034B2 (en) | 2017-04-17 | 2020-04-14 | Micron Technology, Inc. | Element value comparison in memory |
US10147467B2 (en) | 2017-04-17 | 2018-12-04 | Micron Technology, Inc. | Element value comparison in memory |
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