JP2015033119A - Printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an area of a printed circuit board small when an LC resonance type filter capable of reducing a common mode component, which is generated when a differential signal is transmitted, is formed by conductors of a printed wiring board.SOLUTION: Signal conductor patterns 211, 212 are disposed at a conductor layer 201 and a ground conductor pattern 213 is disposed at a conductor layer 203. A conductor pattern 221 is disposed at a conductor layer 202 and a conductor pattern 222 is disposed at a conductor layer 204. The signal conductor pattern 211 and the conductor pattern 221 are connected by a via conductor 231 and the signal conductor pattern 212 and the conductor pattern 222 are connected by a via conductor 232. At least parts of the conductor patterns 221, 222 overlap with the ground conductor pattern 213 when viewed in a Z direction. Further, at least parts of the conductor patterns 221, 222 overlap with each other.

Description

  The present invention relates to a printed circuit board including a printed wiring board used for transmitting differential signals.

  Recent digital copying machines and digital cameras require high-speed transmission of large-capacity digital signals in order to achieve high speed and high definition. Therefore, a differential signal transmission method capable of transmitting a large amount of data at high speed has been widely used.

  In the differential signal transmission method, a basic signal necessary for signal transmission is transmitted by a normal mode component in which the amplitude is approximately equal to each of the pair of signal lines and the polarities are inverted. In addition, the normal mode component includes a signal of a harmonic component of the frequency of the basic signal in addition to the component of the basic signal necessary for signal transmission. However, since the normal mode component cancels out the magnetic flux generated by the mutual current, radiation noise from the differential transmission path due to the harmonic component can be suppressed.

  On the other hand, in the differential signal transmission method, in addition to the normal mode component, a common mode component signal having the same polarity is also transmitted to the pair of signal lines. The common mode component is generated when the normal mode component is converted due to the unbalance property of the normal mode component caused by the transmission circuit that transmits the differential signal or the unbalance between the pair of signal lines. Further, in this common mode component, current flows in the same direction on a pair of signal lines, and the generated magnetic flux strengthens, so that radiation noise from the differential transmission path increases.

  As one of means for suppressing radiation noise caused by such a common mode component, Non-Patent Document 1 describes using an LC resonance type filter. The LC resonance type filter is a series resonance circuit in which an inductor and a capacitor are connected in series, and is individually connected to each signal line. By matching the resonance frequency composed of the inductance of the inductor and the capacitance of the capacitor with the frequency of the unnecessary harmonic component, the common mode component that is an unnecessary harmonic component is reduced. In this LC resonance type filter, when the differential signal becomes high speed, unnecessary harmonic components also become higher in frequency, and therefore, the resonance frequency of the LC resonance type filter needs to be set to a high value.

Tosaburo Sato “Transmission Circuit” Corona Publishing (June 30, 1963, P277)

  However, if an LC resonant filter is configured with a commercially available element (for example, a chip inductor or a chip capacitor), the value of the element needs to be reduced when the resonance frequency is in the high frequency band. It was difficult to obtain a desired resonance frequency. Therefore, when using a commercially available element, it may be difficult to suppress the common mode component.

  On the other hand, electrical and electronic devices such as digital multifunction peripherals and digital cameras have a strong demand for downsizing, so printed circuit boards used for electrical and electronic devices can also be used for mounting parts such as ICs. It is necessary to arrange wiring and the like in a higher density and a smaller area.

  Accordingly, the present invention provides a printed circuit board capable of constituting an LC resonant filter that can reduce the common mode component generated during transmission of a differential signal while realizing a high density and a small area of the printed wiring board. To do.

  The printed circuit board of the present invention transmits a pair of differential signals and a printed wiring board laminated via an insulator layer in the order of the first conductor layer, the second conductor layer, the third conductor layer, and the fourth conductor layer. And a transmission circuit mounted on the printed wiring board, the printed wiring board including the first conductor and the second signal terminal, and a ground terminal to which a ground potential is applied. A first signal conductor pattern disposed in a layer and electrically conducting to the first signal terminal; a second signal conductor pattern disposed in the first conductor layer and electrically conducting to the second signal terminal; A ground conductor pattern disposed on the third conductor layer and electrically conducting to the ground terminal, and at least a part of the ground conductor pattern overlaps with the second conductor layer in a direction perpendicular to the surface of the printed wiring board. A first conductor pattern arranged at a position, and a fourth conductor layer disposed at a position at least partially overlapping the ground conductor pattern and the first conductor pattern in a direction perpendicular to the surface of the printed wiring board in the fourth conductor layer. Two conductor patterns, a first via conductor that electrically connects the first signal conductor pattern and the first conductor pattern, the first conductor pattern and the ground conductor pattern, and the second conductor pattern; It has a 2nd via conductor which electrically connects a signal conductor pattern and the 2nd conductor pattern, It is characterized by the above-mentioned.

  According to the present invention, the occupied area occupied by the first and second conductor patterns can be reduced when viewed from the direction perpendicular to the surface of the printed wiring board, and the printed wiring board and thus the printed circuit board can be reduced in size. Can be realized. Furthermore, a desired resonance frequency can be obtained, and the amount of transmission of the common mode component in the first and second signal conductor patterns can be reduced.

It is explanatory drawing which shows schematic structure of the printed circuit board which concerns on 1st Embodiment. It is a circuit diagram which shows the equivalent circuit of the printed circuit board which concerns on 1st Embodiment. It is explanatory drawing which shows schematic structure of the printed circuit board which concerns on 2nd Embodiment. For the ratio _(r 1 _/ r ₂₎ is a graph showing the maximum value of the amount of generation of the common mode component. It is explanatory drawing which shows schematic structure of the printed circuit board which concerns on a comparative example.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is an explanatory diagram showing a schematic configuration of a printed circuit board according to the first embodiment of the present invention. FIG. 1A is a schematic diagram showing a schematic configuration of a printed circuit board, and FIG. 1B is a cross-sectional view showing a printed wiring board of the printed circuit board. FIG. 2 is a circuit diagram showing an equivalent circuit of the printed circuit board according to the first embodiment of the present invention.

  As shown in FIG. 1A, a printed circuit board 100 includes a printed wiring board 200, a transmission circuit 300 mounted on the printed wiring board 200, and a connector mounted on the printed wiring board 200 to which a cable 500 is connected. 400.

  The transmission circuit 300 transmits a pair of differential signals whose polarities are inverted to each other. The signal terminal 301 as a first signal terminal for transmitting one differential signal and the second differential signal for transmitting the other differential signal. And a signal terminal 302 as a two-signal terminal. The transmission circuit 300 includes a ground terminal 303 to which a ground potential is applied and a power supply terminal (not illustrated) to which a power supply potential is applied. The transmission circuit 300 operates when a DC voltage is applied between the power supply terminal and the ground terminal 303, and a pair of differential signals that are digital signals of a predetermined transmission rate [bps] from the pair of signal terminals 301 and 302. Is to send.

  Specifically, the transmission circuit 300 serializes a parallel signal, which is a digital signal indicating data, and outputs it as a differential signal. At that time, the transmission circuit 300 embeds a clock signal in the serialized data string and transmits it.

  The connector 400 is connected with a cable 500 for transmitting a pair of differential signals, which are digital signals, to a receiving circuit 600 (FIG. 2) mounted on another printed wiring board or another electronic device. The receiving circuit 600 receives a pair of differential signals (serial signals), deserializes them, and converts them into parallel signals. As a result, the receiving circuit 600 reproduces the clock and data.

  In clock-embedded serial transmission, data and a synchronous clock are serialized together, and data encoded so that the logic transition rate between the high level and the low level is 50% is transmitted. For this reason, the serial signal to be transmitted does not have a continuous low level or high level in multiple bits, and a repetitive waveform having a basic period of 1 bit appears dominantly.

  Therefore, from each signal terminal 301, 302, a common mode component observed at a frequency that is an integral multiple of a 1-bit period of the serial signal is output. The spectrum of a serial signal transmitted as a rectangular wave is represented by a sinc function and is known to have no spectrum at a frequency that is an integral multiple of a 1-bit period. That is, a common mode component is generated at a frequency where there is no spectrum of the transmission signal.

  Here, the frequency corresponding to the transmission rate of the digital signal is the fundamental frequency (repetition frequency) [Hz]. For example, when the transmission rate of the digital signal is 1 [Gbps], the fundamental frequency is 1 [GHz]. In other words, the fundamental frequency is a frequency corresponding to a cycle per bit.

  As shown in FIG. 1B, the printed wiring board 200 is configured by laminating at least four conductor layers, in the first embodiment, four conductor layers 201 to 204 via insulator layers 205 to 207. 4 layer substrate. In the first embodiment, the printed wiring board 200 includes a conductor layer 201 as a first conductor layer, a conductor layer 202 as a second conductor layer, a conductor layer 203 as a third conductor layer, and a conductor as a fourth conductor layer. The layers 204 are stacked in this order via insulator layers 205 to 207.

  The printed wiring board 200 has a signal conductor pattern 211 as a first signal conductor pattern that is disposed on the conductor layer 201 and is electrically connected to the signal terminal 301. The printed wiring board 200 has a signal conductor pattern 212 as a second signal conductor pattern that is disposed on the conductor layer 201 and is electrically connected to the signal terminal 302.

  Specifically, the signal conductor patterns 211 and 212 are conductor patterns formed in a strip shape. One end of the signal conductor pattern 211 in the longitudinal direction is joined to the signal terminal 301, and the other end is joined to a terminal (not shown) of the connector 400. One end of the signal conductor pattern 212 in the longitudinal direction is joined to the signal terminal 302, and the other end is joined to a terminal (not shown) of the connector 400. As a result, the pair of differential signals propagates through the pair of signal conductor patterns 211 and 212 and is transmitted from the connector 400 to the external receiving circuit 600.

  The printed wiring board 200 includes a ground conductor pattern 213 that is disposed on the conductor layer 203 and is electrically connected to the ground terminal 303. The ground conductor pattern 213 is a planar conductor pattern disposed over substantially the entire surface of the conductor layer 203. A ground conductor pattern 214 to which the ground terminal 303 of the transmission circuit 300 is joined is disposed on the conductor layer 201. The ground conductor pattern 213 and the ground conductor pattern 214 are electrically connected by the ground via conductor 215. Yes.

  In addition, the printed wiring board 200 is a conductor as a first conductor pattern disposed at a position at least partially overlapping the ground conductor pattern 213 in the Z direction perpendicular to the surface (XY plane) of the printed wiring board 200 in the conductor layer 202. A pattern 221 is included. Here, the Z direction is a stacking direction of the printed wiring boards 200.

  Further, the printed wiring board 200 has a conductor pattern 222 as a second conductor pattern disposed at a position at least partially overlapping the ground conductor pattern 213 and the conductor pattern 221 in the Z direction orthogonal to the XY plane in the conductor layer 204. . Specifically, the conductor pattern 221 and the conductor pattern 222 have portions facing each other with the insulator layers 206 and 207 and the ground conductor pattern 213 interposed therebetween. That is, the conductor pattern 222 is disposed so as to overlap at least a part of the conductor pattern 221 when projected onto the conductor layer 202 in the Z direction (stacking direction). These conductor patterns 221 and 222 are planar conductor patterns.

  Further, the printed wiring board 200 includes a via conductor 231 as a first via conductor that electrically connects the signal conductor pattern 211 and the conductor pattern 221. Furthermore, the printed wiring board 200 has a via conductor 232 as a second via conductor that is disposed in non-contact with the conductor pattern 221 and the ground conductor pattern 213 and electrically connects the signal conductor pattern 212 and the conductor pattern 222.

  The via conductors 215, 231, and 232 are conductors arranged in via holes formed in the printed wiring board 200 and extending in the Z direction orthogonal to the surface (XY plane) of the printed wiring board 200. In the first embodiment, the via conductors 215, 231 and 232 are formed in a columnar shape extending in the Z direction, but may be a cylindrical shape or another shape. The via conductor 232 is formed longer in the Z direction than the via conductor 231.

  In the first embodiment, the entire surface of the conductor pattern 221 on the side of the ground conductor pattern 213 is opposed to a region surrounded by the outer peripheral edge of the ground conductor pattern 213 with the insulator layer 206 interposed therebetween. That is, the entire projection image when the conductor pattern 221 is projected onto the conductor layer 203 in the Z direction is within the region surrounded by the outer peripheral edge of the ground conductor pattern 213. Further, the entire surface of the conductor pattern 222 on the side of the ground conductor pattern 213 is opposed to a region surrounded by the outer peripheral edge of the ground conductor pattern 213 with the insulator layer 207 interposed therebetween. That is, the entire projected image when the conductor pattern 222 is projected onto the conductor layer 203 in the Z direction is within the region surrounded by the outer peripheral edge of the ground conductor pattern 213.

  Further, in the first embodiment, the entire surface of the conductor pattern 222 on the side of the ground conductor pattern 213 faces the region surrounded by the outer peripheral edge of the conductor pattern 221. That is, the projection image when the conductor pattern 222 is projected onto the conductor layer 202 in the Z direction is in the region surrounded by the outer periphery of the conductor pattern 221.

The via conductor 231 and the via conductor 232 mainly function as inductance. On the other hand, the conductor pattern 221 and the ground conductor pattern 213 facing each other with the insulator layer 206 interposed therebetween mainly function as capacitance. In addition, the conductor pattern 222 and the ground conductor pattern 213 that face each other with the insulator layer 207 interposed therebetween mainly function as capacitance. That is, the signal conductor patterns 211 and 212 are connected to LC series resonance circuits (LC resonance type filters) Q ₁ and Q ₂ as shown in FIG. 2 branched from one end to the other end. .

Here, as shown in FIG. 2, the inductance of the via conductor 231 is L ₁ [H], and the inductance of the via conductor 232 is L ₂ [H]. The capacitance between the conductor pattern 221 and the ground conductor pattern 213 is C ₁ [F], and the capacitance between the conductor pattern 222 and the ground conductor pattern 213 is C ₂ [F]. Then, as shown in FIG. 2, LC series resonance circuits Q ₁ and Q _{2 in} which L ₁ and C ₁ and L ₂ and C ₂ are connected in series are formed.

The resonance frequency f _{1 of the} LC series resonance circuit Q _{1 and} the resonance frequency f ₂ of the LC series resonance circuit Q ₂ are:

と表される。

It is expressed.

At these resonance frequencies f ₁ and f ₂ , the impedance between the signal conductor patterns 211 and 212 and the ground conductor pattern 213 becomes small. Therefore, among the frequency components of the common mode component included in the pair of differential signals output from the transmission circuit 300, the common mode component that matches the resonance frequencies f ₁ and f ₂ of the LC series resonance circuits Q ₁ and Q ₂ is Effectively reduced. Theoretically, the peak frequency of the common mode component coincides with one of the fundamental frequency of the transmitted digital signal or an integer multiple of the fundamental frequency. Therefore, it is preferable to make the resonance frequencies f ₁ and f ₂ coincide with the fundamental frequency of the digital signal corresponding to the common mode component to be reduced or an integer multiple thereof.

However, depending on the environment around which the signal is transmitted, the peak frequency of the common mode component and the fundamental frequency of the transmitted digital signal may have an error of about ± 10%. Accordingly, the common mode component can be effectively reduced by setting the resonance frequencies f ₁ and f ₂ within the error range of ± 5% of the fundamental frequency of the transmitted digital signal or an integral multiple of the fundamental frequency. it can. In order to suppress the common mode component, it is not always necessary to match the resonance frequencies f ₁ and f ₂ with the fundamental frequency of the low digital signal or one of the integral multiples thereof, and an error of about ± 10%. If it is within the range, the common mode component can be reduced sufficiently effectively. Also from this point, it can be said that an error range of about ± 10% is an effective range.

According to the first embodiment, it is possible to obtain a desired resonance frequency in the LC series resonance circuits Q ₁ and Q ₂ by forming inductance and capacitance with the conductor of the printed wiring board 200. Therefore, the transmission amount of the common mode component in the signal conductor patterns 211 and 212 can be reduced, that is, radiation noise from the cable 500 and the like due to the common mode component can be reduced. Furthermore, when the printed wiring board 200 is viewed from the Z direction perpendicular to the XY plane, the area occupied by the conductor patterns 221 and 222 can be reduced, and the printed wiring board 200 and thus the printed circuit board 100 can be downsized. can do.

  In the first embodiment, the via conductor 232 is disposed through the conductor pattern 221 and the ground conductor pattern 213. Therefore, the occupied area occupied by the conductor patterns 221 and 222 can be further reduced when viewed from the Z direction perpendicular to the XY plane of the printed wiring board 200, and the printed wiring board 200 and thus the printed circuit board 100 can be further reduced in size. Can be realized.

  In the first embodiment, the insulator layer 206 and the insulator layer 207 are set to have the same thickness in the Z direction. In addition, the dielectric constants (relative dielectric constants) of the insulators (dielectrics) of the insulator layers 206 and 207 are also the same.

Furthermore, in order to reduce the common mode component more effectively, it is preferable to set the resonance frequency f ₁ = f ₂ . In order to set f ₁ = f ₂ , L ₁ × C ₁ = L ₂ × C ₂ may be set according to the equations (1) and (2). Theoretically, the common mode component can be reduced most effectively by setting the resonance frequency f ₁ = f ₂ . However, it is not always necessary to set the resonance frequency f ₁ = f _2, and the common mode component can be sufficiently effectively reduced within an error range of about ± 5%.

In the first embodiment, the thickness of the via conductor 231 and the via conductor 232, that is, the cross-sectional area of the via conductor 231 along the XY plane, and the cross-sectional area of the via conductor 232 along the XY plane are Are the same. Therefore, since the via conductor 232 is longer in the Z direction than the via conductor 231, the inductance L ₂ of the via conductor 232 is higher than the inductance L ₁ of the via conductor 231. That is, L ₁ <L ₂ . Therefore, an attempt to equalize the resonant frequency _f 1, _{f 2} of each LC series resonance circuit _Q 1, _{Q 2,} is smaller than the _{C 2 C 1, i.e.,} it is necessary to make _C 1> C _2.

When C ₁ > C ₂ , the distance between the conductor pattern 221 and the ground conductor pattern 213 is made smaller than the distance between the conductor pattern 222 and the ground conductor pattern 213, or the dielectric constant of the insulator layer 206 is changed to the insulator layer 207. It may be higher than the dielectric constant.

In the first embodiment, the insulator layers 206 and 207 have the same thickness and the same dielectric constant for ease of manufacture. The opposing area between the conductor pattern 222 and the ground conductor pattern 213 is smaller than the opposing area between the conductor pattern 221 and the ground conductor pattern 213. That is, the area of the conductor pattern 222 is made smaller than the area of the conductor pattern 221. In this way, C ₁ > C ₂ can be achieved with a simple configuration, and the common mode component propagating through the signal conductor patterns 211 and 212 can be effectively removed while the occupation area is small.

The common mode component that has flowed to the ground conductor pattern 213 through the LC series resonant circuits Q ₁ and Q ₂ is fed back to the ground terminal 303 of the transmission circuit 300 via the ground via conductor 215 and the ground conductor pattern 214.

  FIG. 5 is an explanatory diagram showing a schematic configuration of a printed circuit board according to a comparative example. In addition, about the structure similar to the printed circuit board 100, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  Two conductor patterns 1221 and 1222 having the same area and facing the ground conductor pattern 213 with an insulator layer interposed therebetween are arranged in the same conductor layer. The signal conductor pattern 211 and the conductor pattern 1221 are electrically connected by a via conductor 1231, and the signal conductor pattern 212 and the conductor pattern 1222 are electrically connected by a via conductor 1232. The via conductor 1231 and the via conductor 1232 are formed to have the same length and the same thickness. When formed in this way, the resonance frequency of each LC series resonance circuit can be made equal, but the occupied area of the entire conductor patterns 1221 and 1222 constituting these LC series resonance circuits is large when viewed from the Z direction.

  On the other hand, in the first embodiment, when the conductor pattern 222 is disposed on the conductor layer 204 different from the conductor pattern 221 and projected in the stacking direction (Z direction) of the printed wiring board 200, the conductor pattern 221 They are arranged so that they overlap. As a result, it is possible to reduce the occupied area occupied by the conductor patterns 221 and 222 in the printed wiring board 200 when viewed from the Z direction. And in this 1st Embodiment, it has a substantially equivalent common mode transmission amount with respect to a comparative example, and can reduce radiation noise effectively.

[Second Embodiment]
Next, a printed circuit board according to a second embodiment of the present invention will be described. FIG. 3 is an explanatory diagram showing a schematic configuration of a printed circuit board according to the second embodiment of the present invention. FIG. 3A is a schematic diagram showing a schematic configuration of a printed circuit board, and FIG. 3B is a cross-sectional view showing a printed wiring board of the printed circuit board. Note that in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 3A, a printed circuit board 100A includes a printed wiring board 200A, and a transmission circuit 300 and a connector 400 that are mounted on the printed wiring board 200A and have the same configuration as in the first embodiment. I have.

  As shown in FIG. 3B, the printed wiring board 200A is configured by laminating at least four conductor layers, in the second embodiment, four conductor layers 201 to 204 via insulator layers 205 to 207. 4 layer substrate.

  The printed wiring board 200A includes a pair of signal conductor patterns 211 and 212 and a ground conductor pattern 213, as in the first embodiment.

  In addition, the printed wiring board 200A is a conductor as a first conductor pattern disposed at a position at least partially overlapping the ground conductor pattern 213 in the Z direction perpendicular to the surface (XY plane) of the printed wiring board 200A in the conductor layer 202. It has a pattern 221A.

  Further, the printed wiring board 200A has a conductor pattern 222A as a second conductor pattern disposed at a position at least partially overlapping the ground conductor pattern 213 and the conductor pattern 221A in the Z direction orthogonal to the XY plane in the conductor layer 204. . Specifically, the conductor pattern 221A and the conductor pattern 222A have portions facing each other with the insulator layers 206 and 207 and the ground conductor pattern 213 interposed therebetween. That is, the conductor pattern 222A is arranged to overlap with at least a part of the conductor pattern 221A when projected onto the conductor layer 202 in the Z direction (stacking direction). These conductor patterns 221A and 222A are planar conductor patterns.

  Moreover, the printed wiring board 200A has a via conductor 231A as a first via conductor that electrically connects the signal conductor pattern 211 and the conductor pattern 221A. Furthermore, the printed wiring board 200A has a via conductor 232A as a second via conductor that is disposed in non-contact with the conductor pattern 221A and the ground conductor pattern 213 and electrically connects the signal conductor pattern 212 and the conductor pattern 222A. The via conductor 232A is formed longer in the Z direction than the via conductor 231A. In the second embodiment, the via conductors 231A and 232A are formed in a columnar shape extending in the Z direction. However, the via conductors 231A and 232A may have a cylindrical shape or another shape.

  In the second embodiment, the entire surface of the conductor pattern 221A on the side of the ground conductor pattern 213 is opposed to a region surrounded by the outer periphery of the ground conductor pattern 213 with the insulator layer 206 interposed therebetween. That is, the entire projected image when the conductor pattern 221A is projected onto the conductor layer 203 in the Z direction is within the region surrounded by the outer peripheral edge of the ground conductor pattern 213. Further, the entire surface of the conductor pattern 222A on the side of the ground conductor pattern 213 is opposed to a region surrounded by the outer periphery of the ground conductor pattern 213 with the insulator layer 207 interposed therebetween. That is, the entire projected image when the conductor pattern 222A is projected onto the conductor layer 203 in the Z direction is within the region surrounded by the outer peripheral edge of the ground conductor pattern 213.

  Further, in the second embodiment, the entire surface of the conductor pattern 222A on the side of the ground conductor pattern 213 faces the region surrounded by the outer peripheral edge of the conductor pattern 221A. That is, the projected image when the conductor pattern 222A is projected onto the conductor layer 202 in the Z direction is in the region surrounded by the outer peripheral edge of the conductor pattern 221A.

  The via conductor 231A and the via conductor 232A mainly function as inductance. On the other hand, the conductor pattern 221A and the ground conductor pattern 213 that are opposed to each other with the insulator layer 206 interposed therebetween mainly function as capacitance. Further, the conductor pattern 222A and the ground conductor pattern 213 facing each other with the insulator layer 207 interposed therebetween mainly function as capacitance. That is, each signal conductor pattern 211, 212 is connected to an LC series resonance circuit (LC resonance type filter) that branches from one end to the other end.

  According to the second embodiment, a desired resonance frequency can be obtained in the LC series resonance circuit by forming an inductance or a capacitance with the conductor of the printed wiring board 200A. Therefore, the transmission amount of the common mode component in the signal conductor patterns 211 and 212 can be reduced, that is, radiation noise from the cable 500 and the like due to the common mode component can be reduced. Furthermore, the occupied area occupied by the conductor patterns 221A and 222A can be reduced when viewed from the Z direction perpendicular to the XY plane of the printed wiring board 200A, and the printed wiring board 200A and thus the printed circuit board 100A can be downsized. can do.

  In the second embodiment, the via conductor 232A is disposed through the conductor pattern 221A and the ground conductor pattern 213. Therefore, when viewed from the Z direction perpendicular to the XY plane of the printed wiring board 200A, the occupied area occupied by the conductor patterns 221A and 222A can be further reduced, and the printed wiring board 200A and thus the printed circuit board 100A can be further reduced in size. Can be realized.

  In the second embodiment, the insulator layer 206 and the insulator layer 207 are set to have the same thickness in the Z direction. In addition, the dielectric constants (relative dielectric constants) of the insulators (dielectrics) of the insulator layers 206 and 207 are also the same.

Here, the inductance of the via conductor 231A is L ₁ [H], and the inductance of the via conductor 232A is L ₂ [H]. The capacitance between the conductor pattern 221A and the ground conductor pattern 213 is C ₁ [F], and the capacitance between the conductor pattern 222A and the ground conductor pattern 213 is C ₂ [F].

In the second embodiment, the printed wiring board 200A is the product of _{L 2} and _{C 2} is formed so as to approach the product of _{L 1} and _{C 1.} That is, L ₁ × C ₁ ≈L ₂ × C ₂ . In particular, L ₁ × C ₁ = L ₂ × C ₂ is preferable.

Here, if the inductance L ₂ is larger than the inductance L ₁ and the capacitance C ₂ is smaller than the capacitance C ₁ , an imbalance exists between the pair of signal conductor patterns 211 and 212. Therefore, the normal mode component may be converted into a common mode component, and a common mode component may be generated.

Therefore, in the second embodiment, the opposing area between the conductor pattern 221A and the ground conductor pattern 213 and the opposing area between the conductor pattern 222A and the ground conductor pattern 213 are the same (including substantially the same). That is, the area of the conductor pattern 221A and the area of the conductor pattern 222A are the same (including substantially the same). Therefore, it is more preferable that C ₁ ≈C ₂ and C ₁ = C ₂ .

Furthermore, in the second embodiment, the cross-sectional area of the via conductor 232A along the XY plane of the printed wiring board 200A is larger than the cross-sectional area of the via conductor 231A along the XY plane. In other words, in the second embodiment, as shown in FIG. 3, the diameter of the via conductor 232A is larger than the diameter of the via conductor 231A, L ₁ ≈L ₂ , and L ₁ = L _2. More preferred.

In the second embodiment, since L ₂ and L ₁ and C ₂ and C ₁ are substantially equal, it is difficult for the pair of signal conductor patterns 211 and 212 to be unbalanced. Therefore, it is possible to suppress the normal mode component from being converted into the common mode component, that is, the occurrence of the common mode component.

[Example 1]
As Example 1, a result of performing a three-dimensional electromagnetic field simulation on the printed circuit board 100 shown in FIG. 1 will be described. As a simulation model, the printed wiring board 200 has an outer width of 100 [mm], a length of 100 [mm], and a thickness of 1.6 [mm]. The conductor layer 201, which is the surface layer, is provided with a conductor having a width of 1 [mm], a length of 100 [mm], and a thickness of 0.035 [mm] as a pair of signal conductor patterns 211 and 212, and a pair of signal conductor patterns. The distance between 211 and 212 was set to 0.2 [mm]. Further, a planar ground conductor having a width of 100 [mm], a length of 100 [mm], and a thickness of 0.035 [mm] at a position of 1.5 [mm] from the conductor layer 201 in the lamination direction of the printed wiring board 200 A microstrip structure provided with a pattern 213 was formed. The dielectric was FR4 (relative permittivity 4.3), and the conductor was copper (conductivity 5.8 × 10 ⁷ [S / m]).

  The transmitter circuit 300 is set as the S parameter port 1a and port 1b, and the receiver circuit 600 is set as the S parameter port 2a and port 2b between the both ends of the pair of signal conductor patterns 211 and 212 and the ground conductor pattern 213. . That is, port 1a and port 2a are set in the signal conductor pattern 211, and port 1b and port 2b are set in the signal conductor pattern 212.

  In addition, a via conductor 231 having a diameter of 0.2 [mm] and a length of 1.4 [mm] is provided at the midpoint of the signal conductor pattern 211, and a thickness of 0.035 [mm] and one side are provided at the tip of the via conductor 231. A square conductor pattern 221 having a length of 5.34 [mm] was provided. The conductor pattern 221 is centered on the midpoint between the pair of signal conductor patterns 211 and 212.

  The interlayer thickness between the conductor pattern 221 and the ground conductor pattern 213 was 30 [μm]. Furthermore, a via conductor 232 having a diameter of 0.2 [mm] and a length of 1.53 [mm] is provided at the midpoint of the signal conductor pattern 212, and a thickness of 0.035 [mm] and one side are provided at the tip of the via conductor 232. A square conductor pattern 222 having a length of 5.08 [mm] was provided. The interlayer thickness between the conductor pattern 222 and the ground conductor pattern 213 was 30 [μm]. The conductor pattern 222 is centered on the midpoint between the pair of signal conductor patterns 211 and 212. The via conductor 232 is not connected to the conductor pattern 221 and the ground conductor pattern 213.

  Further, the printed circuit board of the comparative example shown in FIG. 5 was similarly modeled. Only differences from the simulation model of the first embodiment will be described. A via conductor 1231 having a diameter of 0.2 [mm] and a length of 1.4 [mm] is provided at the midpoint of the signal conductor pattern 211, and a thickness of 0.035 [mm] and the length of one side is provided at the tip of the via conductor 1231. A square conductor pattern 1221 having a length of 5.34 [mm] was provided.

  Further, a via conductor 1232 having a diameter of 0.2 [mm] and a length of 1.4 [mm] is provided at the midpoint of the signal conductor pattern 212, and a thickness of 0.035 [mm] and one side are provided at the tip of the via conductor 1232. A square conductor pattern 1222 having a length of 5.34 [mm] was provided. The interval between the conductor patterns 1221 and 1222 was set to 0.1 [mm].

  As an example, each model was dimensioned so that the resonance frequency was 1 [GHz].

  Here, for each model, in order to clarify the reduction capability with respect to the common mode component, the transmission amount with respect to the common mode component (Scc21 of the mixed mode S parameter) was obtained by simulation.

  Table 1 shows the transmission amount of the common mode component at the resonance frequency of 1 [GHz] in the comparative example and the example 1.

  From Table 1, in the printed circuit board of Example 1, the transmission amount of the common mode component at the resonance frequency 1 [GHz] is the transmission amount of the common mode component at the resonance frequency 1 [GHz] of the printed circuit board of the comparative example. In comparison, it can be seen that the levels are almost the same.

  In other words, Example 1 has substantially the same common mode transmission amount at the resonance frequency as compared with the comparative example, and the occupied area occupied by the conductor patterns 221 and 222 in the printed circuit board 100 can be reduced. It is.

[Example 2]
As Example 2, the result of performing a three-dimensional electromagnetic simulation on the printed circuit board 100A shown in FIG. 3 will be described. As for the simulation model, only the parts different from the model used in the first embodiment will be described.

  A via conductor 232A having a diameter of 0.24 [mm] and a length of 1.53 [mm] is provided at the midpoint of the signal conductor pattern 212, and a thickness of 0.035 [mm] and the length of one side is provided at the tip of the via conductor 232A. A square conductor pattern 222A having a length of 5.34 [mm] was provided. The conductor pattern 221A had the same conditions as the conductor pattern 221 of Example 1, and the via conductor 231A had the same conditions as the via conductor 231 of Example 1. As an example, the dimensions are determined so that the resonance frequency is 1 [GHz].

  About Example 1 and Example 2, in order to compare the generation amount of the common mode component, the generation amount of the common mode component (Scd21 of the mixed mode S parameter) was obtained by simulation. Table 2 shows the maximum value of the generation amount of the common mode component in Example 1 and Example 2.

  From Table 2, it can be seen that Example 2 further suppresses the generation amount of the common mode component as compared with Example 1.

  Next, the results of performing a three-dimensional electromagnetic field simulation to define the diameter range of the via conductor 232A to be thickened will be described. As for the simulation model, only the parts different from the model used in the first embodiment will be described.

  A via conductor 232A having a diameter of 0.32 [mm] and a length of 1.53 [mm] is provided at the midpoint of the signal conductor pattern 212, and a thickness of 0.035 [mm] and the length of one side is provided at the tip of the via conductor 232A. A square conductor pattern 222A having a length of 5.7 mm was provided. As an example, the dimensions are determined so that the resonance frequency is 1 [GHz].

It is assumed that the length of the via conductor 231A in the Z direction is l ₁ , the length of the via conductor 232A in the Z direction is l ₂ , the diameter of the via conductor 231A is r ₁ , and the diameter of the via conductor 232A is r ₂ .

Regarding Example 1 and Example 2, FIG. 4 shows a graph in which the horizontal axis represents the ratio of r ₂ and r ₁ (r ₂ / r ₁ ), and the vertical axis represents the maximum amount of common mode component generated.

Let the value of the ratio of r ₂ and r _{1 be} the square of the ratio of l ₂ and l ₁

で表すことができる。そのため、ヴィア導体の長さが変わった場合においても、上記範囲が変わることは無い。

Can be expressed as Therefore, even when the length of the via conductor changes, the above range does not change.

From FIG. 4, when the value of the ratio of r ₂ and r ₁ increases, the generation amount of the common mode component is suppressed, and when the value of the ratio of r ₂ and r ₁ continues to increase, the common mode It can also be seen that the amount of components generated increases.

That is, the value of the ratio of r ₂ and r ₁ is

であれば、実施例１と比較して、コモンモード成分の発生量を抑制することができることが分かる。

Then, it can be seen that the amount of the common mode component generated can be suppressed as compared with the first embodiment.

Here, the value of the ratio of r ₂ and r _{1 is} the square of the ratio of l ₂ and l ₁

で表せることについて説明する。

I will explain what can be expressed.

  In general, since the inductance of a linear conductor such as a via is approximately inversely proportional to the diameter and proportional to the length, the relational expression can be expressed as shown in Expression (3).

  Here, L represents the inductance of the linear conductor, r represents the diameter of the linear conductor, and l represents the length of the linear conductor.

Considering the case of L ₁ = L ₂ , from equation (3),

となるので、以下の式（５）に示すような関係式を求めることができる。

Therefore, a relational expression as shown in the following expression (5) can be obtained.

In general, if the reduction effect is 6 dB, radiation noise is suppressed. Here, from FIG. 4, the value of the ratio of r ₂ and r ₁ , which is reduced by 6 dB compared to Example 1, is

となる。つまり、より好ましくは、

It becomes. That is, more preferably,

であれば、コモンモード成分の発生量をより効果的に抑制することが可能である。

If so, it is possible to more effectively suppress the generation amount of the common mode component.

  The present invention is not limited to the embodiments and examples described above, and many modifications can be made by those having ordinary knowledge in the art within the technical idea of the present invention.

  In the first and second embodiments, the description has been given of the case where one LC resonance type filter structure including a via conductor, a conductor pattern, and a ground conductor pattern is provided for each signal conductor pattern. Not what you want. Since there are a plurality of unnecessary harmonics of the differential signal to be transmitted, a plurality of LC resonance filter structures may be provided in accordance with the frequency.

  Moreover, although the said 1st and 2nd embodiment demonstrated the case where a printed wiring board had four conductor layers, this invention is applicable also to a printed wiring board with five or more conductor layers. In this case, the first conductor layer and the fourth conductor layer may be inner conductor layers instead of the surface conductor layers as in the first and second embodiments.

  In the first and second embodiments, the case where the via conductors 232 and 232A penetrate the conductor patterns 221 and 221A and the ground conductor pattern 213 has been described. Good.

DESCRIPTION OF SYMBOLS 100 ... Printed circuit board, 200 ... Printed wiring board, 201 ... Conductor layer (1st conductor layer), 202 ... Conductor layer (2nd conductor layer), 203 ... Conductor layer (3rd conductor layer), 204 ... Conductor layer ( 4th conductor layer), 211... Signal conductor pattern (first signal conductor pattern), 212... Signal conductor pattern (second signal conductor pattern), 213... Ground conductor pattern, 221 .. conductor pattern (first conductor pattern), 222 ... Conductor pattern (second conductor pattern), 231 ... Via conductor (first via conductor), 232 ... Via conductor (second via conductor), 300 ... Transmission circuit, 301 ... Signal terminal (first signal terminal), 302 ... Signal terminal (second signal terminal), 303 ... Ground terminal

Claims (11)

A printed wiring board laminated via an insulator layer in the order of the first conductor layer, the second conductor layer, the third conductor layer, and the fourth conductor layer;
A first signal terminal that transmits a pair of differential signals, a second signal terminal, a ground terminal to which a ground potential is applied, and a transmission circuit mounted on the printed wiring board,
The printed wiring board is
A first signal conductor pattern disposed on the first conductor layer and electrically conducting to the first signal terminal;
A second signal conductor pattern disposed in the first conductor layer and electrically conducting to the second signal terminal;
A ground conductor pattern disposed in the third conductor layer and electrically conducting to the ground terminal;
A first conductor pattern disposed at a position at least partially overlapping the ground conductor pattern in a direction perpendicular to the surface of the printed wiring board in the second conductor layer;
A second conductor pattern disposed at a position at least partially overlapping the ground conductor pattern and the first conductor pattern in a direction orthogonal to the surface of the printed wiring board in the fourth conductor layer;
A first via conductor that electrically connects the first signal conductor pattern and the first conductor pattern;
A print having a second via conductor that is disposed in contact with the first conductor pattern and the ground conductor pattern and electrically connects the second signal conductor pattern and the second conductor pattern. Circuit board.   The printed circuit board according to claim 1, wherein the second via conductor is disposed through the first conductor pattern and the ground conductor pattern. The inductance of the first via conductor is L ₁ , the inductance of the second via conductor is L ₂ , the capacitance between the first conductor pattern and the ground conductor pattern is C ₁ , and the second conductor pattern and the ground conductor pattern are when the capacitance was C _2, the resonance frequency f ₁ represented by the following formula (1) of the series resonant circuit formed with the first via conductors in the first conductor pattern, and the first via conductor wherein The value of the resonance frequency f _{2 represented} by the following equation (2) of the series resonance circuit formed by the first conductor pattern is transmitted from the transmission circuit to the first signal conductor pattern and the second signal conductor pattern. The frequency is within ± 10% of the fundamental frequency of the digital signal or one of the integral multiples of the fundamental frequency. Printed circuit board according to Motomeko 1 or 2.

  In the printed wiring board, the product of the inductance of the second via conductor and the capacitance of the second conductor pattern and the ground conductor pattern is the inductance of the first via conductor, the first conductor pattern, and the ground. 4. The printed circuit board according to claim 1, wherein the printed circuit board is within a range of ± 5% of a product of the capacitance of the conductor pattern and the capacitance. 5. The inductance of the first via conductor is L ₁ , the inductance of the second via conductor is L ₂ , the capacitance between the first conductor pattern and the ground conductor pattern is C ₁ , and the second conductor pattern and the ground conductor pattern are Let C _{2 be} the capacitance of
The printed circuit board according to claim 4, wherein L ₁ × C ₁ = L ₂ × C ₂ .   6. The printed circuit board according to claim 4, wherein an opposing area between the second conductor pattern and the ground conductor pattern is smaller than an opposing area between the first conductor pattern and the ground conductor pattern.   The cross-sectional area of the cross section along the surface of the printed wiring board in the first via conductor and the cross-sectional area of the cross section along the surface of the printed wiring board in the second via conductor are the same. Item 7. The printed circuit board according to item 6.   The cross-sectional area of the cross section along the surface of the printed wiring board in the second via conductor is larger than the cross-sectional area of the cross section along the surface of the printed wiring board in the first via conductor. 5. A printed circuit board according to 5.   9. The printed circuit board according to claim 8, wherein an opposing area between the first conductor pattern and the ground conductor pattern and an opposing area between the second conductor pattern and the ground conductor pattern are the same. . The diameter of the first via conductor is r ₁ , the length of the first via conductor in the direction perpendicular to the surface of the printed wiring board is l ₁ , the diameter of the second via conductor is r ₂ , and the second via conductor is the length in the direction perpendicular to the plane of the printed circuit board when the l ₂ in,
The printed wiring board is

The printed circuit board according to claim 9, wherein the printed circuit board is formed so as to satisfy the following requirements. The printed wiring board is

The printed circuit board according to claim 10, wherein the printed circuit board is formed so as to satisfy the above requirement.

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