TWM478913U - Semiconductor structure - Google Patents
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- TWM478913U TWM478913U TW102212447U TW102212447U TWM478913U TW M478913 U TWM478913 U TW M478913U TW 102212447 U TW102212447 U TW 102212447U TW 102212447 U TW102212447 U TW 102212447U TW M478913 U TWM478913 U TW M478913U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Abstract
Description
本新型創作是有關於一種半導體結構,且特別是有關於一種可增加結構可靠度的半導體結構。The novel creation is related to a semiconductor structure, and in particular to a semiconductor structure that can increase structural reliability.
圖1繪示為習知發光二極體半導體結構的立體示意圖。請參考圖1,一般而言,發光二極體半導體結構10a包括一基板11和一配置於基板11上的磊晶結構12,其中磊晶結構12包括一主要出光的突出部22和一基部24。發光二極體半導體結構10a透過在磊晶結構12上配置的電極(未繪示)來提供電能,便可利用光電效應而發光。FIG. 1 is a schematic perspective view of a conventional light emitting diode semiconductor structure. Referring to FIG. 1 , in general, the LED semiconductor structure 10 a includes a substrate 11 and an epitaxial structure 12 disposed on the substrate 11 , wherein the epitaxial structure 12 includes a main light-emitting protrusion 22 and a base portion 24 . . The light-emitting diode semiconductor structure 10a transmits electric energy through an electrode (not shown) disposed on the epitaxial structure 12, and can emit light by using a photoelectric effect.
在發光二極體半導體結構10a的製作過程中,蝕刻作業是常使用到的一項技術。然而,由於一般發光二極體半導體結構10a中主要出光的突出部22相鄰的側邊皆呈直角設計,此時相鄰側邊直角的交界處13因為過於尖突,容易在蝕刻的作用下導致交界處13產生塌陷的現象。如此一來,將會降低發光二極體半導體結構10a的發光結構可靠度,進而影響發光效率。In the fabrication of the light-emitting diode semiconductor structure 10a, etching is a commonly used technique. However, since the adjacent sides of the protruding portions 22 which are mainly light-emitting in the general-purpose LED semiconductor structure 10a are designed at right angles, the boundary 13 of the right-side orthogonal angles is too sharp and easy to be etched. This causes the junction 13 to collapse. As a result, the reliability of the light-emitting structure of the light-emitting diode semiconductor structure 10a is reduced, thereby affecting the luminous efficiency.
本新型創作提供一種半導體結構,具有較佳的結構可靠度。The novel creation provides a semiconductor structure with better structural reliability.
本新型創作的半導體結構,其包括一基板與一半導體層。半導體層配置於基板上,且具有一基部以及位於基部上的一突出部。突出部在俯視時具有一上表面,而上表面具有多個側邊,其中至少兩個相鄰側邊之間具有一平切角(beveled edge)。The novel semiconductor structure is composed of a substrate and a semiconductor layer. The semiconductor layer is disposed on the substrate and has a base and a protrusion on the base. The projection has an upper surface when viewed from above, and the upper surface has a plurality of sides, wherein at least two adjacent sides have a beveled edge therebetween.
在本新型創作的一實施例中,上述的兩個相鄰側邊之間皆有一平切角。In an embodiment of the present invention, the two adjacent sides have a flat cut angle therebetween.
在本新型創作的一實施例中,上述的突出部具有多個側表面,至少兩個相鄰側表面之間具有一斜切面。In an embodiment of the present invention, the protrusion has a plurality of side surfaces, and at least two adjacent side surfaces have a chamfered surface therebetween.
在本新型創作的一實施例中,上述的半導體層包括一第一型半導體層、一發光層以及一第二型半導體層。發光層位於第一型半導體層與第二型半導體層之間,而第一型半導體層位於基板與發光層之間。第一型半導體層的一部分定義出基部,而第一型半導體層的另一部分、發光層以及第二型半導體層定義出突出部。In an embodiment of the present invention, the semiconductor layer includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer. The light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer, and the first type semiconductor layer is located between the substrate and the light emitting layer. A portion of the first type semiconductor layer defines a base, and another portion of the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer define a protrusion.
在本新型創作的一實施例中,上述的半導體層的側壁、基板的側壁或半導體層的側壁與基板的側壁為一粗糙表面。In an embodiment of the present invention, the sidewall of the semiconductor layer, the sidewall of the substrate or the sidewall of the semiconductor layer and the sidewall of the substrate are a rough surface.
本新型創作的半導體結構,其包括一基板與一半導體層。半導體層配置於基板上,且具有一基部以及位於基部上的一 突出部。突出部在俯視時具有一上表面,而上表面具有多個側邊,其中至少兩個相鄰側邊之間具有一導角(chamfer angle)。導角的兩端點的連線與導角定義出一封閉區域,導角的端點的連線與對應的側邊的延伸方向定義出一三角形。封閉區域的面積小於三角形的面積的0.8倍。The novel semiconductor structure is composed of a substrate and a semiconductor layer. The semiconductor layer is disposed on the substrate and has a base and a base on the base Highlights. The projection has an upper surface when viewed from above, and the upper surface has a plurality of sides with a chamfer angle between at least two adjacent sides. The line connecting the two ends of the lead angle defines a closed area, and the line connecting the end points of the lead angle defines a triangle with the extending direction of the corresponding side. The area of the enclosed area is less than 0.8 times the area of the triangle.
本新型創作的一實施例中,上述的導角為一圓角(round angle)。In an embodiment of the novel creation, the lead angle is a round angle.
本新型創作的一實施例中,上述的上表面的兩個相鄰側邊之間皆有圓角。In an embodiment of the present invention, the upper surface of the upper surface has rounded corners therebetween.
本新型創作的一實施例中,上述的圓角的曲率半徑介於10微米至30微米之間。In an embodiment of the present invention, the radius of curvature of the rounded corners is between 10 microns and 30 microns.
在本新型創作的一實施例中,上述的圓角包括一外凸圓角(protrusive round angle)或一內凹圓角(recessive round angle)。In an embodiment of the novel creation, the rounded corners include a protruding round angle or a recessive round angle.
在本新型創作的一實施例中,上述的突出部具有多個側表面,至少兩個相鄰側表面之間具有一圓切面。In an embodiment of the present invention, the protrusion has a plurality of side surfaces, and at least two adjacent side surfaces have a circular cut surface therebetween.
在本新型創作的一實施例中,上述的導角的弧線包括圓形弧線、橢圓弧線、拋物曲線或雙曲線。In an embodiment of the novel creation, the arc of the lead angle includes a circular arc, an elliptical arc, a parabola or a hyperbola.
在本新型創作的一實施例中,上述的半導體層包括一第一型半導體層、一發光層以及一第二型半導體層。發光層位於第一型半導體層與第二型半導體層之間,而第一型半導體層位於基板與發光層之間。第一型半導體層的一部分定義出基部,而第一型半導體層的另一部分、發光層以及第二型半導體層定義出突出 部。In an embodiment of the present invention, the semiconductor layer includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer. The light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer, and the first type semiconductor layer is located between the substrate and the light emitting layer. A portion of the first type semiconductor layer defines a base, and another portion of the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer define a protrusion unit.
在本新型創作的一實施例中,上述的半導體層的側壁、基板的側壁或半導體層的側壁與基板的側壁為一粗糙表面。In an embodiment of the present invention, the sidewall of the semiconductor layer, the sidewall of the substrate or the sidewall of the semiconductor layer and the sidewall of the substrate are a rough surface.
基於上述,由於本新型創作的半導體層具有平切角或導角的設計,因此可以避免習知突出部相鄰側邊的直角設計而導致結構崩裂的問題發生。簡言之,本新型創作的半導體結構可具有較佳的結構可靠度。Based on the above, since the semiconductor layer created by the present invention has a flat cut angle or a guide angle design, it is possible to avoid the problem that the structure is cracked due to the right angle design of the adjacent side edges of the conventional protruding portion. In short, the novel semiconductor structure created by the present invention can have better structural reliability.
為讓本新型創作的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will become more apparent and understood from the following description.
10a‧‧‧發光二極體半導體結構10a‧‧‧Light emitting diode semiconductor structure
11‧‧‧基板11‧‧‧Substrate
12‧‧‧磊晶結構12‧‧‧ Epitaxial structure
13‧‧‧交界處13‧‧‧ Junction
22‧‧‧突出部22‧‧‧Protruding
24‧‧‧基部24‧‧‧ base
100a、100b、100c‧‧‧半導體結構100a, 100b, 100c‧‧‧ semiconductor structure
110‧‧‧基板110‧‧‧Substrate
110a‧‧‧側壁110a‧‧‧ Sidewall
120a、120b、120c‧‧‧半導體層120a, 120b, 120c‧‧‧ semiconductor layer
122、122c‧‧‧基部122, 122c‧‧‧ base
124a、124b、124c‧‧‧突出部124a, 124b, 124c‧‧‧ protruding parts
125a、125b‧‧‧側邊125a, 125b‧‧‧ side
125s1、125s2‧‧‧側表面125s1, 125s2‧‧‧ side surface
126a‧‧‧導角126a‧‧‧ lead angle
126a1、126a2‧‧‧端點126a1, 126a2‧‧‧ endpoint
126b‧‧‧圓切面126b‧‧‧round cut
127a‧‧‧平切角127a‧‧‧cut angle
127b‧‧‧斜切面127b‧‧‧ chamfered surface
128a、128b‧‧‧上表面128a, 128b‧‧‧ upper surface
129c、129c1、129c2‧‧‧側壁129c, 129c1, 129c2‧‧‧ side wall
L1、L2‧‧‧延伸方向L1, L2‧‧‧ extension direction
L3‧‧‧連線L3‧‧‧ connection
S1‧‧‧第一型半導體層S1‧‧‧ first type semiconductor layer
S11‧‧‧第一型半導體的一部分Part of the S11‧‧‧ first-type semiconductor
S12‧‧‧第一型半導體的另一部分S12‧‧‧Another part of the first type of semiconductor
S2‧‧‧第二型半導體層S2‧‧‧Second type semiconductor layer
E‧‧‧發光層E‧‧‧Lighting layer
A1‧‧‧封閉區域A1‧‧‧closed area
A2‧‧‧三角形A2‧‧‧ triangle
圖1繪示為習知發光二極體半導體結構的立體示意圖。FIG. 1 is a schematic perspective view of a conventional light emitting diode semiconductor structure.
圖2A繪示為本新型創作的一實施例的一種半導體結構的立體示意圖。2A is a perspective view of a semiconductor structure according to an embodiment of the present invention.
圖2B繪示為圖2A之半導體結構的俯視示意圖。2B is a top plan view of the semiconductor structure of FIG. 2A.
圖3A繪示為本新型創作的另一實施例的一種半導體結構的立體示意圖。3A is a perspective view of a semiconductor structure according to another embodiment of the present invention.
圖3B繪示為圖3A之半導體結構的俯視示意圖。3B is a top plan view of the semiconductor structure of FIG. 3A.
圖4繪示為本新型創作的另一實施例的一種半導體結構的剖面示意圖。4 is a cross-sectional view showing a semiconductor structure of another embodiment of the present invention.
圖2A繪示為本新型創作的一實施例的一種半導體結構的立體示意圖。圖2B繪示為圖2A之半導體結構的俯視示意圖。請同時參考圖2A與圖2B,在本實施例中,半導體結構100a包括一基板110與一半導體層120a。半導體層120a配置於基板110上,且具有一基部122以及位於基部122上的一突出部124a。突出部124a在俯視時具有一上表面128a,而上表面128a具有多個側邊125a,其中至少兩個相鄰側邊125a之間具有一平切角127a。2A is a perspective view of a semiconductor structure according to an embodiment of the present invention. 2B is a top plan view of the semiconductor structure of FIG. 2A. Referring to FIG. 2A and FIG. 2B simultaneously, in the embodiment, the semiconductor structure 100a includes a substrate 110 and a semiconductor layer 120a. The semiconductor layer 120a is disposed on the substrate 110 and has a base portion 122 and a protruding portion 124a on the base portion 122. The projection 124a has an upper surface 128a in plan view and the upper surface 128a has a plurality of sides 125a with a flattening angle 127a between at least two adjacent sides 125a.
更具體來說,在本實施例中,基板110例如是一藍寶石基板,但並不以此為限。半導體層120a包括一第一型半導體層S1、一發光層E以及一第二型半導體層S2。第一型半導體層S1例如為一N型半導體層,而第二型半導體層S2例如為一P型半導體層,於此並不加以限制。發光層E位於第一型半導體層S1與第二型半導體層S2之間,而第一型半導體層S1配置於基板110和發光層E之間。如圖1A所示,第一型半導體層S1的一部分S11定義出基部122,而第一型半導體層S1的另一部分S12、發光層E以及第二型半導體層S2定義出突出部124a。特別是,突出部124a於基板110上的正投影面積小於基部122於基板110上的正投影面積。More specifically, in the embodiment, the substrate 110 is, for example, a sapphire substrate, but is not limited thereto. The semiconductor layer 120a includes a first type semiconductor layer S1, a light emitting layer E, and a second type semiconductor layer S2. The first type semiconductor layer S1 is, for example, an N type semiconductor layer, and the second type semiconductor layer S2 is, for example, a P type semiconductor layer, which is not limited thereto. The light emitting layer E is located between the first type semiconductor layer S1 and the second type semiconductor layer S2, and the first type semiconductor layer S1 is disposed between the substrate 110 and the light emitting layer E. As shown in FIG. 1A, a portion S11 of the first type semiconductor layer S1 defines a base portion 122, and another portion S12 of the first type semiconductor layer S1, the light emitting layer E, and the second type semiconductor layer S2 define a protruding portion 124a. In particular, the orthographic projection area of the protrusion 124a on the substrate 110 is smaller than the orthographic area of the base 122 on the substrate 110.
本實施例的半導體層120a的突出部124a的相鄰兩側邊125a之間至少具有一平切角127a的設計。更詳細地說,突出部124a具有多個側表面125s1,且至少兩個相鄰側表面125s1之間具 有一斜切面127b。也就是說,突出部124a的上表面128a之邊角有平切角的設計,使得突出部124a的側面125s1具有斜切面127b。因此,相較於習知突出部22相鄰側邊皆為直角,使交界處13過於尖突的設計,本實施例的半導體層120a可利用平切角127a的設計讓交處界多一斜切面127b做為緩衝,因此在經過蝕刻製程後,不會因為過於尖突產生塌陷現象,藉此提高半導體層120a的結構強度。如此一來,本實施例的半導體結構100a可具有較佳的結構可靠度。The adjacent side edges 125a of the protruding portion 124a of the semiconductor layer 120a of the present embodiment have at least a flat cut angle 127a. In more detail, the protrusion 124a has a plurality of side surfaces 125s1 and between at least two adjacent side surfaces 125s1 There is a chamfered surface 127b. That is, the corner of the upper surface 128a of the projection 124a has a flat cut angle design such that the side surface 125s1 of the projection 124a has a chamfered surface 127b. Therefore, compared with the design that the adjacent side of the conventional protruding portion 22 is a right angle and the interface 13 is too sharp, the semiconductor layer 120a of the embodiment can utilize the design of the flattening angle 127a to make the intersection boundary more oblique. Since the cut surface 127b serves as a buffer, after the etching process, the collapse phenomenon does not occur due to excessive sharpness, thereby increasing the structural strength of the semiconductor layer 120a. As such, the semiconductor structure 100a of the present embodiment can have better structural reliability.
值得一提的是,雖然在本實施例中相鄰兩側邊125a之間皆具有平切角127a的設計,但於其他未繪示的實施例中,亦可僅於部分側邊125a之間設置平切角127a,仍屬於本新型創作可採用的技術方案,不脫離本新型創作所欲保護的範圍。It should be noted that although in the embodiment, the design of the flat cutting angle 127a is provided between the adjacent side edges 125a, in other embodiments not shown, it may be only between the partial side edges 125a. Setting the flat cut angle 127a is still a technical solution that can be used in the creation of the novel, without departing from the scope of the novel creation.
圖3A繪示為本新型創作的另一實施例的一種半導體結構的立體示意圖。圖3B繪示為圖3A之半導體結構的俯視示意圖。本實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例,本實施例不再重複贅述。3A is a perspective view of a semiconductor structure according to another embodiment of the present invention. 3B is a top plan view of the semiconductor structure of FIG. 3A. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description is not repeated herein.
請參考圖3A與圖3B,本實施例的半導體結構100b與前述實施例的半導體結構100a主要的差異是在於:本實施例的半導體層120b的突出部124b在俯視時具有一上表面128b,而上表面128b具有多個側邊125b,其中至少兩個相鄰側邊125b之間具有 一導角126a。特別是,導角126a的兩端點126a1、126a2的連線L3與導角126a定義出一封閉區域A1,而導角126a的端點126a1、126a2的連線L3與對應的側邊125b的延伸方向L1、L2定義出一三角形A2,且封閉區域A1的面積小於三角形A2的面積的0.8倍。於本實施例中,導角126a具體化為一圓角且曲率半徑介於10微米至30微米之間,較佳地,其曲率半徑介於15微米至25微米之間,可具有較高的發光效率。此處,本實施例的突出部124b具有多個側表面125s2,至少兩個相鄰側表面125s2之間具有一圓角設計所形成的圓切面126b。Referring to FIG. 3A and FIG. 3B, the main difference between the semiconductor structure 100b of the present embodiment and the semiconductor structure 100a of the foregoing embodiment is that the protruding portion 124b of the semiconductor layer 120b of the present embodiment has an upper surface 128b in plan view, and Upper surface 128b has a plurality of sides 125b with at least two adjacent sides 125b therebetween A lead angle 126a. In particular, the line L3 and the lead angle 126a of the two end points 126a1, 126a2 of the lead angle 126a define a closed area A1, and the line L3 of the end points 126a1, 126a2 of the lead angle 126a and the extension of the corresponding side edge 125b The directions L1, L2 define a triangle A2, and the area of the closed area A1 is smaller than 0.8 times the area of the triangle A2. In this embodiment, the lead angle 126a is embodied as a rounded corner and has a radius of curvature between 10 micrometers and 30 micrometers. Preferably, the radius of curvature is between 15 micrometers and 25 micrometers, and the light has a high light emission. effectiveness. Here, the protruding portion 124b of the present embodiment has a plurality of side surfaces 125s2, and at least two adjacent side surfaces 125s2 have a circular cut surface 126b formed by a rounded design.
如圖3A與圖3B所示,本實施例的導角126a具體化為一外凸圓角(protrusive round angle)的設計,且導角126a的弧線為圓形弧線。但於其他未繪示的實施例中,導角126a亦可為一內凹圓角(recessive round angle)或橢圓角的設計,而導角126a的弧線亦可為橢圓弧線、拋物曲線或雙曲線。上述導角126a設計仍屬於本新型創作可採用的技術方案,不脫離本新型創作所欲保護的範圍。As shown in FIG. 3A and FIG. 3B, the lead angle 126a of the present embodiment is embodied as a design of a convex round angle, and the arc of the lead angle 126a is a circular arc. However, in other embodiments not shown, the lead angle 126a may also be a recessed round angle or an elliptical angle design, and the arc of the lead angle 126a may also be an elliptical arc, a parabola or a hyperbola. . The design of the above-mentioned lead angle 126a still belongs to the technical solution that can be used in the creation of the novel, without departing from the scope of protection of the novel creation.
本實施例的半導體層120b的突出部124b的相鄰兩側邊125b之間皆具有導角126a的設計,因此相較於習知突出部22相鄰側邊皆為直角使交界處13過於尖突的設計,本實施例的半導體層120b可利用導角126a的設計讓交處界多一緩衝切面,例如圓切面126b,因此在經過蝕刻製程後,不會因為側邊過於尖突產生塌陷現象,藉此提高半導體層120b的結構強度。如此一來,本實 施例的半導體結構100b可具有較佳的結構可靠度。較佳地,封閉區域A1的面積小於三角形A2的面積的0.8倍,將在不影響出光效率的情況下,達到最佳的緩衝效果。大於0.8倍將使相鄰側邊交界處過於接近直角的設計,以致蝕刻時易產生塌陷現象。The adjacent side edges 125b of the protruding portion 124b of the semiconductor layer 120b of the present embodiment have a design of the lead angle 126a. Therefore, the adjacent sides of the conventional protruding portion 22 are at right angles to make the boundary 13 too sharp. The semiconductor layer 120b of the present embodiment can utilize the design of the lead angle 126a to make the intersection boundary more than a buffer cut surface, for example, the circular cut surface 126b. Therefore, after the etching process, there is no collapse phenomenon due to the side edge being too sharp. Thereby, the structural strength of the semiconductor layer 120b is increased. In this way, this reality The semiconductor structure 100b of the embodiment can have better structural reliability. Preferably, the area of the closed area A1 is less than 0.8 times the area of the triangle A2, and the optimal buffering effect is achieved without affecting the light extraction efficiency. More than 0.8 times will make the adjacent side junctions too close to the right angle design, so that the collapse phenomenon is easy to occur during etching.
圖4繪示為本新型創作的另一實施例的一種半導體結構的剖面示意圖。本實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例,本實施例不再重複贅述。4 is a cross-sectional view showing a semiconductor structure of another embodiment of the present invention. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description is not repeated herein.
請參考圖4,本實施例的半導體結構100c與前述實施例的半導體結構100a主要的差異是在於:本實施例的半導體層120c的側壁129c為一粗糙表面。更具體來說,利用蝕刻技術,使半導體層120c的基部122c的側壁129c1與突出部124c的側壁129c2皆為粗糙表面,可有效提高半導體層120c的出光效率。選擇性地,基板110的側壁110a亦可為一粗糙表面,讓半導體結構100a的出光效率更佳。當然,於其他未繪示的實施例中,亦可僅有基板的側壁為粗糙表面,而半導體層的側壁並非為粗糙表面,此仍屬於本新型創作可採用的技術方案,不脫離本新型創作所欲保護的範圍。Referring to FIG. 4, the main difference between the semiconductor structure 100c of the present embodiment and the semiconductor structure 100a of the foregoing embodiment is that the sidewall 129c of the semiconductor layer 120c of the present embodiment is a rough surface. More specifically, by the etching technique, the sidewall 129c1 of the base portion 122c of the semiconductor layer 120c and the sidewall 129c2 of the protruding portion 124c are both rough surfaces, and the light extraction efficiency of the semiconductor layer 120c can be effectively improved. Optionally, the sidewall 110a of the substrate 110 may also be a rough surface to make the light-emitting efficiency of the semiconductor structure 100a better. Of course, in other embodiments not shown, only the sidewall of the substrate is a rough surface, and the sidewall of the semiconductor layer is not a rough surface, which is still a technical solution that can be used in the novel creation, without departing from the novel creation. The scope of protection.
此外,於其他未繪示的實施例中,亦可選用於如前述實施例所提及之具有導角126a設計的半導體層120b,本領域的技術人員當可參照前述實施例的說明,依據實際需求,而選用前述構 件,以達到所需的技術效果。In addition, in other embodiments not shown, the semiconductor layer 120b having the design of the lead angle 126a as mentioned in the foregoing embodiment may be selected, and those skilled in the art may refer to the description of the foregoing embodiment, according to the actual situation. Demand, and the above structure Pieces to achieve the desired technical effect.
綜上所述,本新型創作的半導體層具有平切角或導角的設計,以避免習知直角設計過於尖突而影響結構的情況,藉此提高半導體層的結構強度。簡言之,本新型創作的半導體結構可具有較佳的結構可靠度。In summary, the novel semiconductor layer has a flat cut angle or a lead angle design to avoid the conventional right angle design being too sharp and affecting the structure, thereby improving the structural strength of the semiconductor layer. In short, the novel semiconductor structure created by the present invention can have better structural reliability.
雖然本新型創作已以實施例揭露如上,然其並非用以限定本新型創作,任何所屬技術領域中具有通常知識者,在不脫離本新型創作的精神和範圍內,當可作些許的更動與潤飾,故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.
100a‧‧‧半導體結構100a‧‧‧Semiconductor structure
110‧‧‧基板110‧‧‧Substrate
120a‧‧‧半導體層120a‧‧‧Semiconductor layer
122‧‧‧基部122‧‧‧ base
124a‧‧‧突出部124a‧‧‧Protruding
125a‧‧‧側邊125a‧‧‧ side
127a‧‧‧平切角127a‧‧‧cut angle
128a‧‧‧上表面128a‧‧‧ upper surface
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TWI560910B (en) * | 2014-12-27 | 2016-12-01 | Advanced Optoelectronic Tech | Light emitting diode packaging stucture |
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