TWM472947U - Dual-directional silicon controlled rectifier - Google Patents

Dual-directional silicon controlled rectifier Download PDF

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TWM472947U
TWM472947U TW102216191U TW102216191U TWM472947U TW M472947 U TWM472947 U TW M472947U TW 102216191 U TW102216191 U TW 102216191U TW 102216191 U TW102216191 U TW 102216191U TW M472947 U TWM472947 U TW M472947U
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semiconductor region
controlled rectifier
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TW102216191U
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Yun-Chiang Wang
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Feature Integration Technology Inc
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Description

雙向矽控整流器Bidirectionally controlled rectifier

本新型係有關於一種雙向矽控整流器(Dual-directional Silicon Controlled Rectifier,DSCR),尤其是一種具有摻雜區域(doped region)之雙向矽控整流器。The present invention relates to a Dual-directional Silicon Controlled Rectifier (DSCR), and more particularly to a bidirectionally controlled rectifier having a doped region.

隨著半導體技術之進步,金屬氧化物半導體場效電晶體(Metal-oxide-semiconductor field-effect transistor,MOSFET)的尺寸亦日漸微小化,其尺寸已降至次微米(submicron meter)、甚至深次微米(deep submicron meter)等級。而隨此先進技術而日漸甚薄的閘極氧化層(gate oxide),在此情況下,極可能在外加稍高電壓時,即產生損害。在面臨一般環境下的靜電電壓時,由於靜電電壓所夾帶的電壓值可以高達幾千甚至幾萬伏特,因此,在設計積體電路時,設計者必須考量在靜電累積至一定量前,將其放電。在此條件之下,具有低導通電阻、低電容、低功率消耗以及高功率電流導出能力的矽控整流器(Silicon Controlled Rectifier,SCR)即是可用以達成靜電防護(Electromagnetic interference,EMI)的一種有效元件。With the advancement of semiconductor technology, the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has become smaller and smaller, and its size has been reduced to submicron meters or even deep times. Deep submicron meter rating. With this advanced technology, the gate oxide is getting thinner. In this case, it is very likely that damage will occur when a slightly higher voltage is applied. When facing an electrostatic voltage in a general environment, since the voltage value of the electrostatic voltage can be as high as several thousand or even tens of thousands of volts, when designing an integrated circuit, the designer must consider the static electricity before it accumulates to a certain amount. Discharge. Under these conditions, a Silicon Controlled Rectifier (SCR) with low on-resistance, low capacitance, low power consumption, and high power current derivation capability is an effective way to achieve Electromagnetic Interference (EMI). element.

一般而言,雙向矽控整流器已成為正負電壓之I/O防護電路的市場主流。初期之矽控整流器,有直接製作於矽基板上者,其由於耐壓度低,因此應用僅受限於一般的積體電路製程中。習知亦有環型佈局之矽控整流器,但其佈局面積大、啟動速度因結構過大而不如預期,亦不被廣 泛地使用。In general, bidirectionally controlled rectifiers have become the mainstream of the I/O protection circuit for positive and negative voltages. The initial controlled rectifiers are directly fabricated on the germanium substrate. Due to their low withstand voltage, the application is limited only to the general integrated circuit process. It is also known that there is a ring-type layout of the controlled rectifier, but its layout area is large, the starting speed is too large due to the structure, and it is not widely Use it in general.

是以,為了改善矽控整流器之啟動速度,遂有設計者透過改良其內部之金氧半導體結構,來降低其崩潰電壓,以調變矽控整流器之觸發電壓(trigger voltage)的做法。然而,值得注意的是,此種做法雖可快速啟動矽控整流器,但同時也使得積體電路的工作電壓受限。也就是說,積體電路的工作電壓會被限制在金氧半導體結構中P+/N well(或是N+/P well)間以及擊穿效應(punchthrough)發生前被限制在崩潰電壓以下,而在輸入電壓高於工作電壓時,會有誤動作的情況發生,例如EIA/TIA-232-E規範輸入電壓為正負15伏特的情況下,極容易提早崩潰或擊穿,因此,無法適用於此類應用的電路上。Therefore, in order to improve the startup speed of the controlled rectifier, the designer has reduced the breakdown voltage by modifying the internal MOS structure to modulate the trigger voltage of the rectifier. However, it is worth noting that although this method can quickly start the rectifier rectifier, it also limits the operating voltage of the integrated circuit. That is to say, the operating voltage of the integrated circuit is limited to P+/N well (or N+/P well) in the MOS structure and the breakdown voltage is limited below the breakdown voltage before the occurrence of the punchthrough. When the input voltage is higher than the operating voltage, a malfunction may occur. For example, if the input voltage of the EIA/TIA-232-E specification is 15 volts or so, it is easy to collapse or breakdown early, so it cannot be applied to such applications. On the circuit.

因此,如何設計出一種具有良好靜電防護之效,並且同時可用以承受高工作電壓之矽控整流器,即成為現今發展沿革上重要的研究方向之一。Therefore, how to design a controlled rectifier with good electrostatic protection and at the same time can withstand high working voltage is one of the important research directions in the development of today.

鑒於以上的問題,本新型在於提供一種雙向矽控整流器,以解決習知存在之問題。In view of the above problems, the present invention is to provide a bidirectionally controlled rectifier to solve the conventional problems.

本新型提出一種雙向矽控整流器(Dual-directional Silicon Controlled Rectifier,DSCR),包括:一基板、一埋入層、一第一井、第二井與第三井、一第一半導體區、第二半導體區、第三半導體區與第四半導體區、以及一摻雜區域(doped region)。其中,基板係為第一導電型態。埋入層位於基板上,且為第二導電型態。第一井與第二井位於埋入層上,且皆為第一導電型態。第三井位於埋入層上,且於第一井與第二井之間,第三井 係為第二導電型態。第一半導體區與第二半導體區,皆位於第一井內;第三半導體區與第四半導體區,皆位於第二井內。摻雜區域(doped region),位於第一半導體區與第三半導體區之間,摻雜區域包括部分之第三井,且摻雜區域係為第二導電型態。The present invention provides a dual-directional silicon controlled rectifier (DSCR), comprising: a substrate, a buried layer, a first well, a second well and a third well, a first semiconductor region, and a second a semiconductor region, a third semiconductor region and a fourth semiconductor region, and a doped region. Wherein, the substrate is in a first conductivity type. The buried layer is on the substrate and is in a second conductivity type. The first well and the second well are located on the buried layer and are all in a first conductivity type. The third well is located on the buried layer and between the first well and the second well, the third well It is a second conductivity type. The first semiconductor region and the second semiconductor region are both located in the first well; the third semiconductor region and the fourth semiconductor region are both located in the second well. A doped region is disposed between the first semiconductor region and the third semiconductor region, the doped region includes a portion of the third well, and the doped region is in a second conductivity type.

根據本新型提出之雙向矽控整流器,其中摻雜區域更包括部分之第一井與第二井。According to the bidirectionally controlled rectifier of the present invention, the doped region further includes a portion of the first well and the second well.

根據本新型提出之雙向矽控整流器,其中第一導電型態與第二導電型態其中之一係為N型,另一係為P型。According to the bidirectionally controlled rectifier of the present invention, one of the first conductivity type and the second conductivity type is N-type, and the other is P-type.

根據本新型提出之雙向矽控整流器,其中第一半導體區與第三半導體區係為第一導電型態時,第二半導體區與第四半導體區係為第二導電型態。According to the bidirectionally controlled rectifier of the present invention, when the first semiconductor region and the third semiconductor region are in the first conductivity type, the second semiconductor region and the fourth semiconductor region are in the second conductivity type.

根據本新型提出之雙向矽控整流器,其中第一半導體區與第三半導體區係為第二導電型態時,第二半導體區與第四半導體區係為第一導電型態。According to the bidirectional voltage controlled rectifier proposed by the present invention, when the first semiconductor region and the third semiconductor region are in the second conductivity type, the second semiconductor region and the fourth semiconductor region are in the first conductivity type.

是以,根據本新型提出之雙向矽控整流器,係藉由第一半導體區與第三半導體區之間的摻雜區域,改變載子濃度或使用標準製程中不同載子濃度之半導體,以調節其接面(junction)之崩潰電壓,令積體電路之工作電壓不再被限制於習知擊穿效應或低崩潰點之前,大幅增加其應用價值與產業利用性。Therefore, the bidirectionally controlled rectifier according to the present invention is regulated by a doping region between the first semiconductor region and the third semiconductor region, changing the carrier concentration or using a semiconductor having a different carrier concentration in a standard process. The collapse voltage of the junction causes the operating voltage of the integrated circuit to be no longer limited to the conventional breakdown effect or low breakdown point, greatly increasing its application value and industrial utilization.

以上有關於本新型的內容說明,與以下的實施方式係用以示範與解釋本新型的精神與原理,並且提供本新型的專利申請範圍更進一步的解釋。有關本新型的特徵、實作與功效,茲配合圖式作較佳實施例詳 細說明如下。The above description of the present invention is provided to demonstrate and explain the spirit and principles of the present invention, and to provide a further explanation of the scope of the present patent application. With regard to the features, implementations and effects of the present invention, the preferred embodiment is described in conjunction with the drawings. The details are as follows.

10‧‧‧P型基板10‧‧‧P type substrate

10a‧‧‧N型基板10a‧‧‧N type substrate

20‧‧‧N型埋入層20‧‧‧N type buried layer

20a‧‧‧P型埋入層20a‧‧‧P type buried layer

31‧‧‧P型第一井31‧‧‧P type first well

31a‧‧‧N型第一井31a‧‧‧N type first well

32‧‧‧P型第二井32‧‧‧P type second well

32a‧‧‧N型第二井32a‧‧‧N type second well

33‧‧‧N型第三井33‧‧‧N type third well

33a‧‧‧P型第三井33a‧‧‧P type third well

34‧‧‧N型第四井34‧‧‧N type fourth well

34a‧‧‧P型第四井34a‧‧‧P type fourth well

41‧‧‧N型第一半導體區41‧‧‧N type first semiconductor area

41a‧‧‧P型第一半導體區41a‧‧‧P type first semiconductor area

42‧‧‧P型第二半導體區42‧‧‧P type second semiconductor area

42a‧‧‧N型第二半導體區42a‧‧‧N type second semiconductor area

43‧‧‧N型第三半導體區43‧‧‧N type third semiconductor area

43a‧‧‧P型第三半導體區43a‧‧‧P type third semiconductor area

44‧‧‧P型第四半導體區44‧‧‧P type fourth semiconductor area

44a‧‧‧N型第四半導體區44a‧‧‧N type fourth semiconductor area

50‧‧‧N型摻雜區域50‧‧‧N-doped region

50a‧‧‧P型摻雜區域50a‧‧‧P type doped area

1000‧‧‧雙向矽控整流器1000‧‧‧Bidirectional remote control rectifier

1000a‧‧‧雙向矽控整流器1000a‧‧‧Bidirectional remote control rectifier

第1A圖係為根據本新型第一實施例之雙向矽控整流器之結構示意圖。FIG. 1A is a schematic structural view of a bidirectionally controlled rectifier according to a first embodiment of the present invention.

第1B圖係為根據本新型第二實施例之雙向矽控整流器之結構示意圖。FIG. 1B is a schematic structural view of a bidirectionally controlled rectifier according to a second embodiment of the present invention.

第1C圖係為根據本新型第三實施例之雙向矽控整流器之結構示意圖。1C is a schematic structural view of a bidirectionally controlled rectifier according to a third embodiment of the present invention.

第1D圖係為根據本新型第四實施例之雙向矽控整流器之結構示意圖。1D is a schematic structural view of a bidirectionally controlled rectifier according to a fourth embodiment of the present invention.

第2A圖係為根據「第1A圖」之雙向矽控整流器,其正向工作電壓-電流之示意圖。Figure 2A is a schematic diagram of the forward operating voltage-current of the bidirectionally controlled rectifier according to "1A".

第2B圖係為根據「第1A圖」之雙向矽控整流器,其負向工作電壓-電流之示意圖。Figure 2B is a schematic diagram of the negative operating voltage-current of the bidirectionally controlled rectifier according to "1A".

第3A圖係為根據本新型第五實施例之雙向矽控整流器之結構示意圖。3A is a schematic structural view of a bidirectionally controlled rectifier according to a fifth embodiment of the present invention.

第3B圖係為根據本新型第六實施例之雙向矽控整流器之結構示意圖。3B is a schematic structural view of a bidirectionally controlled rectifier according to a sixth embodiment of the present invention.

第3C圖係為根據本新型第七實施例之雙向矽控整流器之結構示意圖。3C is a schematic structural view of a bidirectionally controlled rectifier according to a seventh embodiment of the present invention.

第3D圖係為根據本新型第八實施例之雙向矽控整流器之結構示意圖。The 3D figure is a schematic structural view of the bidirectionally controlled rectifier according to the eighth embodiment of the present invention.

以下在實施方式中詳細敘述本新型之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本新型之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本新型相關之目的及優點。The detailed features and advantages of the present invention are described in detail in the following detailed description of the embodiments of the present invention. Any related art and related art can easily understand the related purposes and advantages of the present invention.

「第1A圖」係為根據本新型第一實施例之雙向矽控整流器之結構示意圖。雙向矽控整流器1000包括一P型基板10,其上具有一N型 埋入層(N-buried layer,NBL)20。N型埋入層20上包括有一P型第一井31、P型第二井32與N型第三井33,其中N型第三井33係配置於P型第一井31與P型第二井32之間。Fig. 1A is a schematic structural view of a bidirectionally controlled rectifier according to a first embodiment of the present invention. The bidirectionally controlled rectifier 1000 includes a P-type substrate 10 having an N-type thereon N-buried layer (NBL) 20. The N-type buried layer 20 includes a P-type first well 31, a P-type second well 32 and an N-type third well 33, wherein the N-type third well 33 is disposed in the P-type first well 31 and the P-type Between two wells 32.

根據本新型之實施例,P型第一井31、N型埋入層20與P型基板10之間更具有一N型第四井34。同樣地,N型第四井34亦可配置於P型第二井32、N型埋入層20與P型基板10之間。其中,N型第四井34可以是但不限於未摻雜的磊晶層(epitaxy)、抑或是任何具有N型之導電型區域,例如:N型磊晶層或N型井區。According to an embodiment of the present invention, an N-type fourth well 34 is further provided between the P-type first well 31, the N-type buried layer 20 and the P-type substrate 10. Similarly, the N-type fourth well 34 may be disposed between the P-type second well 32, the N-type buried layer 20, and the P-type substrate 10. The N-type fourth well 34 may be, but not limited to, an undoped epitaxial layer or any type of conductive type having an N-type, such as an N-type epitaxial layer or an N-type well region.

P型第一井31內包括一N型第一半導體區41與一P型第二半導體區42,其係共同連接至一陽極。P型第二井32內包括一N型第三半導體區43與一P型第四半導體區44,其係共同連接至一陰極。其中,半導體區連接至陽極與陰極的方式亦可以如「第1B圖」所示,其係將N型第一半導體區41與P型第二半導體區42共同連接至陰極,而N型第三半導體區43與P型第四半導體區44共同連接至陽極。The P-type first well 31 includes an N-type first semiconductor region 41 and a P-type second semiconductor region 42 which are commonly connected to an anode. The P-type second well 32 includes an N-type third semiconductor region 43 and a P-type fourth semiconductor region 44 that are commonly connected to a cathode. The manner in which the semiconductor region is connected to the anode and the cathode may also be as shown in FIG. 1B, which connects the N-type first semiconductor region 41 and the P-type second semiconductor region 42 to the cathode, and the N-type third. The semiconductor region 43 and the P-type fourth semiconductor region 44 are commonly connected to the anode.

如「第1A圖」所示,N型摻雜區域(Doped region)50係配置於N型第一半導體區41與N型第三半導體區43之間,N型摻雜區域50並且包括部分之P型第一井31、P型第二井32與N型第三井33。於此,N型摻雜區域50在N型第一半導體區41、N型第三半導體區43、P型第一井31與P型第二井32之間形成一摻雜濃度(Doped concentration)之N型區域。As shown in FIG. 1A, an N-type doped region 50 is disposed between the N-type first semiconductor region 41 and the N-type third semiconductor region 43, and the N-type doped region 50 includes a portion. P-type first well 31, P-type second well 32 and N-type third well 33. Here, the N-type doped region 50 forms a Doped concentration between the N-type first semiconductor region 41, the N-type third semiconductor region 43, the P-type first well 31 and the P-type second well 32. N-type area.

其中,「第1C圖」係為根據本新型又一實施例之雙向矽控整流器之結構示意圖。其中,N型摻雜區域50可以設計為不連續之佈植(implant)區域。又「第1D圖」係為根據本新型另一實施例之雙向矽控整流 器之結構示意圖。如圖所示,其中N型摻雜區域50亦可選擇性地僅包括部分之N型第三井33,而以上各實施方式皆可以同樣用以實現本新型之功效(以下詳述)。The "1C diagram" is a schematic structural view of a bidirectionally controlled rectifier according to still another embodiment of the present invention. Among them, the N-type doping region 50 can be designed as a discontinuous implant region. Further, "1D" is a two-way controlled rectifier according to another embodiment of the present invention. Schematic diagram of the structure of the device. As shown, wherein the N-type doped region 50 can also selectively include only a portion of the N-type third well 33, and all of the above embodiments can be used to achieve the efficacy of the present invention (described in detail below).

根據本新型之實施例,由於N型摻雜區域50係可用以將原先N型第一半導體區41與P型第一井31之間的崩潰點有效延伸至P型第一井31與N型摻雜區域50之接面,並且同樣地將原先N型第三半導體區43與P型第二井32之間的崩潰點有效延伸至P型第二井32與N型摻雜區域50之接面,雙向矽控整流器1000之耐壓係藉此有效地被改變(即改變其崩潰電壓)。是以,根據本新型第一至第四實施例之雙向矽控整流器,在應用於I/O電壓高於工作電壓時,仍可作為其維持整流與靜電防護之有效元件。According to an embodiment of the present invention, since the N-type doping region 50 can be used to effectively extend the collapse point between the original N-type first semiconductor region 41 and the P-type first well 31 to the P-type first well 31 and the N-type The junction of the doped regions 50, and likewise the collapse point between the original N-type third semiconductor region 43 and the P-type second well 32 is effectively extended to the junction of the P-type second well 32 and the N-type doped region 50. In this way, the withstand voltage of the bidirectionally controlled rectifier 1000 is thereby effectively changed (i.e., its breakdown voltage is changed). Therefore, the bidirectionally controlled rectifier according to the first to fourth embodiments of the present invention can be used as an effective component for maintaining rectification and electrostatic protection when applied to an I/O voltage higher than an operating voltage.

「第2A圖」與「第2B圖」係分別為根據「第1A圖」之雙向矽控整流器,其正向工作電壓-電流與負向工作電壓-電流之示意圖,由「第2A圖」與「第2B圖」中可見,雙向矽控整流器1000之崩潰電壓已被有效提昇至20伏特,因此,即便當應用於EIA/TIA-232-E規範輸入電壓為正負15伏特的情況下,雙向矽控整流器1000仍然適用而不至於誤動作,且可維持良好之低信號損失與高靜電防護力。"2A" and "2B" are schematic diagrams of the forward operating voltage-current and negative operating voltage-current according to the "1A" bidirectionally controlled rectifier, respectively, from "A 2A" and As can be seen in Figure 2B, the breakdown voltage of the bidirectionally controlled rectifier 1000 has been effectively boosted to 20 volts, so even when applied to the EIA/TIA-232-E specification, the input voltage is plus or minus 15 volts. The controlled rectifier 1000 is still applicable without malfunction and can maintain good low signal loss and high electrostatic protection.

本新型之第一至第四實施例(意即「第1A圖」至「第1D圖」),其係利用P型基板作為雙向矽控整流器一實施例之說明。其中,各個元件(包括:埋入層、第一井至第三井、以及摻雜區域)之導電型態皆係根據P型基板之導電型態而定。舉例而言,雙向矽控整流器亦可用N型基板,作為另一實施例之說明,「第3A圖」即為根據本新型第五實施例之雙向矽 控整流器之結構示意圖,其係利用N型基板作為其基材。The first to fourth embodiments of the present invention (that is, "1A" to "1D") are illustrative of an embodiment in which a P-type substrate is used as a bidirectionally controlled rectifier. The conductivity patterns of the respective components (including the buried layer, the first well to the third well, and the doped region) are all determined according to the conductivity type of the P-type substrate. For example, the bidirectionally controlled rectifier can also be an N-type substrate. As an illustration of another embodiment, "3A" is a bidirectional 矽 according to the fifth embodiment of the present invention. A schematic diagram of the structure of a controlled rectifier using an N-type substrate as its substrate.

雙向矽控整流器1000a包括N型基板10a、P型埋入層20a、N型第一井31a、N型第二井32a、P型第三井33a、P型第四井34a與P型摻雜區域50a,其中N型第一井31a內包括共同連接至陽極之P型第一半導體區41a與N型第二半導體區42a,N型第二井32a內包括共同連接至陰極之P型第三半導體區43a與N型第四半導體區44a。其中,第一半導體區、第二半導體區、第三半導體區與第四半導體區之導電型態並非用以限定本新型之新型範圍。以本新型提出之實施例而言,當第一半導體區與第三半導體區因應P型基板而為N型半導體型時,第二半導體區與第四半導體區即為P型;而當第一半導體區與第三半導體區因應N型基板而為P型半導體型時,第二半導體區與第四半導體區即為N型,當可根據實際之電路應用狀況,設計其導電型態。The bidirectionally controlled rectifier 1000a includes an N-type substrate 10a, a P-type buried layer 20a, an N-type first well 31a, an N-type second well 32a, a P-type third well 33a, a P-type fourth well 34a, and a P-type doping. The region 50a, wherein the N-type first well 31a includes a P-type first semiconductor region 41a and an N-type second semiconductor region 42a commonly connected to the anode, and the N-type second well 32a includes a P-type third commonly connected to the cathode. The semiconductor region 43a and the N-type fourth semiconductor region 44a. The conductivity patterns of the first semiconductor region, the second semiconductor region, the third semiconductor region and the fourth semiconductor region are not intended to limit the novel range of the novel. In the embodiment proposed by the present invention, when the first semiconductor region and the third semiconductor region are N-type semiconductor type in response to the P-type substrate, the second semiconductor region and the fourth semiconductor region are P-type; When the semiconductor region and the third semiconductor region are of a P-type semiconductor type in response to the N-type substrate, the second semiconductor region and the fourth semiconductor region are N-type, and the conductive type can be designed according to actual circuit application conditions.

其次,同本新型之第一實施例,雙向矽控整流器1000a連接至陽極、陰極之連接方式亦可互換,且P型摻雜區域50a亦可選擇性設置為不連續之佈植(implant)區域,或者僅包括部分之P型第三井33a,其分別如「第3B圖」、「第3C圖」與「第3D圖」所示,亦可用以實現本新型之功效。Secondly, with the first embodiment of the present invention, the connection mode of the bidirectionally controlled rectifier 1000a to the anode and the cathode can also be interchanged, and the P-type doping region 50a can also be selectively set as a discontinuous implant region. Or only part of the P-type third well 33a, as shown in "3B", "3C" and "3D", respectively, can also be used to achieve the effects of the present invention.

是以,綜上所述,本新型之目的在於提供一種雙向矽控整流器,以有效防止靜電對半導體元件可能造成的損傷,並維持其高靜電防護能力。Therefore, in summary, the purpose of the present invention is to provide a bidirectionally controlled rectifier to effectively prevent damage to the semiconductor component caused by static electricity and to maintain its high electrostatic protection capability.

本新型之另一目的,在於提供一種具有摻雜區域(Doped region)之雙向矽控整流器,以透過控制摻雜區域之載子濃度或使用標準製程中不同載子濃度之半導體,以有效調變積體電路之崩潰電壓,在I/O電壓遠 高於工作電壓時,亦不會有誤動作的問題發生,藉此有效解決習知矽控整流器觸發電壓受限之問題。Another object of the present invention is to provide a bidirectionally controlled rectifier having a doped region for effectively modulating the concentration of a carrier in a doped region or using a semiconductor having a different carrier concentration in a standard process. The breakdown voltage of the integrated circuit, at the I/O voltage far When the voltage is higher than the working voltage, there will be no problem of malfunction, which effectively solves the problem that the trigger voltage of the conventional controlled rectifier is limited.

雖然本新型以前述的較佳實施例揭露如上,然其並非用以限定本新型,任何熟習相像技藝者,在不脫離本新型之精神與範圍內,當可作些許更動與潤飾,因此本新型之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。Although the present invention has been described above with reference to the preferred embodiments thereof, it is not intended to limit the present invention. Any one skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

10‧‧‧P型基板10‧‧‧P type substrate

20‧‧‧N型埋入層20‧‧‧N type buried layer

31‧‧‧P型第一井31‧‧‧P type first well

32‧‧‧P型第二井32‧‧‧P type second well

33‧‧‧N型第三井33‧‧‧N type third well

34‧‧‧N型第四井34‧‧‧N type fourth well

41‧‧‧N型第一半導體區41‧‧‧N type first semiconductor area

42‧‧‧P型第二半導體區42‧‧‧P type second semiconductor area

43‧‧‧N型第三半導體區43‧‧‧N type third semiconductor area

44‧‧‧P型第四半導體區44‧‧‧P type fourth semiconductor area

50‧‧‧N型摻雜區域50‧‧‧N-doped region

1000‧‧‧雙向矽控整流器1000‧‧‧Bidirectional remote control rectifier

Claims (10)

一種雙向矽控整流器(Dual-directional Silicon Controlled Rectifier,DSCR),包括:一基板,係為一第一導電型態;一埋入層,位於該基板上,且為一第二導電型態;一第一井與一第二井,位於該埋入層上,且皆為該第一導電型態;一第三井,位於該埋入層上,且於該第一井與該第二井之間,該第三井係為該第二導電型態;一第一半導體區與一第二半導體區,係位於該第一井內;一第三半導體區與一第四半導體區,係位於該第二井內;以及一摻雜區域(Doped region),位於該第一半導體區與該第三半導體區之間,該摻雜區域包括部分之該第三井,且該摻雜區域係為該第二導電型態。A dual-directional Silicon Controlled Rectifier (DSCR) includes: a substrate in a first conductivity type; a buried layer on the substrate and a second conductivity type; a first well and a second well are located on the buried layer and are all in the first conductivity type; a third well is located on the buried layer, and in the first well and the second well The third well is in the second conductivity type; a first semiconductor region and a second semiconductor region are located in the first well; a third semiconductor region and a fourth semiconductor region are located in the first semiconductor region a second well; and a doped region between the first semiconductor region and the third semiconductor region, the doped region comprising a portion of the third well, and the doped region is The second conductivity type. 如請求項1所述之雙向矽控整流器,其中該摻雜區域更包括部分之該第一井與該第二井。The bidirectionally controlled rectifier of claim 1, wherein the doped region further comprises a portion of the first well and the second well. 如請求項1所述之雙向矽控整流器,其中該第一導電型態係為N型或P型其中之一,該第二導電型態係為N型或P型其中之另一。The bidirectionally controlled rectifier of claim 1, wherein the first conductivity type is one of an N type or a P type, and the second conductivity type is another one of an N type or a P type. 如請求項1所述之雙向矽控整流器,其中該第一半導體區與該第二半導體區係連接至一陽極,該第三半導體區與該第四半導體區係連接至一陰極。The bidirectionally controlled rectifier of claim 1, wherein the first semiconductor region and the second semiconductor region are connected to an anode, and the third semiconductor region and the fourth semiconductor region are connected to a cathode. 如請求項1所述之雙向矽控整流器,其中該第一半導體區與該第二半導 體區係連接至一陰極,該第三半導體區與該第四半導體區係連接至一陽極。The bidirectionally controlled rectifier of claim 1, wherein the first semiconductor region and the second semiconductor are The body region is connected to a cathode, and the third semiconductor region and the fourth semiconductor region are connected to an anode. 如請求項1所述之雙向矽控整流器,更包括至少一第四井,連接於該第一井、該埋入層與該基板之間,該第四井係為該第二導電型態。The bidirectionally controlled rectifier according to claim 1, further comprising at least one fourth well connected between the first well, the buried layer and the substrate, wherein the fourth well is in the second conductivity type. 如請求項6所述之雙向矽控整流器,其中該第四井係為一磊晶層(epitaxy)。The bidirectionally controlled rectifier of claim 6, wherein the fourth well is an epitaxy layer. 如請求項1所述之雙向矽控整流器,更包括至少一第四井,連接於該第二井、該埋入層與該基板之間,該第四井係為該第二導電型態。The bidirectionally controlled rectifier according to claim 1, further comprising at least one fourth well connected between the second well, the buried layer and the substrate, wherein the fourth well is in the second conductivity type. 如請求項8所述之雙向矽控整流器,其中該第四井係為一磊晶層(epitaxy)。The bidirectionally controlled rectifier of claim 8, wherein the fourth well is an epitaxy. 如請求項1所述之雙向矽控整流器,其中該第一半導體區與該第三半導體區係為該第一導電型態或該第二導電型態其中之一,該第二半導體區與該第四半導體區係為該第一導電型態或該第二導電型態其中之另一。The bidirectionally controlled rectifier of claim 1, wherein the first semiconductor region and the third semiconductor region are one of the first conductivity type or the second conductivity type, the second semiconductor region and the The fourth semiconductor region is the other of the first conductivity type or the second conductivity type.
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