TWM471674U - An embedded package structure - Google Patents
An embedded package structure Download PDFInfo
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- TWM471674U TWM471674U TW102217212U TW102217212U TWM471674U TW M471674 U TWM471674 U TW M471674U TW 102217212 U TW102217212 U TW 102217212U TW 102217212 U TW102217212 U TW 102217212U TW M471674 U TWM471674 U TW M471674U
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- package
- package structure
- electronic carrier
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- connection port
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Tests Of Electronic Circuits (AREA)
Description
本創作係屬一種封裝體結構,尤其是指一種具有內嵌座體之整合式封裝體結構。 The present invention is a package structure, in particular, an integrated package structure having an embedded body.
近年來的半導體封裝技術包括有二維的系統單晶片(System on Chip;SoC),目的在於將電子系統集成於單一晶片的積體電路,並具有低功耗、高性能、實裝面積小的優點,但系統單晶片的設計時間太長,且不同元件封裝於同一顆IC上,其所生產的IC,仍佔有相當大面積,其應用範圍有限。 In recent years, semiconductor packaging technology includes a two-dimensional system on chip (SoC), which aims to integrate an electronic system into a single-chip integrated circuit, and has low power consumption, high performance, and small mounting area. The advantage is that the design time of the system single chip is too long, and different components are packaged on the same IC, and the IC produced by the system still occupies a considerable area, and its application range is limited.
而系統級封裝(System in Package;SiP)為新型的封裝技術,可將一個系統或子系統的全部或大部份電子功能配置在整合型基板,相較於SOC更具有小型化、高功能、開發週期短、低價格的優點,其中,系統級封裝包括三維整合型的系統級封裝(SiP)3D IC,以及同為3D整合型的矽穿孔(Through Silicon Via;TSV)3D IC等3種技術。 System in Package (SiP) is a new type of packaging technology that can configure all or most of the electronic functions of a system or subsystem on an integrated substrate. Compared with SOC, it is more compact and highly functional. The development cycle has the advantages of short cycle and low price. Among them, the system-in-package includes three-dimensional integrated system-in-package (SiP) 3D IC, and three technologies including 3D integrated through-chip (Through Silicon Via; TSV) 3D IC. .
但矽穿孔3D IC技術技術門檻與製造成本仍太高,應用尚未廣泛,故目前以如多晶片封裝(Multi-chip Package;MCP)技術、晶片堆疊(Stack Die)、層疊封裝(Package on Package;PoP)、PiP(Package in Package)、內埋式基板(Embedded Substrate)等技術為業界主流技術。 However, the threshold and manufacturing cost of the perforated 3D IC technology is still too high, and the application has not been widely used. Therefore, it is currently based on multi-chip package (MCP) technology, stack stacking, and package on package. PoP), PiP (Package in Package), embedded substrate (Embedded Technology such as Substrate) is the mainstream technology in the industry.
前述如MCP等技術的系統極封裝製程,皆是將數顆IC整合於一封裝體內,惟,整合前的IC通常並非皆為已知的良好晶片(known good die),欲將所有IC整合必然面臨整合前後的複雜測試過程以及散熱的問題,更甚者,當任一IC故障,則該3D IC只能整顆報廢。 The system package process such as the MCP technology integrates several ICs into one package. However, the ICs before integration are not all known good good chips, and it is necessary to integrate all ICs. Faced with the complex test process before and after integration and the problem of heat dissipation, even more, when any IC fails, the 3D IC can only be scrapped.
因此,如何在目前的系統級封裝技術提出一解決方案,實為一亟欲解決之問題。 Therefore, how to propose a solution in the current system-level packaging technology is a problem to be solved.
本創作主要目的在於提出一種便於組裝、擴充、測試與替換的封裝結構。 The main purpose of this creation is to propose a package structure that is easy to assemble, expand, test, and replace.
根據前述目的,本創作提出一種內嵌式封裝體結構,其包括:至少一封裝體,該封裝體包括至少一內嵌座體,該內嵌座體具有至少一連接端口,該連接端口開放於該封裝體外側。 According to the foregoing objective, the present invention provides an in-line package structure including: at least one package, the package includes at least one embedded body, the embedded body has at least one connection port, and the connection port is open to The outside of the package.
本創作特點在於,改進習知將IC整個於同一顆封裝體內卻導致單一IC故障而整顆IC報廢的缺失,以高腳數(high pin count)的內嵌式封裝體為載體,並透過將週邊IC插接於連接端口,藉由可依照不同功能的需求而插接週邊IC、模組、控制器(Controller),亦或以排線連接至其他系統或裝置,進而達到方便組裝、擴充、測試與替換IC零件的優點,因此,本創作具有縮短製程時間、降低積熱、節省成本以及增加良率的功效。 The feature of this creation is that it improves the conventional IC chip in the same package but causes a single IC failure and the entire IC is discarded. The high pin count embedded package is used as the carrier and The peripheral IC is plugged into the connection port, and the peripheral IC, the module, the controller (Controller) can be plugged according to the requirements of different functions, or connected to other systems or devices by the cable, thereby facilitating assembly, expansion, and Testing and replacing the advantages of IC parts, this creation has the effect of reducing process time, reducing heat buildup, saving costs, and increasing yield.
11、11b、11c、11d、11e、11f、11z‧‧‧連接端口 11, 11b, 11c, 11d, 11e, 11f, 11z‧‧‧ connection ports
1、1a、1b、1c、1d、1e、1f、1z‧‧‧內嵌座體 1, 1a, 1b, 1c, 1d, 1e, 1f, 1z‧‧‧ embedded body
21、21z、22‧‧‧金屬接點 21, 21z, 22‧‧‧ metal joints
2、2b、2c、2d、2e、2f、2z‧‧‧電路基板 2, 2b, 2c, 2d, 2e, 2f, 2z‧‧‧ circuit substrate
3、3b、3d、3e、3f、3z‧‧‧封裝體 3, 3b, 3d, 3e, 3f, 3z‧‧‧ package
4‧‧‧中介層 4‧‧‧Intermediary
5、5a、7、8‧‧‧電子載體 5, 5a, 7, 8‧‧‧ electronic carrier
a‧‧‧Micro-USB接頭 a‧‧‧Micro-USB connector
b‧‧‧連接組件 b‧‧‧Connecting components
c‧‧‧晶片 C‧‧‧chip
d‧‧‧電子元件 d‧‧‧Electronic components
p‧‧‧端子 P‧‧‧terminal
第1-1圖:為本創作製程第一實施例的組裝示意圖(一)。 Figure 1-1: Assembly diagram (1) of the first embodiment of the creative process.
第1-2圖:為本創作製程第一實施例的組裝示意圖(二)。 Figure 1-2: Assembly diagram (2) of the first embodiment of the creative process.
第1-3圖:為本創作製程第一實施例以另一態樣的內嵌座體來實施的組裝示意圖(一)。 Figure 1-3: Assembly diagram (1) of the first embodiment of the creative process implemented by another embodiment of the embedded body.
第1-4圖:為本創作製程第一實施例以另一態樣的內嵌座體來實施的組裝示意圖(二)。 Figure 1-4: Assembly diagram (2) of the first embodiment of the creative process implemented by another embodiment of the embedded body.
第1-5圖:為本創作製程第一實施例的組裝示意圖(三)。 Figure 1-5: Assembly diagram (3) of the first embodiment of the creative process.
第1-6圖:為本創作製程第一實施例以另一態樣的封裝體來實施的組裝示意圖(一)。 Figure 1-6: Assembly diagram (1) of the first embodiment of the creative process implemented by another aspect of the package.
第1-7圖:為本創作製程第一實施例以另一態樣的封裝體來實施的組裝示意圖(二)。 Figure 1-7: Assembly diagram (2) of the first embodiment of the authoring process implemented by another aspect of the package.
第2-1圖:為本創作製程第二實施例的組裝示意圖(一)。 Figure 2-1: Assembly diagram (1) of the second embodiment of the creative process.
第2-2圖:為本創作製程第二實施例的組裝示意圖(二)。 Figure 2-2: Schematic diagram of the assembly of the second embodiment of the authoring process (2).
第2-3圖:為本創作製程第二實施例的組裝示意圖(三)。 Figure 2-3: Assembly diagram (3) of the second embodiment of the authoring process.
第3圖:為本創作製程第三實施例的組裝示意圖。 Fig. 3 is a schematic view showing the assembly of the third embodiment of the creative process.
第4圖:為本創作結構的組合圖。 Figure 4: A combination of the creation structure.
以下配合所附的圖式,詳加說明本創作的結構如何組合、使用,應當更容易瞭解本創作的目的、技術內容、特點及其所達成的功效。 The following is a description of how the structure of the creation is combined and used in conjunction with the attached drawings. It should be easier to understand the purpose, technical content, characteristics and effects of the creation.
首先請參照第1-1圖至第1-5圖,說明本創作內嵌式封裝體結構的第一實施例,而為使本創作內容更易於了解,底下以製作一種USB 3.0/Micro-USB雙接頭快閃存儲碟的步驟為例說明。 First, please refer to the first embodiment of FIG. 1-1 to FIG. 1-5 to illustrate the first embodiment of the in-line package structure of the present invention, and to make the content of the creation easier to understand, a USB 3.0/Micro-USB is created underneath. The steps of the dual-connect flash memory disc are illustrated as an example.
如第1-1圖所示,本創作結構包括一封裝體3,該封裝體包括具有複數連接端口11的一內嵌座體1及一電路基板2,該電路基板 2具有快閃記憶體晶片(圖未示出)、控制電路(圖未示出)及USB 2.0、USB 3.0金屬接點21、22,該內嵌座體1可為固態封模材料(Epoxy Molding Compound,EMC)或射出成型的公座或母座,以下則皆以母座與連接端口為實施來說明;此時,該些連接端口11尚未外露於該封裝體3外側;如第1-2圖所示,該封裝體的連接端口11係可採用切割的方式外露,亦可透過將內嵌座體1放置在可使該些連接端口11、11a外露而開放於該封裝體3外側的特定位置,則該些連接端口11分別開放於該封裝體3外側;此外,內嵌座體以如第1-3圖所示的另一種態樣實施,其與第1-1圖差異在於此係以個別具有一連接端口11a的複數內嵌座體1a與電路基板2連接後再封裝來形成一封裝體3,接續如第1-4圖所示,此封裝體3經切割後,該些內嵌座體1a個別的連接端口11a外露於封裝體3;至此,即可輕易地如第1-2圖或第1-4圖所示將Micro-USB接頭a插接於該些連接端口11,後續再進一步如第1-5圖所示,以SMT技術或以卡合、接合後(亦可再選擇性地灌膠)的組裝式技術將USB 3.0連接組件b與該封裝體3連接(詳細組裝方式已揭露於中華民國專利證書號第M439795號說明書內文,該說明書內文主要包括將原USB 2.0介面之存儲碟升級為可用於USB 3.0介面存儲碟的技術特徵),形成一以內嵌式封裝體製程所完成之USB 3.0/Micro-USB的雙介面接頭快閃存儲碟的內嵌式封裝體結構;前述的封裝體係更可另以具有端子p的一封裝體3z實施,即 ,如第1-6圖所示,複數端子p得以射出包覆成型、卡勾或表面黏著技術設於連接端口11z中而與內嵌座體1z接合,此處以表面黏著技術(SMT)填膠為實施,並且,在接合後,該些端子p的一端係分別延伸而外露於該內嵌座體1z一側,該些端子p分別與該金屬接點21z接觸而與電路基板2z電性連接,最後,如第1-7圖所示透過封裝形成一封裝體3z,於此,可再接續安裝Micro-USB接頭a以供電源或資料的傳輸,完成一內嵌式封裝體結構。 As shown in FIG. 1-1, the creation structure includes a package body 3 including an embedded body 1 having a plurality of connection ports 11 and a circuit substrate 2, the circuit substrate 2 has a flash memory chip (not shown), a control circuit (not shown) and USB 2.0, USB 3.0 metal contacts 21, 22, the embedded body 1 can be a solid molding material (Epoxy Molding) Compound, EMC) or injection molded male or female seat, the following is described by the mother seat and the connection port; at this time, the connection ports 11 have not been exposed outside the package 3; As shown in the figure, the connection port 11 of the package can be exposed by cutting, or can be opened by placing the embedded body 1 on the outside of the package 3 so that the connection ports 11 and 11a can be exposed. In the position, the connection ports 11 are respectively open outside the package body 3; further, the embedded body is implemented in another aspect as shown in Figures 1-3, and the difference from the 1-1 figure is A plurality of embedded sockets 1a having a connection port 11a are connected to the circuit board 2 and then packaged to form a package body 3, as shown in FIGS. 1-4, after the package body 3 is cut, the insides are The individual connection ports 11a of the socket body 1a are exposed to the package body 3; thus, it can be easily as shown in Figure 1-2 or Figure 1-4. The micro-USB connector a is plugged into the connection ports 11 and further assembled as shown in Figures 1-5 by SMT technology or after snapping, bonding (and optionally potting). The technology connects the USB 3.0 connection component b to the package 3. The detailed assembly method has been disclosed in the specification of the Republic of China Patent No. M439795, which mainly includes upgrading the storage disk of the original USB 2.0 interface to be usable. The technical characteristics of the USB 3.0 interface storage disc) form an embedded package structure of the USB 3.0/Micro-USB dual interface connector flash memory disc completed by the embedded package system; the foregoing packaging system is more Alternatively, it can be implemented in a package 3z having a terminal p, that is, As shown in FIG. 1-6, the plurality of terminals p can be injection-molded, hooked or surface-adhesive technology is disposed in the connection port 11z to be engaged with the embedded body 1z, where the surface adhesion technology (SMT) is used for filling. For the implementation, and after the bonding, the terminals p are respectively extended and exposed on the side of the embedded body 1z, and the terminals p are respectively in contact with the metal contacts 21z and electrically connected to the circuit substrate 2z. Finally, a package 3z is formed through the package as shown in FIGS. 1-7. Here, the Micro-USB connector a can be further connected for power source or data transmission to complete an in-line package structure.
現有一般多晶片封裝技術是將兩種以上的記憶體晶片,透過水平放置與(或)堆疊(垂直)方式整合而封裝在同一個BGA封裝裡,而本創作的第一實施例則針對多晶片封裝技術的創新應用結構,請參照第2-1圖至第2-3圖,其包括:接續,本創作的第二實施例,得以一可為高腳數的球柵陣列(BGA)或格柵陣列(LGA)的封裝體3b實施,本實施例的封裝體3b以一BGA的封裝體3b為實施,其包括複數內嵌座體1b及一電路基板2b,該些內嵌座體1b分別設於該電路基板2b一側,其中,該些內嵌座體1b分別具有複數連接端口11b,該電路基板2b具有複數晶片a或電子元件b,該電路基板2b上的引腳接引至各單邊,該些內嵌座體1b對應接引至各單邊的引腳而分設於該電路基板2b的四側;其中,本創作結構在製程中係將內嵌座體1b預先設置於特定位置後再封裝,故該些連接端口11b外露而開放於該封裝體3b的四週緣;接續,本創作更包括設於該封裝體3b一側的中介層4,透過 該中介層4,該封裝體3b可進一步與一電子載體5堆疊連結,其中該中介層4進一步為散熱膏、矽基板、墊片或薄膜,而該電子載體5可為任一電路基板或任一種封裝體,而本實施例之中介層4、電子載體5係如第1-2圖所示,分別以一散熱膏及LGA封裝體為實施;而為了防止堆疊後產生電磁干擾(EMI),封裝體3b的電路基板2b上或電子載體5上可具有濺鍍處理層(圖未示出),或者,堆疊的封裝體或電子載體之間更包括一金屬材質層。藉此,使本創作為一組裝容易、快速、成本低且改善散熱問題的內嵌式封裝體結構;於此該封裝體3b更可進一步應用而包括具有插接頭的至少一電子載體7,此電子載體7可為另一電路基板或晶片或電子元件或封裝體或作為傳輸用的線路接頭,例如週邊IC、控制器、LGA或BGA封裝體、排線,訊號線、傳輸線(圖未示出),該電子載體7插接於該步驟2之封裝體3b的該些連接端口11b,形成一由內嵌式封裝體堆疊插接週邊IC的系統級封裝產品。 The conventional multi-chip package technology is to package two or more types of memory chips in the same BGA package through horizontal placement and/or stacking (vertical) integration, and the first embodiment of the present invention is directed to multi-chip. For the innovative application structure of the packaging technology, please refer to FIG. 2-1 to FIG. 2-3, which includes: Continuation, the second embodiment of the present creation, a ball grid array (BGA) or lattice which can be a high number of balls The package body 3b of the gate array (LGA) is implemented. The package body 3b of the present embodiment is implemented by a package 3b of a BGA, and includes a plurality of embedded body 1b and a circuit substrate 2b, and the embedded body 1b is respectively The circuit board 2b has a plurality of connection ports 11b, and the circuit board 2b has a plurality of chips a or electronic components b, and the pins on the circuit board 2b are connected to the respective On one side, the embedded body 1b is respectively connected to the pins of the single sides and is disposed on the four sides of the circuit board 2b. The authored structure pre-sets the embedded body 1b in the process. After being sealed at a specific location, the connection ports 11b are exposed and open to the package. Four weeks edge 3b; splicing, the present writing further includes an interposer. 4 disposed on the side 3b of the package body, through The interposer 4, the package 3b may be further connected to an electronic carrier 5, wherein the interposer 4 is further a heat dissipating paste, a crucible substrate, a spacer or a film, and the electronic carrier 5 may be any circuit substrate or any A package body, and the interposer 4 and the electron carrier 5 of the embodiment are implemented as a heat dissipating paste and an LGA package as shown in FIG. 1-2; and in order to prevent electromagnetic interference (EMI) after stacking, The circuit board 2b of the package 3b or the electronic carrier 5 may have a sputtering treatment layer (not shown), or the stacked package or the electronic carrier further includes a metal material layer. Therefore, the present invention is an in-line package structure that is easy to assemble, fast, low in cost, and improved in heat dissipation. The package 3b is further applicable to include at least one electronic carrier 7 having a plug connector. The electronic carrier 7 can be another circuit substrate or wafer or electronic component or package or as a line connector for transmission, such as a peripheral IC, a controller, an LGA or BGA package, a cable, a signal line, a transmission line (not shown) The electronic carrier 7 is plugged into the connection ports 11b of the package 3b of the step 2 to form a system-in-package product in which the peripheral ICs are plugged into the package by the embedded package.
再如第3圖所示意,用以說明本創作第三實施例,其係將第一實施例中以LGA封裝體實施的電子載體5以另一以LGA封裝的電子載體5a(即此電子載體5a包括相互連接的至少一內嵌座體1c與一電路基板2c,該內嵌座體具有複數連接端口11c)來實施;進一步來說,本實施例的封裝體3b與該電子載體5a堆疊連結後,更進一步包括至少一連接件6,該連接件6電性連接於該連接端口11c及該連接端口11b,而該連接件6可為電線或導電膠或運用線路重佈(redistribution layer,RDL)技術的鍍線;再如第3圖所示意,用以說明本創作第三實施例,其係將第 一實施例中以LGA封裝體實施的電子載體5以另一以LGA封裝的電子載體5a(即此電子載體5a包括相互連接的至少一內嵌座體1c與一電路基板2c,該內嵌座體具有複數連接端口11c)來實施;進一步來說,本實施例的封裝體3b與該電子載體5a堆疊連結後,更進一步包括至少一連接件6,該連接件6電性連接於該連接端口11c及該連接端口11b,而該連接件6可為電線或導電膠或運用線路重佈(redistribution layer,RDL)技術的鍍線;此外,若該些水平插接於該電子載體5a的電子載體7係分別為具有如前述連接端口11b、11c的電子載體5、5a,則該些電子載體7亦可再供其他具有插接頭電子載體進行水平的插接而達到更佳的擴充度,並且,每一電子載體7亦皆可再藉由中介層4進行垂直的堆疊,由於本創作之結構是極具彈性的混合式應用(即水平擺放與垂直堆疊兼具的擴充方式),因此,本創作的結構深具良好的應用性與擴充性。 3 is a schematic view for explaining the third embodiment of the present invention, which is to use the electronic carrier 5 implemented in the LGA package in the first embodiment as another electronic carrier 5a encapsulated in LGA (ie, the electronic carrier). 5a includes at least one embedded body 1c and a circuit substrate 2c connected to each other, the embedded body having a plurality of connection ports 11c); further, the package 3b of the embodiment is stacked with the electronic carrier 5a And further comprising at least one connecting member 6 electrically connected to the connecting port 11c and the connecting port 11b, and the connecting member 6 can be a wire or a conductive adhesive or a redistribution layer (RDL) The plating line of the technology; as shown in Fig. 3, to illustrate the third embodiment of the creation, the system will be In one embodiment, the electronic carrier 5 implemented in the LGA package is in another LGA-encapsulated electronic carrier 5a (ie, the electronic carrier 5a includes at least one embedded body 1c and a circuit substrate 2c connected to each other, the embedded frame The body has a plurality of connection ports 11c) for implementation; further, after the package body 3b of the embodiment is stacked and coupled with the electronic carrier 5a, the package body 3b further includes at least one connector 6 electrically connected to the connection port. 11c and the connection port 11b, and the connecting member 6 can be a wire or a conductive adhesive or a plating line using a redistribution layer (RDL) technology; in addition, if the horizontally inserted electronic carriers of the electronic carrier 5a 7 is an electronic carrier 5, 5a having the above-mentioned connection ports 11b, 11c, respectively, and the electronic carriers 7 can be further inserted into other plug-in electronic carriers for horizontal expansion to achieve a better degree of expansion, and Each of the electronic carriers 7 can also be vertically stacked by the interposer 4, and since the structure of the present invention is a highly flexible hybrid application (ie, an expansion method of horizontal placement and vertical stacking), creation Good application of the deep structure and scalability.
再者,如第4圖中所示,為本創作第四實施例之堆疊為三層的結構,其係包括複數封裝體3d、3e、3f(封裝體3d以BGA封裝為實施、封裝體3e、3f以LGA封裝為實施),該些封裝體3d、3e、3f分別藉由複數中介層4連接複數電路基板2d、2e、2f,該些封裝體3d、3e、3f內分別具有一內嵌座體1d、1e、1f,該些內嵌座體1d、1e、1f分別具有複數連接端口11d、11e、11f,該些連接端口11d、11e、11f開放於該封裝體3d外側,續此,本創作內嵌式封裝體結構更包括至少一電子載體8,該電子載體8與該封裝體3d的該連接端口11d電性連接,而該電子載體8與前述電子載體7相同,得以具有插接頭的的一電路基板或具有插接頭的一 封裝體或作為傳輸用的線路實施。 Furthermore, as shown in FIG. 4, the structure of the fourth embodiment is a stack of three layers, which includes a plurality of packages 3d, 3e, and 3f (the package 3d is implemented by a BGA package, and the package 3e is implemented). 3f, 3e, 3f are respectively connected to the plurality of circuit boards 2d, 2e, 2f by a plurality of interposers 4, and each of the packages 3d, 3e, 3f has an in-line The socket bodies 1d, 1e, and 1f respectively have a plurality of connection ports 11d, 11e, and 11f, and the connection ports 11d, 11e, and 11f are open to the outside of the package body 3d. The in-line package structure further includes at least one electronic carrier 8 electrically connected to the connection port 11d of the package 3d, and the electronic carrier 8 is identical to the electronic carrier 7 to have a plug connector. a circuit substrate or a plug having a plug connector The package is implemented as a line for transmission.
如上所述,當本創作以第一實施例實施時,本創作結構則更包括由中介層連結個別的封裝體的堆疊結構,據此堆疊結構,亦以一連接件電性連接該個別的封裝體相對應的連接端口,以完成應用於系統級封裝的內嵌式封裝體結構。 As described above, when the present invention is implemented in the first embodiment, the authoring structure further includes a stack structure in which individual packages are connected by an interposer, and according to the stack structure, the individual packages are electrically connected by a connecting member. The corresponding connection port of the body to complete the embedded package structure applied to the system-in-package.
本創作在實際產品的應用上,可將同類型的產品進行連結,如快閃記憶體產品的堆疊,或者,將達上千腳數的高腳數產品或較為複雜或應用在高頻(如3D封裝產品、MCP、eMCP)的產品作為載體(例如一無線通訊模組),再進一步串連其他的周邊IC封裝體(例如串接一GPS定位模組及一多媒體模組)。 This creation can link the same type of products in the application of actual products, such as the stacking of flash memory products, or the high number of products that will reach thousands of feet or more complex or applied at high frequencies (such as The 3D package product, MCP, eMCP) product is used as a carrier (for example, a wireless communication module), and further connected to other peripheral IC packages (for example, a GPS positioning module and a multimedia module).
綜上所述,本創作應用在如3D IC的系統級封裝時,得以垂直堆疊、水平插接、堆疊與插接混合或水平插接後再堆疊與插接等方式來實施,可達到良好的應用性,不僅解決習知將所有IC整合於同一堆疊上的缺失而提高良率,更具有節省時間、方便組裝與方便測試的功效。 In summary, the application is implemented in a system-level package such as a 3D IC, which can be implemented by vertical stacking, horizontal plugging, stacking and plugging, or horizontally plugging, stacking and plugging, etc. Applicability not only solves the problem of knowing that all ICs are integrated on the same stack, but also improves the yield, saves time, facilitates assembly and facilitates testing.
惟前述者僅為本創作的較佳實施例,其目的在使熟習該項技藝者能夠瞭解本創作的內容而據以實施,並非用來限定本創作實施的範圍;故舉凡依本創作申請範圍所述的形狀、構造及特徵所為的均等變化或修飾,均應包括在本創作的申請專利範圍內。 The foregoing is only a preferred embodiment of the present invention, and its purpose is to enable the skilled person to understand the content of the present invention and implement it, and is not intended to limit the scope of the present invention; Equivalent variations or modifications of the shapes, configurations, and features described herein are intended to be included within the scope of the present application.
1b‧‧‧內嵌座體 1b‧‧‧Inlay body
11b‧‧‧連接端口 11b‧‧‧Connect port
2b‧‧‧電路基板 2b‧‧‧ circuit board
3b‧‧‧封裝體 3b‧‧‧Package
4‧‧‧中介層 4‧‧‧Intermediary
5‧‧‧電子載體 5‧‧‧Electronic carrier
7‧‧‧電子載體 7‧‧‧Electronic carrier
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CN113178421B (en) * | 2021-04-08 | 2022-03-29 | 深圳市磐锋精密技术有限公司 | Multi-chip packaging positioning device and method for mobile phone integrated circuit |
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