TWM468097U - Timing generator for power converter - Google Patents

Abstract

A timing generator for a power converter is provided. The timing generator includes a logic control unit, a time adjusting unit, and a ramp generating unit. The logic control unit is coupled to the time adjusting unit and the ramp generating unit. The logic control unit receives a comparing signal by a first comparator, and receives the first control signal and the second control signal, so as to provide a pulse width modulation signal. The logic control unit can change a width of a turning-on time or a width of a turning-off time in response to a load transient, and a sum of the turning-on time and the turning-off time in different periods is maintained at a fixed value.

Description

Power converter time generator

This creation is about a power conditioning technique, and in particular, a time generator for a power converter.

1 is a schematic diagram of a conventional power converter. Figure 2 is a schematic diagram of the waveforms in the power converter. Please refer to Figure 1 and Figure 2. The design of existing power converters 100 often employs a fixed on-time architecture. The comparator 110 compares the error signal Xerr with the ramp signal Xramp to generate a comparison signal Xcm. The time control circuit 120 sets the pulse width modulation signal Xpwm according to the comparison on-time mechanism Xcm using a fixed on-time mechanism, wherein the width of the on-time Ton is related to the input voltage Vin and the output voltage Vout, and the width of the on-time Ton is a fixed value.

In the power converter 100, when the output time Ton is outputted by the error signal Xerr and the ramp signal Xramp, the magnitude of the error signal Xramp is related to both the feedback signal Vfb and the reference voltage Vref. And at the timing of outputting the on-time Ton, the time control circuit 120 starts calculating and generating the pulse width modulation signal Xpwm, and the on-time Ton of each period in the pulse width modulation signal Xpwm is fixed. However, the conventional pulse width modulation operation architecture can achieve a fixed frequency effect. However, when the output voltage Vout changes as the load current Iload changes, the time control circuit 120 still supplies the same energy at each cycle at a fixed frequency, so that the power converter 100 performs during the load transient. Not good.

3 is a circuit diagram of a conventional time control circuit. Please refer to Figure 3. The time control circuit 320 includes a current source It, transistors MP1 and MP2, a switch S1, a capacitor C1, and a comparator 322. The current mirror is composed of a current source It, a transistor MP1 and an MP2. The current source It is related to the input voltage Vin. When the pulse width modulation signal is logic high level, the reverse signal PWMB of the pulse width modulation signal is a logic low level, thus turning off the switch S1, and charging the capacitor C1 with the current M*It related to the current source It until charging The counting of the on-time Ton is ended when the voltage Xc is greater than the output voltage Vout.

Although the conventional technique can achieve a fixed frequency effect for the pulse width modulation signal, when the load voltage changes instantaneously, the time control circuit outputs the pulse wave of the same energy every cycle while counting the on time. Thus, when the load changes instantaneously, the time control circuit cannot quickly converge the output voltage, and thus performs poorly. In addition, in order to achieve the fixed frequency operation of the power converter, the time control circuit needs to extract the input voltage and the output voltage information to calculate the on-time, and also needs an additional integrated circuit input pin or used for A circuit that draws input voltage and output voltage.

In view of this, the present invention proposes a time generator for a power converter to solve the problems described in the prior art.

The present invention provides a time generator for a power converter, the time generator including a logic control unit, a time adjustment unit, and a ramp generation unit. Logical control The unit receives the comparison signal via the first comparator, and receives the first control signal and the second control signal, and provides a pulse width modulation signal, a third control signal, and a fourth control signal, wherein the first comparator compares the first ramp signal A comparison signal is generated with an error signal associated with the output voltage of the power converter. The time adjustment unit is coupled to the logic control unit, receives the third control signal and the error signal, generates a second ramp signal according to the third control signal, and outputs the first control signal to the logic control according to the second ramp signal and the first threshold voltage unit. The ramp generating unit is coupled to the logic control unit, receives the fourth control signal, the error signal and the second threshold voltage, generates a first ramp signal according to the fourth control signal, and outputs the second control according to the first ramp signal and the error signal Signal to the logic control unit.

In an embodiment of the present invention, the first ramp signal generated by the ramp generating unit and the second ramp signal generated by the time adjusting unit have the same absolute value of the falling slope.

In an embodiment of the present creation, the logic control unit includes a first switch, a second switch, a first inverter, and a second inverter. The control terminal of the first switch receives the comparison signal. The second end of the first switch is coupled to the ground. The control terminal of the second switch receives the first control signal. The second end of the second switch is coupled to the ground. The input end of the first inverter is coupled to the first end of the first switch. The output of the first inverter is coupled to the first end of the second switch. The input end of the second inverter is coupled to the first end of the second switch. The output end of the second inverter is coupled to the first end of the first switch. The third inverter, the second inverter and the first switch are coupled to generate a third control signal.

In an embodiment of the present creation, the logic control unit includes a third switch, a fourth switch, a third inverter, and a fourth inverter. The control terminal of the third switch receives the first control signal. The second end of the third switch is coupled to the ground. Control of the fourth switch The terminal receives the second control signal. The second end of the fourth switch is coupled to the ground. The input end of the third inverter is coupled to the first end of the third switch. The output end of the third inverter is coupled to the first end of the fourth switch. The input end of the fourth inverter is coupled to the first end of the fourth switch. The output end of the fourth inverter is coupled to the first end of the third switch. The fourth inverter, the fourth inverter and the third switch are coupled to generate a fourth control signal.

In an embodiment of the present creation, the time adjustment unit includes a first amplifier, a fifth switch, a first capacitor, a first current source, and a second comparator. A first input of the first amplifier receives the error signal. A second input of the first amplifier is coupled to its output. The control terminal of the fifth switch receives the third control signal. The first end of the fifth switch is coupled to the output of the first amplifier. The first end of the first capacitor is coupled to the second end of the fifth switch. The second end of the first capacitor is coupled to the ground. The first current source is connected in parallel with the first capacitor. A second ramp signal is generated at a junction of the first current source and the first end of the first capacitor. A first input of the second comparator receives the first threshold voltage. A second input of the second comparator receives the second ramp signal. The output of the second comparator outputs a first control signal.

In an embodiment of the present creation, the ramp wave generating unit includes a second amplifier, a sixth switch, a second capacitor, a second current source, and a third comparator. A first input of the second amplifier receives a second threshold voltage, and a second input of the second amplifier is coupled to an output thereof. The control end of the sixth switch receives the fourth control signal, and the first end thereof is coupled to the output end of the second amplifier. The first end of the second capacitor is coupled to the second end of the sixth switch. The second end of the second capacitor is coupled to the ground. The second current source is connected in parallel with the second capacitor. A coupling of the second current source to the first end of the second capacitor produces a first ramp signal. The first input of the third comparator receives the error signal, the second input receives the first ramp signal, and the output outputs the second control signal.

In an embodiment of the present invention, the relationship between the first threshold voltage and the second threshold voltage used by the time generator and the error signal is as follows: the error signal is a variable signal, the second threshold voltage is greater than the error signal, and the error signal Greater than the first threshold voltage.

In an embodiment of the present creation, the difference between the first threshold voltage and the second threshold voltage is a fixed value.

In an embodiment of the present invention, the sum of the on-time and the off-time of the pulse width modulation signal output by the logic control unit in each cycle is a fixed value.

In an embodiment of the present invention, the time generator determines an on-time in a period of the pulse width modulation signal according to the error signal, the first ramp signal, and the first threshold voltage, and according to the error signal, the second ramp signal, The first threshold voltage and the second threshold voltage determine an off time in the period.

Based on the above, in the present creation, the time generator of the power converter generates a pulse width modulation signal of a fixed frequency using an error signal associated with the output voltage and an adjustment means for the on time and the off time. The logic control unit can change the width of the on-time or the width of the off-time according to the instantaneous change of the load, and the sum of the on-time and the off-time in the different periods maintains a fixed value. Since the pulse width modulation signal provided by the time generator can effectively accelerate the convergence output voltage when the load changes instantaneously, the output voltage can be stabilized and the oscillation time can be shortened, thereby solving the problems described in the prior art.

In order to make the above features and advantages of the present invention more comprehensible, the following embodiments are described in detail with reference to the accompanying drawings.

100‧‧‧Power Converter

110‧‧‧ comparator

120‧‧‧Time Control Circuit

10‧‧‧Time generator

12‧‧‧Logical Control Unit

13‧‧‧Time adjustment unit

14‧‧‧ ramp generation unit

20‧‧‧ drive

30‧‧‧Output level

31‧‧‧Upper bridge switch

32‧‧‧Bridge switch

40‧‧‧Return circuit

50‧‧‧Amplifier

60‧‧‧Compensation circuit

70‧‧‧ comparator

121‧‧‧ first unit

121A, 121B‧‧ ‧ switch

121C, 121D‧‧‧ Inverter

122‧‧‧Second unit

122A, 122B‧‧ ‧ switch

122C, 122D‧‧‧ Inverter

131‧‧‧Amplifier

133‧‧‧ comparator

134‧‧‧ switch

141‧‧‧ comparator

143‧‧‧Amplifier

144‧‧‧ switch

320‧‧‧Time Control Circuit

322‧‧‧ comparator

400‧‧‧Power Converter

C, C1, Cramp, Cton‧‧‧ capacitors

CM‧‧‧ comparison signal

Err‧‧‧ error signal

GND‧‧‧ ground terminal

Iload‧‧‧ load current

Iramp, It, Iton‧‧‧ current source

L‧‧‧Inductors

MP1, MP2‧‧‧ transistor

M*It‧‧‧ Current

PWMB‧‧‧reverse signal

SLP1, SLP2‧‧‧ falling slope

S1‧‧ switch

Ton‧‧‧ On time

Toff‧‧‧ disconnection time

X1~X4‧‧‧ control signal

Xc‧‧‧Charging voltage

Xcm‧‧‧ comparison signal

Xerr‧‧‧ error signal

Xpwm‧‧‧ pulse width modulation signal

Xramp‧‧‧ ramp signal

VLB, VUB‧‧‧ threshold voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vfb‧‧‧ feedback signal

Vpwm‧‧‧ pulse width modulation signal

Vref‧‧‧reference voltage

Vramp, Vton‧‧‧ ramp signal

The following drawings are a part of the specification of the present invention, which shows an exemplary embodiment of the present invention, which is used together with the description of the specification to explain the principles of the present invention.

1 is a schematic diagram of a conventional power converter.

Figure 2 is a schematic diagram of the waveforms in the power converter.

3 is a circuit diagram of a conventional time control circuit.

4 is a block diagram of a power converter in accordance with an embodiment of the present invention.

Figure 5 is a schematic illustration of a time generator related signal in accordance with an inventive embodiment.

FIG. 6 is a circuit diagram for calculating the on-time among the time generators according to the present creative embodiment.

FIG. 7 is a circuit diagram for calculating a turn-off time among time generators according to the present creative embodiment.

8A through 8H are schematic diagrams of eight variations of a time generator in accordance with the present creative embodiment.

Reference will now be made in detail to the embodiments of the present invention, and in the drawings In addition, the same or similar reference numerals or components used in the drawings and the embodiments are used to represent the same or similar parts.

4 is a block diagram of a power converter in accordance with an embodiment of the present invention. Please refer to Figure 4. The power converter 400 has an automatic frequency fixed loop control mechanism including a driver 20, an output stage 30, an inductor L, a capacitor C, a feedback circuit 40, an amplifier 50, a compensation circuit 60, a comparator 70, and a time generator 10.

Amplifier 50 can be a transconductance amplifier, and in other embodiments, amplifier 50 can be an error amplifier. A first input of amplifier 50 receives a reference voltage Vref and a second input of amplifier 520 receives a feedback signal Vfb. The feedback signal Vfb is a proportional signal of the output voltage Vout. The amplifier 50 provides an error signal Err based on the reference voltage Vref and the feedback signal Vfb. The compensation circuit 60 is used to compensate and stabilize the error signal Err.

The time generator 10 includes a logic control unit 12, a time adjustment unit 13, and a ramp generation unit 14. The time generator 10 determines the on-time Ton in the period of the pulse width modulation signal Vpwm according to the error signal Err, the ramp signal Vramp and the threshold voltage VLB, and according to the error signal Err and the ramp signal (as shown in FIG. 5 or FIG. 6) The indicated Vton), the threshold voltage VLB and the threshold voltage VUB determine the off time Toff in the period.

The logic control unit 12 is coupled to the time adjustment unit 13 and the ramp wave generating unit 14. The ramp wave generating unit 14 is controlled by the logic control unit 12 and is used to generate the ramp signal Vramp. In addition, the ramp signal Vramp may also be referred to as a ramp-like signal, a triangular wave signal or a sawtooth wave signal, which may be a ramp-wave in a repeat-descent form or a ramp-wave in a repeat-rise form, depending on the application.

The first input of comparator 70 receives error signal Err and the second input of comparator 70 receives ramp signal Vramp. The error signal Err is associated with the output voltage Vout of the power converter 400. The comparator 70 compares the ramp signal Vramp with the error signal Err and generates a comparison signal CM, and outputs a comparison signal CM to the logic control unit 12.

The generation of the comparison signal CM is related to the error signal Err. The logic control unit 12 receives the comparison signal CM via the comparator 70, and thus can be determined according to the comparison signal CM Whether to reset the ramp signal Vramp and issue a control signal X3 or X4.

The time adjustment unit 13 receives the control signal X3 and the error signal Err, generates a ramp signal according to the control signal X3 (such as Vton as shown in FIG. 5 or FIG. 6), and outputs the control signal X1 according to the ramp signal and the threshold voltage VLB. Logic control unit 12.

The ramp wave generating unit 14 receives the control signal X4, the error signal Err, and the threshold voltage VUB, generates the ramp signal Vramp according to the control signal X4, and outputs the control signal X2 to the logic control unit 12 according to the ramp signal Vramp and the error signal Err. Further, the threshold voltage VUB is greater than the threshold voltage VLB.

The logic control unit 12 supplies the pulse width modulation signal Vpwm in accordance with the obtained on-time Ton and off-time Toff. See Figure 5. The sum of the on-time Ton and the off-time Toff of the pulse width modulation signal Vpwm outputted by the logic control unit 12 in each period is a fixed value, and thus a pulse width modulation signal Vpwm of a fixed frequency will be supplied.

The driver 20 drives the output stage 30 based on the pulse width modulation signal Vpwm to thereby control the high side switch 31 and the low side switch 32 in the output stage 30. The output stage 30 is used for DC-to-DC conversion of the input voltage Vin, so that the power converter 400 can generate the output voltage Vout and output it to the load. In addition, when the load changes instantaneously, the output voltage Vout will vary with the load current Iload.

Figure 5 is a schematic illustration of a time generator related signal in accordance with an inventive embodiment. Please refer to Figure 4 and Figure 5 together. The relationship between the threshold voltage VLB, the threshold voltage VUB, and the error signal Err used by the time generator 10 is as follows: the error signal Err is a fluctuating signal, the threshold voltage VUB is greater than the error signal Err, and the error signal Err Greater than the threshold voltage VLB. The threshold voltage VUB and the threshold voltage VLB are used to determine a calculation window of the loop switching frequency. The difference between the threshold voltage VUB and the threshold voltage VLB is a fixed value.

The ramp wave signal Vramp generated by the ramp wave generating unit 14 has the same falling slope absolute value as the ramp wave signal Vton generated by the time adjusting unit 13. The ramp signal Vramp, the ramp signal Vton, and the upper bound (VUB) and lower bound (VLB) of the calculation window determine the loop switching frequency. The on-time Ton is calculated from the error signal Err to the threshold voltage VLB and the falling slope SLP1 of the ramp signal Vton. The off time Toff is calculated from the threshold voltage VUB to the error signal Err and the falling slope SLP2 of the ramp signal Vramp.

When the on-time Ton is calculated, the ramp signal Vramp is clamped to the level of the threshold voltage VUB; when the off-time Toff is calculated, the ramp signal Vton is clamped to the level of the error signal Err.

The falling slope SLP1 of the ramp signal Vton can be expressed as Equation 1 below.

The Iton and Cton in Equation 1 respectively represent the current value of the current source and the capacitance value of the capacitor, which will be described in detail later in the time adjustment unit 13 of the embodiment (Fig. 6 embodiment).

The falling slope SLP2 of the ramp signal Vramp can be expressed as Equation 2 below.

The Iramp and Cramp in Equation 2 respectively indicate the current value of the current source and the capacitance value of the capacitor, which will be described in detail later in the ramp generating unit 14 of the embodiment (Fig. 7 embodiment).

Since the falling slope SLP1 is equal to the falling slope SLP1, it can be expressed as Equation 3: SLP1 = SLP2 (Equation 3).

Further, the relationship between the threshold voltages VUB, VLB and the time T of one cycle can be expressed as Equation 4 below.

Deriving Equation 4 to obtain time T can be expressed as Equation 5 below.

The reciprocal of the time T is the switching frequency FSW, which can be expressed as Equation 6 below.

Similar to Equation 5, the on-time Ton and off-time Toff can be calculated and can be expressed as Equations 7 and 8 below.

Calculate the task period according to Equation 7 and the threshold voltages VUB, VLB The percentage Duty can be expressed as Equation 9 below.

The logic control unit 12 can change the width of the on-time Ton in response to the instantaneous change of the load, and the sum (time T) of the on-time Ton and the off-time Toff in the different periods maintains a fixed value. Therefore, this creation can provide accelerated energy to accelerate the convergence output voltage regardless of the case of light load to heavy load or heavy load to light load, and the pulse width modulation signal Vpwm The sum of the on-time Ton and the off-time Toff in each cycle is maintained at a fixed value. Therefore, the time generator 10 can automatically generate the pulse width modulation signal Vpwm of a fixed frequency. Further, the time generator 10 does not need to extract the information of the input voltage Vin when determining the width of the on-time Ton.

FIG. 6 is a circuit diagram for calculating the on-time among the time generators according to the present creative embodiment. FIG. 7 is a circuit diagram for calculating a turn-off time among time generators according to the present creative embodiment.

Please refer to Figure 4, Figure 6 and Figure 7. The logic control unit 12 includes a first unit 121 and a second unit 122. The first unit 121 includes switches 121A and 121B, and inverters 121C and 122D. The control terminal of the switch 121A receives the comparison signal CM. The second end of the switch 121A is coupled to the ground GND. The control terminal of the switch 121B receives the control signal X1. The second end of the switch 121B is coupled to the ground GND. The input end of the inverter 121C is coupled to the first end of the switch 121A. The output end of the inverter 121C is coupled to the first end of the switch 121B. The input end of the inverter 121D is coupled to the first end of the switch 121B. The output end of the inverter 121D is coupled to the first end of the switch 121A. A coupling signal is generated at the coupling of the inverters 121C and 121D with the switch 121A.

The second unit 122 includes switches 122A and 122B, inverters 122C and 122D. The control terminal of switch 122A receives control signal X1. The second end of the switch 122A is coupled to the ground GND. The control terminal of switch 122B receives control signal X2. The second end of the switch 122B is coupled to the ground GND. The input end of the inverter 122C is coupled to the first end of the switch 122A. The output of the inverter 122C is coupled to the first end of the switch 122B. The input end of the inverter 122D is coupled to the first end of the switch 122B. The output of the inverter 122D is coupled to the first end of the switch 122A. A coupling signal is generated at the coupling of inverters 122C and 122D to switch 122A.

The time adjustment unit 13 includes an amplifier 131, a switch 134, a capacitor Cton, a current source Iton, and a comparator 133. The first input of amplifier 131 receives an error signal Err. A second input of the amplifier 131 is coupled to its output. The control terminal of switch 134 receives control signal X3. The first end of the switch 134 is coupled to the output of the amplifier 131. The first end of the capacitor Cton is coupled to the second end of the switch 134. The second end of the capacitor Cton is coupled to the ground GND. The current source Iton is connected in parallel with the capacitor Cton. A coupling of the current source Iton to the first end of the capacitor Cton produces a ramp signal Vton. The first input of comparator 133 receives a threshold voltage VLB. The second input of the comparator 133 receives the second ramp signal Vton. The output of the comparator 133 outputs a control signal X1.

The ramp wave generating unit 14 includes an amplifier 143, a switch 144, a capacitor Cramp, a current source Iramp, and a comparator 141. A first input of amplifier 143 receives a threshold voltage VUB, and a second input of amplifier 143 is coupled to its output. The control terminal of the switch 144 receives the control signal X4, and the first end thereof is coupled to the output of the amplifier 143. The first end of the capacitor Cramp is coupled to the second end of the switch 144. The second end of the capacitor Cramp is coupled to the ground GND. Current source Iramp and capacitor Cramp Connected in parallel. A ramp signal Vramp is generated at a coupling of the current source Iramp to the first end of the capacitor Cramp. The first input of the comparator 141 receives the error signal Err, the second input receives the ramp signal Vramp, and the output thereof outputs the control signal X2.

8A through 8H are schematic diagrams of eight variations of a time generator in accordance with the present creative embodiment. Please refer to FIG. 8A to FIG. 8H. As shown in FIG. 8A to FIG. 8H, the ramp signal Vramp and the ramp signal Vton may be a ramp wave in a repeat-descent form or a ramp wave in a repeat-rise form, and calculate a discharge slope of the on-time Ton and the off-time Toff. The absolute values are equal, so there are eight combinations of variations. Referring to the above description for FIG. 5, the on-time Ton and the off-time Toff of the pulse width modulation signal Vpwm are respectively calculated using the error signal Err and the preset threshold voltages VUB and VLB.

In summary, in the present creation, the time generator of the power converter generates a pulse width modulation signal of a fixed frequency by using an error signal associated with the output voltage and an adjustment means for the on time and the off time. The logic control unit can change the width of the on-time or the width of the off-time according to the instantaneous change of the load, and the sum of the on-time and the off-time in the different periods maintains a fixed value. Since the pulse width modulation signal provided by the time generator can effectively accelerate the convergence output voltage when the load changes instantaneously, the output voltage can be stabilized and the oscillation time can be shortened, thereby solving the problems described in the prior art.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of this creation is subject to the definition of the scope of the patent application.

In addition, any embodiment or application of the present invention is not required to achieve all of the objects or advantages or features disclosed in the present disclosure. In addition, the summary section and title are only It is used to assist in the search of patent documents and is not intended to limit the scope of patents in this creation.

10‧‧‧Time generator

12‧‧‧Logical Control Unit

13‧‧‧Time adjustment unit

14‧‧‧ ramp generation unit

20‧‧‧ drive

30‧‧‧Output level

31‧‧‧Upper bridge switch

32‧‧‧Bridge switch

40‧‧‧Return circuit

50‧‧‧Amplifier

60‧‧‧Compensation circuit

70‧‧‧ comparator

400‧‧‧Power Converter

C‧‧‧ capacitor

CM‧‧‧ comparison signal

Err‧‧‧ error signal

Iload‧‧‧ load current

L‧‧‧Inductors

Ton‧‧‧ On time

Toff‧‧‧ disconnection time

X1~X4‧‧‧ control signal

VLB, VUB‧‧‧ threshold voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vfb‧‧‧ feedback signal

Vpwm‧‧‧ pulse width modulation signal

Vref‧‧‧reference voltage

Vramp‧‧‧ ramp signal

Claims (10)

A time generator for a power converter, comprising: a logic control unit, receiving a comparison signal via a first comparator, and receiving a first control signal and a second control signal to provide a pulse width modulation signal, a third control signal and a fourth control signal, wherein the first comparator compares a first ramp signal with an error signal associated with an output voltage of the power converter to generate the comparison signal; a time adjustment unit, The logic control unit is coupled to receive the third control signal and the error signal, generate a second ramp signal according to the third control signal, and output the first according to the second ramp signal and a first threshold voltage a control signal to the logic control unit; and a ramp wave generating unit coupled to the logic control unit, receiving the fourth control signal, the error signal, and a second threshold voltage, and generating the first slope according to the fourth control signal And a wave signal, and outputting the second control signal to the logic control unit according to the first ramp signal and the error signal. The time generator of claim 1, wherein the first ramp signal generated by the ramp generating unit and the second ramp signal generated by the time adjusting unit have the same absolute value of the falling slope. . The time generator of claim 1, wherein the logic control unit comprises: a first switch, the control end receiving the comparison signal, the second end of which is coupled to a ground end; and a second switch The control terminal receives the first control signal, and the second end thereof is coupled to the ground end; a first inverter having an input end coupled to the first end of the first switch, an output end coupled to the first end of the second switch, and a second inverter coupled to the input end a first end of the second switch, the output end of which is coupled to the first end of the first switch, wherein the first inverter, the coupling of the second inverter and the first switch generates the third control signal . The time generator of claim 1, wherein the logic control unit comprises: a third switch, the control end receives the first control signal, the second end of which is coupled to a ground end; and a fourth switch The control end receives the second control signal, and the second end is coupled to the ground end; a third inverter has an input end coupled to the first end of the third switch, and an output end coupled to the fourth end a first end of the switch; and a fourth inverter having an input end coupled to the first end of the fourth switch, the output end coupled to the first end of the third switch, wherein the third inverter, The fourth control signal is generated by the coupling of the fourth inverter and the third switch. The time generator of claim 1, wherein the time adjustment unit comprises: a first amplifier, the first input end receives the error signal, and the second input end is coupled to the output end thereof; a switch, the control terminal receives the third control signal, the first end of which is coupled to the output end of the first amplifier; a first capacitor, the first end of which is coupled to the second end of the fifth switch, and the second end thereof Coupling a ground terminal; a first current source connected in parallel with the first capacitor, wherein the first current source and the first end of the first capacitor are coupled to generate the second ramp signal; and a second comparator, the first An input receives the first threshold voltage, a second input receives the second ramp signal, and an output terminal outputs the first control signal. The time generator of claim 1, wherein the ramp generating unit comprises: a second amplifier, the first input terminal receiving the second threshold voltage, and the second input end coupled to the output end thereof; a sixth switch, the control terminal receives the fourth control signal, the first end of which is coupled to the output end of the second amplifier; the second capacitor has a first end coupled to the second end of the sixth switch, The second end is coupled to a ground end; a second current source is connected in parallel with the second capacitor, wherein the first ramp signal is coupled to the first end of the second capacitor to generate the first ramp signal; And a third comparator, the first input end receives the error signal, the second input end receives the first ramp signal, and the output end outputs the second control signal. The time generator of claim 1, wherein the relationship between the first threshold voltage and the second threshold voltage used by the time generator is as follows: the error signal is a variable signal, The second threshold voltage is greater than the error signal, and the error signal is greater than the first threshold voltage. The time generator of claim 1, wherein the difference between the first threshold voltage and the second threshold voltage is a fixed value. The time generator of claim 1, wherein the logic control The pulse width modulation signal output by the unit is a fixed value of an on-time and an off-time in each cycle. The time generator of claim 1, wherein the time generator determines a conduction in a period of the pulse width modulation signal according to the error signal, the first ramp signal, and the first threshold voltage. Time, and determining an off time in the cycle according to the error signal, the second ramp signal, the first threshold voltage, and the second threshold voltage.