TWM458595U - Memory connection structure of storage device - Google Patents

Description

Memory connection structure of the storage device

This creation is related to storage devices, and in particular to improvements in the memory connection architecture used within the storage device.

Generally, in a storage device composed of a volatile memory, volatile memory is usually connected in series in a series connection, so that when data is accessed, It is easy to have problems with signal reflection.

As shown in the first figure and the second figure, respectively, the first memory architecture diagram and the second memory architecture diagram of the prior art. As shown in the figure, a storage device mainly has a control wafer 11, a bus bar 12 and a plurality of volatile memories 13, wherein the control wafer 11 is connected in series to the plurality of volatile memories 13 through a single bus bar 12. . As shown in the first figure, when the control wafer 11 accesses the first volatile memory 13, although the other volatile memory 13 is not accessed, there is still a small current 21 flowing to each of the volatiles. Sexual memory 13. Moreover, when the length of the bus bar 12 is longer (that is, the more the number of the volatile memory bodies 13 connected in series on the bus bar 12), the current 21 that can be accommodated behind it is larger.

In this way, as shown in the second figure, since the volatile memory 13 at the rear does not perform the data access operation, the currents 21 are reflected back to form a reflected current 22, which is a signal. The phenomenon of reflection. As described above, the greater the number of the volatile memory 13 connected in series on the bus bar 12, the larger the current 21 that can be accommodated behind it, so that the reflected current 22 reflected back is larger. As a result, the reflected currents 22 will interfere with the original access signals and data, and even cause errors in signals and data.

In view of the above problems, an On-Die Termination (ODT) technique has been proposed to solve the problem of signal reflection. Generally, to use the ODT technology, the volatile memory 13 has an ODT pin built in, so that the control chip 11 can activate the ODT function of the volatile memory 13 through the ODT pin (for example, DDR3 is built-in). Have ODT function). After the ODT function is activated, a resistor having a specific resistance value is simulated in the volatile memory 13 so that when the volatile memory 13 receives the current 21, it will be directed to the resistor instead of It will be reflected back and form the reflected current 22.

However, when the volatile memory 13 turns on the ODT function, the overall power consumption of the storage device increases, resulting in an increase in power consumption and an increase in overall temperature. According to the experiment of the applicant, it was found that the volatile memory 13 was continuously accessed for 30 minutes under the indoor temperature of 23 degrees, and the average temperature of the volatile memory 13 was 33 degrees when the ODT function was turned off. . The average current consumption of the volatile memory 13 is 1.1A, the average power is 1.65W, and the average current consumption of the volatile memory 13 is 1.2A, and the average power is 1.8W. On the other hand, in the case where the ODT function is enabled, the average temperature of the volatile memory 13 is 37.9 degrees. The average current consumption of the volatile memory 13 is 1.2A, the average power is 1.8W, and the average current consumption of the volatile memory 13 is 2.8A, and the average power is 4.2W.

As described above, although the problem caused by reflection can be effectively solved by the ODT function, the high temperature and high power consumption associated with turning on the ODT function are quite troublesome for those skilled in the art. In view of this, how to solve the existing reflection problem by techniques other than ODT, that is, a problem that is studied by those skilled in the art.

The main purpose of the present invention is to provide a memory connection structure of a storage device, which can solve the problem that the original signal generates noise or causes signal interference by changing the connection structure of the memory.

To achieve the above objective, the present invention provides a storage device including a circuit substrate, a memory controller, a bus bar and a memory module, wherein the memory controller, the bus bar and the memory module They are electrically connected to the circuit substrate. The memory module is composed of a plurality of memory slots and a plurality of volatile memories, and the plurality of volatile memories are respectively connected to the same bus bar through the corresponding memory slots, and are connected to the memory controller through the bus bars. Wherein, the bus bar has more than one contact, and each contact is connected to two memory slots. The two memory slots connected to the same contact are respectively disposed at corresponding positions on the front and back sides of the circuit substrate, and the distance between the two memory slots and the memory controller is equal.

The technical effect achieved by the present invention in comparison with the related art is that two upper and lower relative memory slots and volatile memory are disposed on the same contact of the bus bar, when signal reflection occurs. Most of the current reflected above can cancel out the current reflected by the lower side, leaving only a small current that does not interfere with the access signal. In this way, even if the memory device that does not have the On-Die Termination (ODT) function is used in the storage device of the present invention, or the ODT function built in the memory is not turned on, the problem of signal reflection can be solved. Moreover, the storage device of the present invention can save more power than the related art storage device without using the ODT function, and maintain a lower and stable working temperature.

Furthermore, the connection structure of the present invention can effectively eliminate the current reflected by the volatile memory, so that more sets of volatile memory can be connected to the same busbar, thereby effectively increasing the load of the storage device. Storage capacity.

11‧‧‧Control chip

12‧‧‧ Busbar

13‧‧‧ volatile memory

21‧‧‧ Current

22‧‧‧reflecting current

3, 5‧‧‧ storage devices

31‧‧‧ circuit board

311‧‧‧ positive

312‧‧‧ back

32‧‧‧Transport interface

33‧‧‧ memory controller

34‧‧‧ memory module

341‧‧‧ memory slot

3411‧‧‧First memory slot

3412‧‧‧Second memory slot

3413‧‧‧ third memory slot

3414‧‧‧4th memory slot

342‧‧‧ volatile memory

3421‧‧‧First memory

3422‧‧‧Second memory

3423‧‧‧ Third memory

3424‧‧‧ fourth memory

35‧‧‧Backup memory module

351‧‧‧ Non-volatile memory

36‧‧‧Power supply unit

37‧‧‧ Busbar

4‧‧‧Computer host

41‧‧‧Computer motherboard

42‧‧‧PCI-E slot

43‧‧‧Links

51‧‧‧First transmission interface

52‧‧‧Second transmission interface

6‧‧‧Backup storage device

61‧‧‧Internal transmission line

7‧‧‧External transmission line

A, B, C, D‧‧‧ joints

L, L1, L2‧‧‧ distance

The first figure is a first memory architecture diagram of the prior art.

The second figure is a second memory architecture diagram of the prior art.

The third figure is the front view of the storage device configuration diagram of the first embodiment of the creation.

The fourth figure is the back of the storage device configuration diagram of the first embodiment of the creation.

The fifth figure is a schematic diagram of the storage device setup of the first embodiment of the present invention.

Figure 6 is a block diagram of a storage device of the first embodiment of the present invention.

The seventh figure is a first memory architecture diagram of the first specific embodiment of the creation.

The eighth figure is a second memory architecture diagram of the first embodiment of the creation.

The ninth figure is a first memory architecture diagram of the second embodiment of the creation.

The tenth figure is a second memory architecture diagram of the second embodiment of the creation.

Figure 11 is a block diagram of a storage device of a third embodiment of the present invention.

Figure 12 is a schematic view showing the arrangement of the storage device of the third embodiment of the present invention.

For a more detailed understanding of the features and technical aspects of the present invention, reference should be made to the description and the accompanying drawings.

Referring to the third to sixth figures, respectively, the front view of the storage device configuration diagram, the back of the storage device configuration diagram, the storage device setting diagram, and the storage device block diagram of the first embodiment of the present creation. As shown in the figure, the storage device 3 of the present invention mainly comprises a circuit substrate 31, a memory controller 33 (hereinafter referred to as the controller 33 in the specification), a memory module 34 and a bus bar ( The bus bar 37 is shown in FIG. 7 , wherein the controller 33 , the memory module 34 , and the bus bar 37 are respectively disposed on the circuit substrate 31 . The circuit board 31 has a transmission interface 32. More specifically, the transmission interface 32 can be a Peripheral Component Interconnect Express (PCI-E) transmission interface. The storage device is inserted through the transmission interface 32. A PCI-E slot 42 is connected to an external computer motherboard 41 for signal transmission with the computer motherboard 41. However, the above description is only a preferred embodiment and should not be limited thereto.

The controller 33 is electrically connected to the transmission interface 32 through the circuit board 31, thereby communicating with the computer motherboard 41 through the transmission interface 32, and then receiving the control command issued by the computer host 41, and the memory is accordingly The body module 34 performs an access operation.

The bus bar 37 is electrically connected to the controller 33 through the circuit substrate 31. The memory module 34 is electrically connected to the bus bar 37 through the circuit board 31, thereby communicating with the controller 33 through the bus bar 37. In other words, the storage device 3 serves as the signal transmission bridge between the controller 33 and the memory module 34. It should be noted that, in this embodiment, the storage device 3 accesses all the materials in the memory module 34 by using a single bus bar 37.

The memory module 34 is mainly composed of at least two memory slots 341 and at least two volatile memory (Volatile memory) 342. In this embodiment, the memory slot 341 can be, for example, a small-sized dual-column memory module. The Small Outline Dual In-line Memory Module (SO-DIMM) socket, and the volatile memory 342 can be, for example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Jiake is DDR3 memory. However, the above description is only a preferred embodiment of the present invention and should not be limited thereto. The memory slot 341 is disposed on the circuit board 31 and electrically connected to the bus bar 37 via the circuit board 31. The volatile memory 342 is inserted into the memory slot 341, whereby the volatile memory 342 receives the control signal from the busbar 37 through the memory slot 341, and passes the memory. The body slot 341 transfers data to the bus bar 37.

As shown in the third and fourth figures, the circuit board 31 has a front surface 311 and a rear surface 312. The at least two memory slots 341 and the at least two volatile memory bodies 342 can be respectively disposed on the circuit substrate 31. The front side 311 and the back side 312. The number of the memory slots 341 provided on the front surface 311 of the circuit board 31 is the same as the number of the memory slots 341 provided on the back surface 312 of the circuit board 31. As shown in the figure, two memory slots 341 are disposed on the front surface 311, and two memory slots 341 are disposed on the back surface 312 as an example, but are not limited thereto.

More specifically, each of the memory slots 341 on the front surface 311 has a corresponding memory slot 341 disposed at a relative position on the back surface 312. The distance between the two memory slots 341 and the controller 33 is equal. As shown in the third and fourth figures, the memory slot 341 and the controller 33 on the front surface 311 are The distance is L, and the distance between the other memory slot 341 corresponding to the back surface 312 and the controller 33 is also L, and the distance between the two is equal.

The storage device 3 further includes a power supply unit 36 disposed on the circuit substrate 31, and electrically connected to the controller 33 and the memory module 34 via the circuit substrate 31, thereby providing the controller 33 and the memory. The body module 34 operates with the required power. In this embodiment, the power supply unit 36 is mainly exemplified by a battery. In another embodiment, the power supply unit 36 can also be a power line connector, and the storage device 3 can be connected to an external power line through the power line connector to obtain the power required for the operation of the storage device 3, where It is not limited to the above embodiment.

The storage device 3 further includes a backup memory module 35 disposed on the circuit substrate 31 and electrically connected to the controller 33 via the circuit substrate 31. The backup memory module 35 is mainly composed of a plurality of non-volatile memory 351. In this embodiment, the plurality of non-volatile memory 351 can be, for example, a flash memory (Flash). Memory), but not limited.

In the present invention, the storage device 3 mainly uses the volatile memory 342 in the memory module 34 as a main storage medium. The characteristics of the volatile memory 342 are: the data disappears after the power is turned off. In other words, the access speed of the volatile memory 342 is fast, but after the storage device 3 is powered off, the data stored in the volatile memory 342 will disappear, which will cause the user to Inconvenience. Although the access speed of the non-volatile memory 351 is slightly slower than the volatile memory 342, the non-volatile memory 351 has the characteristic that the data remains after the power is turned off. Therefore, the present invention uses the non-volatile memory 351 as a backup storage medium to avoid the problem that all the data in the volatile memory 342 disappears due to the power-off of the storage device 3.

In the present invention, the storage device 3 is connected to the computer motherboard 41 through the transmission interface 32, thereby receiving data from the computer motherboard 41, and writing data to the volatile memory via the control of the controller 33. 342. It is to be noted that the volatile memory 342 may be a plurality of independent storage spaces for storing different data respectively; or the volatile memory 342 may also constitute a memory having a large storage space. Module 34. Taking thirty of the volatile memory 342 as an example, the controller 33 can treat the complex volatile memory 342 as thirty independent storage spaces (for example, thirty hard disks), or as one single 30 times the capacity of the storage space (such as a large capacity hard disk), but not limited.

As shown in the sixth figure, the controller 33 is electrically connected to the memory module 34 and the backup memory module 35 at the same time. The controller 33 mainly stores the data in the memory module 34, and the controller 33 controls the memory module 34 to volatilize when necessary (for example, before the storage device 3 is powered off). The data in the memory 342 is backed up and stored in the backup memory module 35, thereby avoiding the problem of data disappearing due to power failure. Moreover, the controller 33 also controls the backup memory module 35 to restore the backup data in the non-volatile memory 351 to the same when needed (for example, when the storage device 3 is powered on again). In the memory module 34, the volatile memory 342 is used to allow the user to obtain extremely fast data access speed.

Continuing to refer to the seventh and eighth figures, respectively, the first memory architecture diagram and the second memory architecture diagram of the first embodiment. In the present invention, the controller 33 mainly connects all of the memory slots 341 through a single bus bar 37, and accesses the volatile memory 342 through the memory slots 341. As shown in the seventh and eighth figures, the bus bar 37 has more than one contact, and a contact A and a contact B are taken as an example, but are not limited. Each of the contacts A and B on the bus bar 37 is connected to the upper and lower memory slots 341, and respectively accesses the upper and lower corresponding volatilizations through the two memory slots 341. Sex memory 342. The two memory slots 341 connected to the same contact are respectively disposed on corresponding positions on the front surface 311 and the back surface 312 of the circuit substrate 31, and the two memory slots 341 and the controller are respectively disposed. The distance between 33 is equal.

For example, in the seventh figure, a first memory slot 3411 and a second memory slot 3412 are connected to a contact A on the bus bar 37, wherein the first memory slot 3411 is plugged into a first A memory 3421, the second memory slot 3412 is plugged into a second memory 3422. The first memory slot 3411 and the second memory slot 3412 are respectively disposed at corresponding positions on the front surface 311 and the back surface 312 of the circuit substrate 31, and the first memory slot 3411 and the controller are The distance between 33 and the distance between the second memory slot 3412 and the controller 33 are equal.

A third memory slot 3413 and a fourth memory slot 3414 are also disclosed in the seventh figure. The third memory slot 3413 and the fourth memory slot 3414 are connected to the busbar 37. A contact B is inserted, and the third memory slot 3413 is plugged into a third memory 3423. The fourth memory slot 3414 is plugged into a fourth memory 3424. Similarly, the third memory slot 3413 and the fourth memory slot 3414 are respectively disposed at corresponding positions on the front surface 311 and the back surface 312 of the circuit substrate 31, and the third memory slot 3413 is The distance between the controllers 33 and the distance between the fourth memory slot 3414 and the controller 33 are equal.

Therefore, as shown in the seventh figure, when the controller 33 accesses the first memory 3421, a slight current flows to the second memory 3422, the third memory 3423, and the fourth memory. 3424. When the signal reflection phenomenon occurs, the second memory 3422, the third memory 3423, and the fourth memory 3424 do not perform data access operations, so the current flowing back is reflected back. . The above-mentioned signal reflection phenomenon is a common knowledge in the art, and will not be described herein.

As shown in the eighth embodiment, in this embodiment, since the contacts B are respectively connected to the upper and lower memory slots (ie, the third memory slot 3413 and the fourth memory slot 3414), The distance between the third memory slot 3413 and the controller 33 is equal to the distance between the fourth memory slot 3414 and the controller 33, and therefore, the third memory 3423 reflects The current, which coincides with the current reflected by the fourth memory 3424, cancels each other out. In other words, the current reflected by the third memory 3423 and the fourth memory 3424 does not flow back to the controller 33; or, after the currents of the two are canceled each other, only the bottom is tiny, and the pair is not The signal produces a disturbing current and flows back to the controller 33.

It is worth mentioning that the present invention mainly uses the special connection structure of the volatile memory 342 (and the memory slots 341) to allow the upper and lower two volatile memories of the busbar 37 to be connected. The currents reflected by body 342 can cancel each other out. Therefore, in the present creation, the number of the memory slots 341 and the volatile memory 342 are mainly dominated by a double number.

Please refer to the ninth and tenth drawings at the same time, which are respectively the first memory architecture diagram and the second memory architecture diagram of the second embodiment of the creation. In the above embodiments of the seventh and eighth embodiments, the number of the memory slots 341 and the number of the volatile memory 342 are mainly four. As shown in the ninth and tenth embodiments, in another embodiment, the number of the memory slots 341 is preferably eight, and the number of the volatile memory 342 is preferably eight. And the bus bar 37 preferably has at least four contacts A, B, C, D. The four contacts A, B, C, and D are respectively connected to the upper and lower two sets of the memory slots 341, and the upper and lower two corresponding volatiles are respectively accessed through the two memory slots 341. Memory 342.

As shown in the ninth and tenth diagrams, when the controller 33 accesses one of the volatile memories 342 on the contact A, current also flows to the other seven of the volatile memories 342, however When the phenomenon of signal reflection occurs, the currents reflected by the upper and lower two sets of volatile memory 342 of the contact B can cancel each other, and the current reflected by the upper and lower sets of volatile memory 342 of the contact C is just The currents reflected by the upper and lower sets of volatile memory 342 of the contact D can cancel each other out. In other words, most of the reflected current can be cancelled out, even if there is still current flowing back to the controller 33, but only a very small current that will not interfere with the signal will flow back to the controller. 33. Therefore, the control command issued by the controller 33 and the accessed data are not disturbed by noise and cause an error.

It can be seen from the above description that the volatile memory 342 does not need to have the function of On-Die Termination (ODT) by the memory connection architecture disclosed in the present invention. Even if the volatile memory 342 has built-in ODT function (for example, DDR3 has built-in ODT function), the ODT function does not need to be enabled, and the storage device 3 can also overcome the problem of signal reflection. . In this way, the power consumption of the storage device 3 does not increase, and thus the power can be saved compared with the homogeneous storage device (the ODT function is required to overcome the signal reflection problem). Moreover, since the volatile memory 342 does not have the ODT function or the ODT function is not enabled, the temperature of the storage device 3 can be lower than that of the homogenous storage device, thereby making the operating temperature of the storage device 3 more stable.

Continuing to refer to the eleventh and twelfth drawings, respectively, a block diagram of a storage device and a storage device arrangement diagram of a third embodiment of the present invention. Another storage device 5 is disclosed in this embodiment. The storage device 5 differs from the storage device 3 shown in the sixth figure in that, in addition to the components shown in the sixth figure, the storage device 5 may include The first transmission interface 51 and the at least one second transmission interface 52, the storage device 5 can be connected to the external computer motherboard 51 through the first transmission interface 51, and can be connected to the backup through the second transmission interface 52. Storage device 6. The second transmission interface 52 is disposed on the circuit substrate 31, and is electrically connected to the controller 33 and the memory module 34 through the circuit substrate 31. The backup storage device 6 passes through the second transmission interface 52. The controller 33, the memory module 34 and the backup memory module 35 are electrically connected.

In this embodiment, the second transmission interface 52 is mainly a Serial Advance Technology Attachment (SATA) transmission interface, and the storage device 5 is connected to an internal transmission line 61 through the second transmission interface 52 (for example, A SATA transmission line) is electrically connected to the backup storage device 6 through the internal transmission line 61. It is worth mentioning that the backup storage device 6 can include at least one hard disk (such as a magnetic head read hard disk or a solid state hard disk, etc.). The storage device 5 is connected to the backup storage device 6 through the second transmission interface 52, so that the data stored in the memory module 34 can be backed up to the backup storage device 6. Alternatively, the backup memory can be configured. The data inside the group 35 is copied to the backup storage device 6. In this way, the backup space of the data can be effectively improved.

Furthermore, the backup storage device 6 can also be composed of a plurality of hard disks, and the number of the second transmission interfaces 52 can be two or more (as exemplified by two in the figure). Therefore, the storage device 5 can back up the data in the memory module 34 by using a plurality of the second transmission interfaces 52 in a Redundant Array of Independent Disks (RAID) manner. The plurality of hard disks in the backup storage device 6; in addition, the storage device 5 can also copy the data in the backup memory module 35 to the backup storage device 6 in a RAID manner. In this way, the data backup speed can be effectively improved. The number of hard disks in the backup storage device 6 and the number of the second transmission interface 52 can be set according to actual needs, and should not be limited.

In this way, when the memory module 34 and/or the backup memory module 35 are damaged, or the storage space is insufficient, the backup storage device 6 can be used for data backup, and the RAID can also be used. Improve the backup speed of data. Finally, the storage device 5 controls the backup storage device 6 through the controller 33 to restore the internal backup data to the memory module 34 or the backup memory module 35.

It should be noted that the backup storage device 6 can also be configured as a separate hard disk, and is connected to the computer motherboard 41 through the first transmission interface 51 and the second transmission interface 52 to receive and transmit. data. However, this is only another embodiment of the present invention and is not limited thereto.

In the foregoing embodiment, the storage device 3 is directly inserted into the PCI-E slot 42 of the computer motherboard 41. In other words, the storage device 3 is built in the computer motherboard 41. In the computer host (such as the computer host 4 shown in Figure 12). However, as shown in the twelfth figure, the storage device 3, 5 can also be implemented in an external type for the convenience of the user. In this embodiment, the first transmission interface 51 is mainly an External Serial Advance Technology Attachment (e-SATA) transmission interface or a universal serial bus 3.0 (Universal Serial Bus 3.0, USB3. 0) The transmission interface is implemented, but is not limited. In this way, the storage device 3, 5 can be connected to an external transmission line 7 (such as an e-SATA transmission line or a USB transmission line, etc.) through the first transmission interface 51, and connected to the computer motherboard 41 through the external transmission line 7. A corresponding port 埠43 is connected to establish a connection with the host computer 4.

The above is only a specific description of a preferred embodiment of the present invention, and is not intended to limit the scope of the patents of the present invention, and any other equivalent transformations are within the scope of the patent application described below.

33‧‧‧ memory controller

3411‧‧‧First memory slot

3412‧‧‧Second memory slot

3413‧‧‧ third memory slot

3414‧‧‧4th memory slot

3421‧‧‧First memory

3422‧‧‧Second memory

3423‧‧‧ Third memory

3424‧‧‧ fourth memory

37‧‧‧ Busbar

A, B‧‧‧ contacts

L1, L2‧‧‧ distance

Claims (12)

A memory connection architecture of a storage device, comprising:
a circuit substrate having a front surface and a back surface, and the circuit substrate has a transmission interface through which the storage device is connected to an external computer motherboard;
a memory controller disposed on the circuit substrate and electrically connected to the transmission interface through the circuit substrate;
a bus bar disposed on the circuit substrate and electrically connected to the memory controller through the circuit substrate, the bus bar having more than one contact;
a memory module is disposed on the circuit substrate and electrically connected to the bus bar through the circuit substrate, wherein the memory module is composed of at least two memory slots and at least two volatile memories, the at least two volatilization The sexual memory is respectively connected to the same bus bar through the corresponding memory slot;
Each of the contacts on the bus bar is connected to two memory slots, and respectively accesses the corresponding volatile memory through the two memory slots, wherein the same one is connected to the same The two memory slots are respectively disposed at corresponding positions on the front surface and the back surface of the circuit substrate, and the distance between the two memory slots and the memory controller is equal. The memory connection architecture of the storage device of claim 1, wherein the number of the at least two memory slots and the at least two volatile memories is a double number. The memory connection architecture of the storage device of claim 2, wherein the number of the at least two memory slots is eight, the number of the at least two volatile memories is eight, and the bus bar has at least four connections. Point, wherein each of the contacts is connected to the upper and lower two memory slots, and the upper and lower two volatile memories are respectively accessed through the two memory slots. The memory connection architecture of the storage device of claim 2, wherein the transmission interface is a Peripheral Component Interconnect Express (PCI-E) transmission interface, and an external serial Advance Technology Attachment (External Serial Advance Technology Attachment, e-SATA) One of the transmission interface and Universal Serial Bus 3.0 (USB3.0) transmission interface. The memory connection architecture of the storage device of claim 2, wherein the memory slot is a Small Outline Dual In-line Memory Module (SO-DIMM) socket, the volatile memory It is a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The memory connection structure of the storage device of claim 2, further comprising a power supply unit disposed on the circuit substrate and electrically connected to the memory controller and the memory module through the circuit substrate. The memory connection architecture of the storage device of claim 6, wherein the power supply unit is a battery or a power cord connector. The memory connection structure of the storage device of claim 2, further comprising a backup memory module disposed on the circuit substrate and electrically connected to the memory controller through the circuit substrate, wherein the backup memory The body module is composed of a plurality of non-volatile memory, and the memory controller controls the memory module to store the at least two volatile memory data in the backup memory module and control the backup memory. The body module restores the backup data in the plurality of non-volatile memory to the memory module. The memory connection architecture of the storage device of claim 8, wherein the plurality of non-volatile memory is a flash memory. The memory connection architecture of the storage device of claim 8, wherein the method further comprises:
The at least one second transmission interface is disposed on the circuit substrate, and is electrically connected to the memory controller and the memory module through the circuit substrate; and a backup storage device electrically connected to the second transmission interface The second transmission interface is electrically connected to the memory controller, the memory module, and the backup memory module;
The memory controller controls the memory module or the backup memory module to store the internal data backup to the backup storage device, and control the backup storage device to restore the internal backup data to the The memory module or the backup memory module. The memory connection architecture of the storage device of claim 10, wherein the second transmission interface is a Serial Advance Technology Attachment (SATA) transmission interface. The memory connection architecture of the storage device of claim 11, wherein the backup storage device is composed of a plurality of hard disks, and the number of the second transmission interfaces is two or more, and the memory controller uses the plurality of The second transmission interface stores the data in the memory module or the backup memory module in the backup storage device in the form of a Redundant Array of Independent Disks (RAID).