TWM452456U - 光源模組 - Google Patents

光源模組 Download PDF

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Publication number
TWM452456U
TWM452456U TW101224443U TW101224443U TWM452456U TW M452456 U TWM452456 U TW M452456U TW 101224443 U TW101224443 U TW 101224443U TW 101224443 U TW101224443 U TW 101224443U TW M452456 U TWM452456 U TW M452456U
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Taiwan
Prior art keywords
light
light source
source module
emitting diode
blank
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TW101224443U
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English (en)
Inventor
Cheng-Yen Chen
Yun-Li Li
Yi-Hao Huang
sheng-yuan Sun
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Genesis Photonics Inc
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Publication date
Application filed by Genesis Photonics Inc filed Critical Genesis Photonics Inc
Priority to TW101224443U priority Critical patent/TWM452456U/zh
Priority to CN2013200790383U priority patent/CN203192794U/zh
Publication of TWM452456U publication Critical patent/TWM452456U/zh
Priority to US13/904,027 priority patent/US9012929B2/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

光源模組
本創作是有關於一種光源模組,且特別是有關於一種以發光二極體晶片作為光源之光源模組。
發光二極體具有諸如壽命長、體積小、高抗震性、低熱產生及低功率消耗等優點,因此已被廣泛應用於家用及各種設備中的指示器或光源。近年來,發光二極體已朝高功率發展,因此其應用領域已擴展至道路照明、大型戶外看板、交通號誌燈及相關領域。在未來,發光二極體甚至可能成為兼具省電及環保功能的主要照明光源。
一般來說,發光二極體光源模組是將多個發光二極體晶片以矩陣排列的方式配置於基板上。然而,相鄰兩發光二極體晶片所發出的側向光會被彼此所吸收,因而導致發光二極體晶片所發出的側向光無法被利用,進而降低發光二極體光源模組的出光效率。
本創作提供一種光源模組,具有位於發光二極體晶片之間的空白晶片,可將發光二極體晶片之側向的光重新導向。
本創作提出一種光源模組,包括一基板、至少二發光二極體晶片以及至少一空白晶片。發光二極體晶片配置於 基板上。空白晶片配置於基板上,且位於發光二極體晶片之間。發光二極體晶片、空白晶片以及基板電性連接。空白晶片用以將來自發光二極體晶片之側向的光重新導向。
在本創作之一實施例中,上述之基板包括一透明基板。
在本創作之一實施例中,上述之每一空白晶片的剖面輪廓包括梯形、矩形、錐形或側壁為弧形之四邊形。
在本創作之一實施例中,上述之每一空白晶片的側壁的反射率大於85%。
在本創作之一實施例中,上述之每一空白晶片的側壁為一粗糙表面。
在本創作之一實施例中,上述之每一空白晶片與相鄰之發光二極體晶片之間相隔一距離,且距離介於0.5H至Htan(θ/2)之間,其中H為發光二極體晶片的高度,θ為發光二極體晶片的最大出光角。
在本創作之一實施例中,上述之距離介於H至6H之間。
在本創作之一實施例中,上述之每一空白晶片具有一第一電極與一第二電極,且每一空白晶片透過第一電極與第二電極與基板電性連接。
在本創作之一實施例中,上述之空白晶片包括多個覆晶式空白晶片。
在本創作之一實施例中,上述之發光二極體晶片包括多個覆晶式發光二極體晶片。
在本創作之一實施例中,上述之發光二極體晶片發出相同顏色的光或不同顏色的光。
基於上述,由於本創作之光源模組具有位於發光二極體晶片之間的空白晶片,因此發光二極體晶片之側向的光不但不會被空白晶片所吸收,且會被空白晶片透過反射而重新導向。如此一來,本創作之光源模組可具有較佳的出光效率。
為讓本創作之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A繪示為本創作之一實施例之一種光源模組的俯視示意圖。圖1B繪示為沿圖1A之線I-I’的剖面示意圖。請先參考圖1A,在本實施例中,光源模組100a包括一基板110、至少二發光二極體晶片120(圖1A中僅示意地繪示五個)以及至少一空白晶片130a(圖1A中僅示意地繪示四個)。詳細來說,發光二極體晶片120配置於基板110的一上表面112上。空白晶片130a配置於基板110的上表面112上,且位於發光二極體晶片120之間。發光二極體晶片120、空白晶片130a以及基板110電性連接。特別是,空白晶片130a用以將來自發光二極體晶片120之側向的光重新導向。
更具體來說,基板110例如是一透明基板,其中基板110的上表面112上具有多個接墊(未繪示),而基板110 的外形輪廓例如是圓形,但並不以此為限。發光二極體晶片120的電極122、124則配置於基板110的接墊上,並透過接墊與基板110電性連接。此處,發光二極體晶片120例如是多個覆晶式發光二極體晶片。發光二極體晶片120可發出相同顏色的光或不同顏色的光。此外,空白晶片130a的側壁為一粗糙表面,其中粗糙表面由粒子塗佈(coating)、轟擊(bomboard)、濺鍍(sputter)、電漿處理(plasma)或氧化處理(Ozone)所製得。較佳地,本實施例之空白晶片130a的側壁的反射率可大於85%。
特別是,請參考圖1B,本實施例之每一空白晶片130a與相鄰之發光二極體晶片120之間相隔一距離b,且距離b介於0.5H至Htan(θ/2)之間,其中H為發光二極體晶片120的高度,θ為發光二極體晶片120的最大出光角。較佳地,距離b介於H至6H之間。每一空白晶片130a具有一第一電極132a與一第二電極134a,且每一空白晶片130a透過第一電極132a與第二電極134a與基板110的接墊(未繪示)電性連接。此處,空白晶片130a例如是多個覆晶式空白晶片。每一空白晶片130a的剖面輪廓例如是矩形。需說明的是,此處之空白晶片130a是指不具有發光功效的晶片。此外,如圖1所示,發光二極體晶片120與空白晶片130a例如是呈矩陣排列,但並不以此為限。
由於本實施例之光源模組100a具有位於發光二極體晶片120之間空白晶片130a,因此發光二極體晶片120之側向的光不但不會被空白晶片130a所吸收,且會被空白晶 片130a透過反射而重新導向。也就是說,發光二極體晶片120之側向的光照射至空白晶片130a後,空白晶片130a會直接將光反射出去。如此一來,本實施例之光源模組100a可具有較佳的出光效率。
值得一提的是,本創作並不限定空白晶片130a的剖面輪廓,雖然此處所提及的空白晶片130a的剖面輪廓具體化為矩形。但於其他實施例中,請參考圖2,光源模組100b之空白晶片130b的剖面輪廓亦可為梯形;或者是,請參考圖3,光源模組100c之空白晶片130b的剖面輪廓亦可為錐形;或者是,請參考圖4,光源模組100d之空白晶片130d的剖面輪廓亦可為側壁131為弧形之四邊形。上述仍屬於本創作可採用的技術方案,不脫離本創作所欲保護的範圍。
綜上所述,由於本創作之光源模組具有位於發光二極體晶片之間空白晶片,因此發光二極體晶片之側向的光不但不會被空白晶片所吸收,且會被空白晶片透過反射而重新導向。如此一來,本創作之光源模組可具有較佳的出光效率。
雖然本創作已以實施例揭露如上,然其並非用以限定本創作,任何所屬技術領域中具有通常知識者,在不脫離本創作之精神和範圍內,當可作些許之更動與潤飾,故本創作之保護範圍當視後附之申請專利範圍所界定者為準。
100a、100b、100c、100d‧‧‧光源模組
110‧‧‧基板
112‧‧‧上表面
120‧‧‧發光二極體晶片
122、124‧‧‧電極
130a、130b、130c、130d‧‧‧空白晶片
131‧‧‧側壁
132a‧‧‧第一電極
134a‧‧‧第二電極
b‧‧‧距離
圖1A繪示為本創作之一實施例之一種光源模組的俯 視示意圖。
圖1B繪示為沿圖1A之線I-I’的剖面示意圖。
圖2繪示為本創作之一實施例之一種光源模組的剖面示意圖。
圖3繪示為本創作之另一實施例之一種光源模組的剖面示意圖。
圖4繪示為本創作之又一實施例之一種光源模組的剖面示意圖。
100a‧‧‧光源模組
110‧‧‧基板
112‧‧‧上表面
120‧‧‧發光二極體晶片
130a‧‧‧空白晶片
b‧‧‧距離

Claims (11)

  1. 一種光源模組,包括:一基板;至少二發光二極體晶片,配置於該基板上;以及至少一空白晶片,配置於該基板上,且位於該些發光二極體晶片之間,其中該些發光二極體晶片、該些空白晶片以及該基板電性連接,該空白晶片用以將來自該些發光二極體晶片之側向的光重新導向。
  2. 如申請專利範圍第1項所述之光源模組,其中該基板包括一透明基板。
  3. 如申請專利範圍第1項所述之光源模組,其中各該空白晶片的剖面輪廓包括梯形、矩形、錐形或側壁為弧形之四邊形。
  4. 如申請專利範圍第1項所述之光源模組,其中各該空白晶片的側壁的反射率大於85%。
  5. 如申請專利範圍第1項所述之光源模組,其中各該空白晶片的側壁為一粗糙表面。
  6. 如申請專利範圍第1項所述之光源模組,其中各該空白晶片與相鄰之該發光二極體晶片之間相隔一距離,且該距離介於0.5H至Htan(θ/2)之間,其中H為該發光二極體晶片的高度,θ為該發光二極體晶片的最大出光角。
  7. 如申請專利範圍第6項所述之光源模組,其中該距離介於H至6H之間。
  8. 如申請專利範圍第1項所述之光源模組,其中各該 空白晶片具有一第一電極與一第二電極,且各該空白晶片透過該第一電極與該第二電極與該基板電性連接。
  9. 如申請專利範圍第1項所述之光源模組,其中該些空白晶片包括多個覆晶式空白晶片。
  10. 如申請專利範圍第1項所述之光源模組,其中該些發光二極體晶片包括多個覆晶式發光二極體晶片。
  11. 如申請專利範圍第1項所述之光源模組,其中該些發光二極體晶片發出相同顏色的光或不同顏色的光。
TW101224443U 2012-12-17 2012-12-17 光源模組 TWM452456U (zh)

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TW101224443U TWM452456U (zh) 2012-12-17 2012-12-17 光源模組
CN2013200790383U CN203192794U (zh) 2012-12-17 2013-02-20 光源模块
US13/904,027 US9012929B2 (en) 2012-12-17 2013-05-29 Light source module

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DE102013207308B4 (de) * 2013-04-23 2023-01-12 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen einer optoelektronischen Baugruppe und optoelektronische Baugruppe
TWI635470B (zh) * 2017-07-04 2018-09-11 錼創科技股份有限公司 發光模組及顯示裝置
KR20200056213A (ko) * 2018-11-14 2020-05-22 서울대학교산학협력단 표시 장치

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JP2004312049A (ja) * 2004-08-05 2004-11-04 Toa Corp 表面実装型発光素子の光漏れ防止構造
JP2008122499A (ja) * 2006-11-09 2008-05-29 Sony Corp 面状光源装置及び液晶表示装置組立体

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CN203192794U (zh) 2013-09-11
US9012929B2 (en) 2015-04-21
US20140167077A1 (en) 2014-06-19

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